Page 1
50 MHz to 6 GHz
FEATURES
True rms response
Excellent temperature stability
Up to 30 dB input dynamic range
50 Ω input impedance
1.25 V rms, 15 dBm, maximum input
Single-supply operation: 2.7 V to 5.5 V
Low power: 3.3 mW at 3 V supply
RoHS-compliant
APPLICATIONS
Measurement of CDMA-, CDMA2000-, W-CDMA-, and QPSK-/
QAM-based OFDM, and other complex modulation
waveforms
RF transmitter or receiver power measurement
GENERAL DESCRIPTION
The ADL5501 is a mean-responding TruPwr™ power detector
for use in high frequency receiver and transmitter signal chains
from 50 MHz to 6 GHz. It is easy to apply, requiring only a single
supply between 2.7 V and 5.5 V and a power supply decoupling
capacitor. The input is internally ac-coupled and has a nominal
input impedance of 50 Ω. The output is a linear-responding dc
voltage with a conversion gain of 6.3 V/V rms at 900 MHz.
The ADL5501 is intended for true power measurement of simple
and complex waveforms. The device is particularly useful for
measuring high crest factor (high peak-to-rms ratio) signals,
such as CDMA-, CDMA2000-, W-CDMA-, and QPSK-/QAMbased OFDM waveforms. The on-chip modulation filter provides
adequate averaging for most waveforms.
TruPwr Detector
ADL5501
5
1
OUTPUT (V)
0.1
0.03
–25 –20 –15 –10 –5 0 5 10 15
Figure 1. Output vs. Input Level, Supply = 3 V, Frequency = 1.9 GHz
The on-chip, 100 Ω series resistance at the output, combined
with an external shunt capacitor, creates a low-pass filter response
that reduces the residual ripple in the dc output voltage. For more
complex waveforms, an external capacitor at the FLTR pin can
be used for supplementary signal demodulation.
The ADL5501 offers excellent temperature stability across a
30 dB range and near 0 dB measurement error across temperature
over the top portion of the dynamic range. In addition to its
temperature stability, the ADL5501 offers low process variations
that further reduce calibration complexity.
The ADL5501 operates from −40°C to +85°C and is available in
a small 6-lead SC-70 package. It is fabricated on a proprietary
high f
silicon bipolar process.
T
INPUT (dBm)
06056-001
FUNCTIONAL BLOCK DIAGRAM
ADL5501
RFIN
TRANSCONDICTANCE
CELLS
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
i
2
x
i
2
x
ERROR
AMP
BAND-GAP
REFERENCE
Figure 2.
100Ω
VPOS
FLTR
VRMS
ENBL
COMM
6056-002
INTERNAL FILTER
CAPACITOR
BUFFER
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
Page 2
ADL5501
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Circuit Description ......................................................................... 17
Filtering ........................................................................................ 17
Applications Information .............................................................. 18
Basic Connections ...................................................................... 18
Output Swing .............................................................................. 18
Linearity ....................................................................................... 18
Input Coupling Using a Series Resistor ................................... 19
Multiple RF Inputs ..................................................................... 19
Selecting the Square-Domain Filter and Output Low-Pass
Filter ............................................................................................. 19
Power Consumption, Enable, and Power-On/Power-Off
Response Time ............................................................................ 20
Output Drive Capability and Buffering ................................... 21
VRMS Output Offset ................................................................. 21
Device Calibration and Error Calculation .............................. 22
Calibration for Improved Accuracy ......................................... 22
Drift over a Reduced Temperature Range .............................. 23
Operation Below 100 MHz ....................................................... 23
Evaluation Board ........................................................................ 23
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
3/09—Rev. A to Rev. B
Change to Features ........................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 4, Figure 5, Figure 7, and Figure 9 ............... 10
Deleted Figure 17 and Figure 21; Renumbered Sequentially ... 12
Changes to Figure 18 and Figure 21 ............................................. 13
Changes to Figure 36 and Figure 39 ............................................. 16
Changes to Figure 42 ...................................................................... 18
Changes to Operation Below 100 MHz Section ......................... 23
Deleted Figure 56 ............................................................................ 22
Deleted Figure 57 ............................................................................ 23
10/07—Rev. 0 to Rev. A
Changes to General Description ..................................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Figure 30, Figure 32, and Figure 33 ......................... 14
Changes to Figure 35, Figure 37, and Figure 38 ......................... 15
Changes to Circuit Description Section ...................................... 16
Changes to Layout and Operation Below 100 MHz and
Above 4.0 GHz Section .................................................................. 22
Inserted Figure 56 ........................................................................... 22
Inserted Figure 57 ........................................................................... 23
Changes to Figure 58 ...................................................................... 23
Deleted Figure 57 and Figure 58 .................................................. 24
Changes to Figure 59 and Figure 60............................................. 24
9/06—Revision 0: Initial Version
Rev. B | Page 2 of 28
Page 3
ADL5501
SPECIFICATIONS
TA = 25°C, VS = 3.0 V, C
Table 1.
Parameter Condition Min Typ Max Unit
FREQUENCY RANGE Input RFIN 50 6000 MHz
RMS CONVERSION (f = 50 MHz) Input RFIN to Output VRMS
Input Impedance 87||6.9 Ω||pF
Input Return Loss 11.0 dB
Dynamic Range
±1 dB Error
1
CW input, −40°C < T
2
V
V
±2 dB Error
2
V
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
3
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 1.81 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.11 V
Temperature Sensitivity PIN = −5 dBm
RMS CONVERSION (f = 100 MHz) Input RFIN to Output VRMS
Input Impedance 78||4.2 Ω||pF
Input Return Loss 12.6 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
1
CW input, −40°C < T
4
2
V
±1 dB Error
2
V
V
±2 dB Error
2
V
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
V
Output Intercept
3
V
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 2.47 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.13 V
Temperature Sensitivity PIN = −5 dBm
= open, C
FLTR
0.03 V
Delta from 25°C, V
V
0.03 V
= 100 nF, unless otherwise specified.
OUT
< +85°C
A
= 3 V 25 dB
S
= 5 V 26 dB
S
= 3 V 32 dB
S
= 5 V 35 dB
S
OUT
25°C ≤ T
−40°C ≤ T
= 3 V 19 dB
S
= 5 V 20 dB
S
= 3 V 23 dB
S
= 5 V 27 dB
S
= 3 V 26 dB
S
= 5 V 30 dB
S
OUT
= 5 V 5.6 7.8 V/V rms
S
= 5 V −0.02 +0.1 V
S
25°C ≤ T
−40°C ≤ T
2
8 dBm
2
−18 dBm
= (gain × VIN) + intercept 4.5 V/V rms
≤ 85°C
A
≤ +25°C
A
< +85°C
A
= 5 V 28 dB
S
2
6 dBm
2
−18 dBm
= (gain × VIN) + intercept 6.1 V/V rms
≤ 85°C
A
≤ +25°C
A
0.0039 dB/°C
−0.0037 dB/°C
0.0028 dB/°C
−0.0018 dB/°C
Rev. B | Page 3 of 28
Page 4
ADL5501
Parameter Condition Min Typ Max Unit
RMS CONVERSION (f = 450 MHz) Input RFIN to Output VRMS
Input Impedance 63||1.4 Ω||pF
Input Return Loss 16.0 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 2.81 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.15 V
Temperature Sensitivity PIN = −5 dBm
RMS CONVERSION (f = 900 MHz) Input RFIN to Output VRMS
Input Impedance 52||0.9 Ω||pF
Input Return Loss 17.5 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 2.53 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.14 V
Temperature Sensitivity PIN = −5 dBm
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.03 V
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.03 V
= 3 V 20 dB
S
= 5 V 24 dB
S
= 3 V 25 dB
S
= 5 V 29 dB
S
= 3 V 28 dB
S
= 5 V 33 dB
S
OUT
25°C ≤ T
−40°C ≤ T
= 3 V 20 dB
S
= 5 V 23 dB
S
= 3 V 24 dB
S
= 5 V 27 dB
S
= 3 V 27 dB
S
= 5 V 30 dB
S
OUT
25°C ≤ T
−40°C ≤ T
2
5 dBm
2
−20 dBm
= (gain × VIN) + intercept 7.1 V/V rms
≤ 85°C
A
≤ +25°C
A
2
6 dBm
2
−18 dBm
= (gain × VIN) + intercept 6.3 V/V rms
≤ +85°C
A
≤ +25°C
A
< +85°C
A
= 5 V 32 dB
S
0.0016 dB/°C
−0.0002 dB/°C
< +85°C
A
= 5 V 33 dB
S
0.0019 dB/°C
−0.0002 dB/°C
Rev. B | Page 4 of 28
Page 5
ADL5501
Parameter Condition Min Typ Max Unit
RMS CONVERSION (f = 1900 MHz) Input RFIN to Output VRMS
Input Impedance +33||−0.1 Ω||pF
Input Return Loss 15 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 2.20 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.12 V
Temperature Sensitivity PIN = −5 dBm
RMS CONVERSION (f = 2350 MHz) Input RFIN to Output VRMS
Input Impedance +32||−0.3 Ω||pF
Input Return Loss 13.6 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 2.00 V
Output Voltage—Low Power In PIN = −21 dBm, 20 mV rms 0.10 V
Temperature Sensitivity PIN = −5 dBm
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.02 V
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.02 V
= 3 V 5 dB
S
= 5 V 7 dB
S
= 3 V 25 dB
S
= 5 V 29 dB
S
= 3 V 28 dB
S
= 5 V 32 dB
S
OUT
25°C ≤ T
−40°C ≤ T
= 3 V 4 dB
S
= 5 V 7 dB
S
= 3 V 25 dB
S
= 5 V 29 dB
S
= 3 V 29 dB
S
= 5 V 32 dB
S
OUT
25°C ≤ T
−40°C ≤ T
2
7 dBm
2
−19 dBm
= (gain × VIN) + intercept 5.5 V/V rms
≤ 85°C
A
≤ +25°C
A
2
8 dBm
2
−18 dBm
= (gain × VIN) + intercept 5.0 V/V rms
≤ 85°C
A
≤ +25°C
A
< +85°C
A
= 5 V 32 dB
S
0.0031 dB/°C
−0.0034 dB/°C
< +85°C
A
= 5 V 8 dB
S
0.0032 dB/°C
−0.0044 dB/°C
Rev. B | Page 5 of 28
Page 6
ADL5501
Parameter Condition Min Typ Max Unit
RMS CONVERSION (f = 2700 MHz) Input RFIN to Output VRMS
Input Impedance +35||−0.5 Ω||pF
Input Return Loss 13 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 1.84 V
Output Voltage—Low Power In PIN = –21 dBm, 20 mV rms 0.09 V
Temperature Sensitivity PIN = –5 dBm
RMS CONVERSION (f = 4000 MHz) Input RFIN to Output VRMS
Input Impedance +41||−0.1 Ω||pF
Input Return Loss 20.8 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 1.53 V
Output Voltage—Low Power In PIN = –21 dBm, 20 mV rms 0.07 V
Temperature Sensitivity PIN = –5 dBm
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.02 V
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.01 V
= 3 V 3 dB
S
= 5 V 7 dB
S
= 3 V 25 dB
S
= 5 V 30 dB
S
= 3 V 28 dB
S
= 5 V 33 dB
S
OUT
25°C ≤ T
−40°C ≤ T
= 3 V 4 dB
S
= 5 V 5 dB
S
= 3 V 28 dB
S
= 5 V 31 dB
S
= 3 V 30 dB
S
= 5 V 33 dB
S
OUT
25°C ≤ T
−40°C ≤ T
2
8 dBm
2
−17 dBm
= (gain × VIN) + intercept 4.6 V/V rms
≤ 85°C
A
≤ +25°C
A
2
10 dBm
2
−18 dBm
= (gain × VIN) + intercept 3.8 V/V rms
≤ 85°C
A
≤ +25°C
A
< +85°C
A
= 5 V 5 dB
S
0.0034 dB/°C
−0.0049 dB/°C
< +85°C
A
= 5 V 5 dB
S
0.0019 dB/°C
−0.0043 dB/°C
Rev. B | Page 6 of 28
Page 7
ADL5501
Parameter Condition Min Typ Max Unit
RMS CONVERSION (f = 5000 MHz) Input RFIN to Output VRMS
Input Impedance +51||−0.2 Ω||pF
Input Return Loss 17 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 1.33 V
Output Voltage—Low Power In PIN = –21 dBm, 20 mV rms 0.08 V
Temperature Sensitivity PIN = –5 dBm
RMS CONVERSION (f = 6000 MHz) Input RFIN to Output VRMS
Input Impedance +86||−0.1 Ω||pF
Input Return Loss 10.1 dB
Dynamic Range
±0.25 dB Error
±0.25 dB Error
V
±1 dB Error
V
±2 dB Error
V
Maximum Input Level ±1 dB error
Minimum Input Level ±1 dB error
Conversion Gain V
Output Intercept
Output Voltage—High Power In PIN = 5 dBm, 400 mV rms 0.97 V
Output Voltage—Low Power In PIN = –21 dBm, 20 mV rms 0.07 V
Temperature Sensitivity PIN = –5 dBm
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.02 V
1
CW input, −40°C < T
4
Delta from 25°C, V
2
V
2
V
2
V
3
0.02 V
= 3 V 5 dB
S
= 5 V 5 dB
S
= 3 V 31 dB
S
= 5 V 35 dB
S
= 3 V 34 dB
S
= 5 V 38 dB
S
OUT
25°C ≤ T
−40°C ≤ T
= 3 V 20 dB
S
= 5 V 20 dB
S
= 3 V 31 dB
S
= 5 V 31 dB
S
= 3 V 35 dB
S
= 5 V 35 dB
S
OUT
25°C ≤ T
−40°C ≤ T
2
15 dBm
2
−20 dBm
= (gain × VIN) + intercept 3.3 V/V rms
≤ 85°C
A
≤ +25°C
A
2
14 dBm
2
−17 dBm
= (gain × VIN) + intercept 2.4 V/V rms
≤ 85°C
A
≤ +25°C
A
< +85°C
A
= 5 V 5 dB
S
0.0001 dB/°C
−0.0031 dB/°C
< +85°C
A
= 5 V 25 dB
S
0.0017 dB/°C
−0.0008 dB/°C
Rev. B | Page 7 of 28
Page 8
ADL5501
Parameter Condition Min Typ Max Unit
OUTPUT OFFSET No signal at RFIN 50 150 mV
ENABLE INTERFACE Pin ENBL
Logic Level to Enable Power, High Condition 2.7 V ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 1.8 V
Input Current when High 2.7 V at ENBL, –40°C ≤ TA ≤ +85°C 0.05 0.1 μA
Logic Level to Disable Power, Low Condition 2.7 V ≤ VS ≤ 5.5 V, −40°C < TA < +85°C –0.5 +0.5 V
Power-Up Response Time5 C
C
C
= C
FLTR
= 1 nF, C
FLTR
= open, C
FLTR
= open, 0 dBm at RFIN 6 μs
OUT
= open, 0 dBm at RFIN 21 μs
OUT
= 100 nF, 0 dBm at RFIN 28 μs
OUT
POWER SUPPLIES
Operating Range −40°C < TA < +85°C 2.7 5.5 V
Quiescent Current No signal at RFIN6 1.1 mA
Total Supply Current When Disabled No signal at RFIN, ENBL input low 0.1 <5 μA
1
The available output swing and, therefore, the dynamic range are altered by the supply voltage; see Figure 8.
2
Error referred to best-fit line at 25°C.
3
Calculated using linear regression.
4
Error referred to delta from 25°C response; see Figure 13, Figure 14, Figure 15, Figure 19, Figure 20, and Figure 21.
5
The response time is measured from 10% to 90% of settling level; see Figure 30.
6
Supply current is input-level dependent; see Figure 6.
V
POS
Rev. B | Page 8 of 28
Page 9
ADL5501
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VS 5.5 V
VRMS 0 V, VS
RFIN 1.25 V rms
Equivalent Power, re: 50 Ω 15 dBm
Internal Power Dissipation 80 mW
θJA (SC-70) 494°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 9 of 28
Page 10
ADL5501
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS
FLTR
RFIN
1
ADL5501
2
TOP VIEW
(Not to Scale)
3
6
5
4
VRMS
ENBL
COMM
06056-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V.
2 FLTR
Square-Domain Filter Pin. Connection for an external capacitor to lower the corner frequency of the squaredomain (or modulation) filter. Capacitor is connected between FLTR and V
and forms a low-pass filter with an
S
8 kΩ on-chip resistor. The on-chip capacitor provides filtering with an approximate 100 kHz corner frequency.
For simple waveforms, no further filtering of the demodulated signal is required.
3 RFIN Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 50 Ω input impedance.
4 COMM Device Ground Pin.
5 ENBL
Enable Pin. Connect pin to V
for normal operation. Connect pin to ground for disable mode for a supply
S
current less than 1 μA.
6 VRMS
Output Pin. Rail-to-rail voltage output with limited 3 mA current drive capability. The output has an internal
100 Ω series resistance. High resistive loads are recommended to preserve output swing.
Rev. B | Page 10 of 28
Page 11
ADL5501
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5.0 V, C
10
= open, C
FLTR
= 100 nF, Colors: black = +25°C, blue = −40°C, red = +85°C, unless otherwise noted.
OUT
3
1
100MHz
OUTPUT (V)
0.1
0.03
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
450MHz
900MHz
1900MHz
2350MHz
2700MHz
4000MHz
5000MHz
6000MHz
06056-004
Figure 4. Output vs. Input Level; Frequencies = 100 MHz, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
6
100MHz
450MHz
5
900MHz
1900MHz
2350MHz
4
2700MHz
4000MHz
5000MHz
3
6000MHz
OUTPUT (V)
2
ERROR (dB)
2
1
0
–1
–2
–3
–25 151050–5–10–15–20
100MHz
450MHz
900MHz
1900MHz
2350MHz
2700MHz
INPUT (dBm)
4000MHz
5000MHz
6000MHz
06056-007
Figure 7. Linearity Error vs. Input Level; Frequencies = 100 MHz, 450 MHz, 90 0 MHz,
1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
10
1
OUTPUT (V)
3.0V
5.5V
5.0V
2.7V
1
0
01.41.21.00.80.60.40.2
INPUT (V rms)
06056-005
Figure 5. Output vs. Input Level (Linear Scale); Frequencies = 100 MHz, 450 MHz,
900 MHz,1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
12
11
10
9
8
7
6
5
4
SUPPLY CURRENT (mA)
3
2
1
0
000.80.70.60.50.40.30.20.1
3.0V
INPUT (V rms)
5.0V
.9
06056-006
Figure 6. Supply Current vs. Input Level; Supplies = 3.0 V and 5.0 V;
Temperatures = −40°C, +25°C, and +85°C
0.1
0.03
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 8. Output vs. Input Level;
Supply = 2.7 V, 3.0 V, 5.0 V, and 5.5 V; Frequency = 900 MHz
30
25
20
15
RETURN LOSS ( dB)
10
5
06421
FREQUENCY (GHz)
Figure 9. Return Loss vs. Frequency
06056-008
53
06056-009
Rev. B | Page 11 of 28
Page 12
ADL5501
3
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-010
Figure 10. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 900 MHz; Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 13. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 900 MHz, Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
06056-013
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-011
Figure 11. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 1900 MHz; Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-012
Figure 12. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 2350 MHz; Supply = 5.0 V
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 14. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 1900 MHz, Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 15. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 2350 MHz, Supply = 5.0 V
06056-014
06056-015
Rev. B | Page 12 of 28
Page 13
ADL5501
3
3
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-016
Figure 16. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 2700 MHz; Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 19. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 2700 MHz, Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
06056-019
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-018
Figure 17. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 4000 MHz; Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-018
Figure 18. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 6000 MHz; Supply = 5.0 V
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 20. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 4000 MHz, Supply = 5.0 V
3
2
1
0
ERROR (d B)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 21. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 6000 MHz, Supply = 5.0 V
06056-021
06056-021
Rev. B | Page 13 of 28
Page 14
ADL5501
5
1
VOUT (V)
CW
0.1
0.03
–25 –20 –15 –10 –5 0 5 10
INPUT (dBm)
QPSK
8PSK
16QAM
64QAM
06056-022
Figure 22. Output vs. Input Level with Different Waveforms, 10 MHz Signal BW
for All Modulated Signals, Supply = 5.0 V, Frequency = 1900 MHz
10 MHz Signal BW for All Modulated Signals, Supply = 5.0 V, Frequency = 1900 MHz
3
CW
QPSK, 4.8 dB CF
2
8PSK, 4.8dB CF
16QAM, 6.3dB CF
64QAM, 7.4dB CF
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
INPUT (dBm)
Figure 25. Error from CW Linear Reference vs. Input with Different Waveforms,
06056-025
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
RFIN (dBm)
CW
BPSK, 11dB CF
QPSK, 11dB CF
16QAM, 12dB CF
64QAM, 11dB CF
Figure 23. Error from CW Linear Reference vs. Input Level for Various
802.16 OFDM Waveforms at 2.35 GHz, 10 MHz Signal BW, and
256 Subcarriers for All Modulated Signals, S upply = 5.0 V
3
CW
12.2kbps, DPCCH (–5.46dB, 15kSPS) +
DPDCH (0dB, 60kSPS) , 3.4dB CF
2
64kbps, DPCCH (–9.54dB, 15kSPS) +
DPDCH (0dB, 240kSPS), 3.4dB CF
144kbps, DPCCH (–11.48dB, 15kSPS) +
DPDCH (0dB, 480kSPS), 3.3dB CF
384kbps, DPCCH (–11.48dB, 15kSPS) +
1
DPDCH (0dB, 960kSPS), 3.3dB CF
768kbps, DPCCH (–11.48dB, 15kSPS) +
DPDCH1 + 2 (0dB, 960kSPS), 5.8dB CF
0
ERROR (dB)
–1
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
06056-023
RFIN (dBm)
CW
BPSK, 11dB CF
QPSK, 11dB CF
16QAM, 12dB CF
64QAM, 11dB CF
06056-026
Figure 26. Error from CW Linear Reference vs. Input Level for Various
802.16 OFDM Waveforms at 3.5 GHz, 10 MHz Signal BW, and
256 Subcarriers for All Modulated Signals, Supply = 5.0 V
3
CW
PICH, 4. 7dB CF
PICH + FCH (9. 6kbps), 4.8dB CF
2
PICH + FCH (9.6kbps) + DCCH, 6. 3dB CF
PICH + FCH (9. 6kbps) + SCH (153.6kbps), 6.7dB CF
PICH + FCH (9.6kbps) + DCCH +
1
SCH (153.6kbp s), 7.6dB CF
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
RFIN (dBm)
Figure 24. Error from CW Linear Reference vs. Input with Various
WCDMA Up Link Waveforms at 1900 MHz, C
= Open, C
FLTR
OUT
06056-024
= 100 nF
Rev. B | Page 14 of 28
–2
–3
–25 –20 –15 –10 –5 0 5 10
RFIN (dBm)
Figure 27. Error from CW Linear Reference vs. Input with Various
CDMA2000 Reverse Link Waveforms at 900 MHz, C
= 1 nF, C
FLTR
= 100 nF
OUT
06056-027
Page 15
ADL5501
3
CW
TEST MO DEL 1 w/ 16 DPCH, 1 CARRIER
TEST MO DEL 1 w/ 32 DPCH, 1 CARRIER
2
TEST MO DEL 1 w/ 64 DPCH, 1 CARRIER
TEST MO DEL 1 w/ 64 DPCH, 2 CARRIERS
TEST MO DEL 1 w/ 64 DPCH, 3 CARRIERS
1
TEST MO DEL 1 w/ 64 DPCH, 4 CARRIERS
3
CW
SR1, PILOT CHANNEL, 1 CARRIER
SR1, 9 CHANNEL, 1 CARRI ER
2
SR1, 9 CHANNEL, 3 CARRI ERS
SR1, 9 CHANNEL, 4 CARRI ERS
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
RFIN (dBm)
06056-028
Figure 28. Error from CW Linear Reference vs. Input with Various
WCDMA Down Link Waveforms at 2140 MHz, C
C1
FLTR
C2
0.1µF
ADL5501
1 6
VPOS
2 5
FLTR
3 4
RFIN
VRMS
ENBL
COMM
100pF
POWER
SUPPLY
C
RF PULSE
GENERATOR
= 1 nF, C
FLTR
OSCILLOSCOPE
C
OUT
OUT
FET PROBE
R
OUT
= 100 nF
06056-029
Figure 29. Hardware Configuration for Output Response to RF Input Pulse
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10
INPUT (dBm)
06056-031
Figure 31. Error from CW Linear Reference vs. Input with Various
CDMA2000 Fwd Link Waveforms at 2140 MHz, C
400mV rms RF INPUT
250mV rms
VRMS (500mV/DIV)
160mV rms
70mV rms
40µs/DIV
= 1 nF, C
FLTR
OUT
PULSED
RFIN
= 100 nF
06056-032
Figure 32. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, C
= 1 nF, C
FLTR
= Open, R
OUT
= Open
OUT
PULSED
RFIN
400mV rms RF INPUT
250mV rms
VRMS (500mV/DIV)
160mV rms
70mV rms
10µs/DIV
06056-030
Figure 30. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, C
= Open, C
FLTR
= Open, R
OUT
OUT
= Open
Rev. B | Page 15 of 28
PULSED RFIN
400mV rms RF INPUT
VRMS (500mV/DI V)
250mV rms
160mV rms
70mV rms
100µs/DIV
06056-033
Figure 33. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, C
= Open, C
FLTR
= 0.1 μF, R
OUT
OUT
= 1 kΩ
Page 16
ADL5501
OSCILLOSCOPE
100pF
POWER
SUPPLY
C
RF SIGNAL
GENERATOR
C1
FLTR
C2
0.1µF
1 6
VPOS
2 5
FLTR
3 4
RFIN
PULSE
GENERATOR
ADL5501
VRMS
ENBL
COMM
50Ω
AD811
732Ω
C
OUT
FET PROBE
Figure 34. Hardware Configuration for Output Response to
Enable Gating Measurements
ENBL
R
OUT
VRMS (500mV/DI V)
06056-034
Figure 37. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, C
ENBL
400mV rms RF INPUT
250mV rms
160mV rms
70mV rms
40µs/DIV
= 1 nF, C
FLTR
ENBL
= Open, R
OUT
= Open
OUT
06056-037
400mV rms RF INPUT
250mV rms
VRMS (500mV/DIV)
160mV rms
70mV rms
10µs/DIV
Figure 35. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, C
8
7
6
5
4
3
2
CONVERSION GAIN (V/V rms)
1
0
0 2000 4000 6000
FREQUENCY (MHz )
= Open, C
FLTR
= Open, R
OUT
= Open
OUT
Figure 36. Conversion Gain vs. Frequency, Supply 5 V
400mV rms RF INPUT
VRMS (500mV/DIV)
06056-035
250mV rms
160mV rms
70mV rms
100µs/DIV
06056-038
Figure 38. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, C
100
90
80
70
60
50
40
INTERCEPT (mV)
30
20
10
0
0 2000 4000 6000
06056-036
FREQUENCY (MHz )
= Open, C
FLTR
= 0.1 μF, R
OUT
OUT
= 1 kΩ
06056-039
Figure 39. Intercept vs. Frequency, Supply = 5 V
Rev. B | Page 16 of 28
Page 17
ADL5501
CIRCUIT DESCRIPTION
The ADL5501 is an rms-responding (mean power) detector that
provides an approach to the exact measurement of RF power that
is independent of waveform. It achieves this function by using
a proprietary technique in which the outputs of two identical
squaring cells are balanced by the action of a high gain error
amplifier.
The signal to be measured is applied to the input of the first
squaring cell through the input matching network. The input
is matched to offer a broadband 50 Ω input impedance from
50 MHz to 6 GHz. The input matching network has a high-pass
corner frequency of approximately 70 MHz.
The ADL5501 responds to the voltage, V
this voltage to generate a current proportional to V
, at its input by squaring
IN
2
. This current
IN
is applied to an internal load resistor in parallel with a capacitor,
followed by a low-pass filter, which extracts the mean of V
2
.
IN
Although essentially voltage responding, the associated input
impedance calibrates this port in terms of equivalent power.
Therefore, 1 mW corresponds to a voltage input of 224 mV rms
referenced to 50 Ω. Because both the squaring cell input impedance
and the input matching network are frequency dependent, the
conversion gain is a function of signal frequency.
The voltage across the low-pass filter, whose frequency can
be arbitrarily low, is applied to one input of an error-sensing
amplifier. A second identical voltage-squaring cell is used to
close a negative feedback loop around this error amplifier. This
second cell is driven by a fraction of the quasi-dc output voltage
of the ADL5501. When the voltage at the input of the second
squaring cell is equal to the rms value of V
, the loop is in a stable
IN
state, and the output then represents the rms value of the input.
By completing the feedback path through a second squaring
cell, identical to the one receiving the signal to be measured,
several benefits arise. First, scaling effects in these cells cancel;
therefore, the overall calibration can be accurate, even though
the open-loop response of the squaring cells taken separately
need not be. Note that in implementing rms-dc conversion, no
reference voltage enters into the closed-loop scaling. Second,
the tracking in the responses of the dual cells remains very close
over temperature, leading to excellent stability of calibration.
The squaring cells have very wide bandwidth with an intrinsic
response from dc to microwave. However, the dynamic range of
such a system is small, due in part to the much larger dynamic
range at the output of the squaring cells. There are practical
limitations to the accuracy of sensing very small error signals at
the bottom end of the dynamic range, arising from small random
offsets that limit the attainable accuracy at small inputs.
On the other hand, the squaring cells in the ADL5501 have a
Class AB aspect; the peak input is not limited by its quiescent
bias condition but is determined mainly by the eventual loss of
square-law conformance. Consequently, the top end of their
response range occurs at a large input level (approximately
700 mV rms), while preserving a reasonably accurate square-law
response. The maximum usable range is, in practice, limited by
the output swing. The rail-to-rail output stage can swing from a
few millivolts above ground to within 100 mV below the supply.
An example of the output induced limit, given a conversion gain
of 6.3 V/V rms at 900 MHz and assuming a maximum output of
2.9 V with a 3 V supply, has a maximum input of 2.9 V rms/6.3 or
460 mV rms.
FILTERING
An important aspect of rms-dc conversion is the need for
averaging (the function is root-mean-square). The on-chip
averaging in the square domain has a corner frequency of
approximately 100 kHz and is sufficient for common modulation signals, such as CDMA-, CDMA2000-, WCDMA-, and
QPSK-/QAM-based OFDM (for example, WLAN and WiMAX).
For more complex RF waveforms (with modulation components
extending down into the kilohertz region), more filtering is
necessary to supplement the on-chip, low-pass filter. For this
reason, the FLTR pin is provided; a capacitor attached between
this pin and VPOS can extend the averaging time to very low
frequencies.
Adequate filtering ensures the accuracy of the rms measurement;
however, some ripple or ac residual can still be present on the
dc output. To reduce this ripple, an external shunt capacitor can
be used at the output to form a low-pass filter with the on-chip,
100 Ω resistance (see the Selecting the Square-Domain Filter
and Output Low-Pass Filter section).
Rev. B | Page 17 of 28
Page 18
ADL5501
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 40 shows the basic connections for the ADL5501. The
device is powered by a single supply of between 2.7 V and 5.5 V,
with a quiescent current of 1.1 mA. The VPOS pin is decoupled
using 100 pF and 0.1 μF capacitors.
The ADL5501 RF input does not require external termination
components because it is internally matched for an overall
broadband input impedance of 50 Ω.
+VS 2.7V TO 5.5V
100pF 0.1µF
C
FLTR
RFIN
Figure 40. Basic Connections for the ADL5501
ADL5501
1 6
VPOS
VRMS
2 5
FLTR
3 4
RFIN
ENBL
COMM
VRMS
C
OUT
06056-040
OUTPUT SWING
At 900 MHz, the output voltage is nominally 6.3 times the input
rms voltage (a conversion gain of 6.3 V/V rms). The output voltage
swings from near ground to 4.9 V on a 5.0 V supply.
Figure 41 shows the output swing of the ADL5501 to a CW input
for various supply voltages. It is clear from Figure 41 that
operating the device at lower supply voltages reduces the
dynamic range as the output headroom decreases.
10
1
OUTPUT (V)
0.1
3.0V
5.5V
5.0V
2.7V
LINEARITY
Because the ADL5501 is a linear-responding device, plots of
output voltage vs. input voltage result in a straight line. It is more
useful to plot the error on a logarithmic scale, as shown in
Figure 42. The deviation of the plot for the ideal straight-line
characteristic is caused by output clipping at the high end and
by signal offsets at the low end. However, it should be noted that
offsets at the low end can be either positive or negative; therefore,
this plot could also trend upwards at the low end. Figure 10
through Figure 12 and Figure 16 through Figure 18 show error
distributions for a large population of devices at specific
frequencies.
3
100MHz
450MHz
900MHz
ERROR (dB)
2
1
0
–1
–2
–3
–25 151050–5–10–15–20
Figure 42. Representative Unit, Error in dB vs. Input Level, V
It is also apparent in Figure 42 that the error plot tends to shift
to the right with increasing frequency. The squaring cell has an
input impedance that decreases with frequency. The matching
network compensates for the change and maintains the input
impedance at a nominal 50 Ω. The result is a decrease in the
actual voltage across the squaring cell as the frequency increases,
reducing the conversion gain. Similarly, conversion gain is less
at frequencies near 100 MHz because of the small on-chip
coupling capacitor.
1900MHz
2350MHz
2700MHz
INPUT (dBm)
4000MHz
5000MHz
6000MHz
= 5.0 V
S
06056-107
0.03
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-041
Figure 41. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V, and 5.5 V
Rev. B | Page 18 of 28
Page 19
ADL5501
INPUT COUPLING USING A SERIES RESISTOR
Figure 43 shows a technique for coupling the input signal into
the ADL5501 that can be applicable where the input signal is
much larger than the input range of the ADL5501. A series
resistor combines with the input impedance of the ADL5501
to attenuate the input signal. Because this series resistor forms
a divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the impedance of the transmission line, the VSWR
of the system is relatively unaffected.
R
RFIN
Figure 43. Attenuating the Input Signal
The resistive tap or series resistance, R
= RIN (1 − 10
R
SERIES
SERIES
ATTN/20
)/(10
RFIN
ADL5501
, can expressed as
SERIES
ATTN/20
) (1)
06056-043
where:
R
is the input impedance of RFIN.
IN
AT TN is the desired attenuation factor in dB.
For example, if a power amplifier with a maximum output power
of +28 dBm is matched to the ADL5501 input at +5 dBm, then
a −23 dB attenuation factor is required. At 900 MHz, the input
resistance, R
R
, is 55 Ω.
IN
= (55 Ω) (1 − 10
SERIES
−23/20
)/(10
−23/20
) = 722 Ω
Thus, for an attenuation of −23 dB, a series resistance of
approximately 722 Ω is needed.
MULTIPLE RF INPUTS
Figure 44 shows a technique for combining multiple RF input
signals to the ADL5501. Some applications can share a single
detector for multiple bands. Three 16.5 Ω resistors in a T-network
combine the three 50 Ω terminations (including the ADL5501).
The broadband resistive combiner ensures that each port of the
T-network sees a 50 Ω termination. Because there are only 6 dB
of isolation from one port of the combiner to the other ports,
only one band should be active at a time.
BAND 1
DIRECTIONAL
COUPLER
DIRECTIONAL
COUPLER
Figure 44. Combining Multiple RF Input Signals
BAND 2
50Ω
50Ω
16.5Ω
16.5Ω
16.5Ω
RFIN
ADL5501
06056-044
SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER
The internal filter capacitor of the ADL5501 provides averaging
in the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA or
CDMA2000, can produce ac-residual levels on the ADL5501
dc output. To reduce the effects of these low frequency components
in the waveforms, some additional filtering is required.
The square-domain filter capacitance of the ADL5501 can be
augmented by connecting a capacitor between Pin 2 (FLTR) and
Pin 1 (VPOS). In addition, the output of the ADL5501 can be
filtered directly by placing a capacitor between VRMS (Pin 6)
and ground. The combination of the on-chip, 100 Ω output
series resistance and the external shunt capacitor forms a lowpass filter to reduce the residual ac.
Tabl e 4 shows the effects of several capacitor values for various
communications standards with high peak-to-average ratios
along with the residual ripple at the output, in peak-to-peak and
rms volts. Note that large load capacitances increase the turn-on
and pulse response times (see Figure 30, Figure 32, Figure 33,
Figure 35, Figure 37, and Figure 38). For more information on
the effects of the filter capacitances on the response, see the
Power Consumption, Enable, and Power-On/Power-Off
Response Time section.
Rev. B | Page 19 of 28
Page 20
ADL5501
Table 4. Waveform and Output Filter Effects on Residual AC
Output Residual AC
Waveform C
, C
V dc mV p-p mV rms
FILT
OUT
64QAM 1 nF, 0.5 83 11
(7.4 dB CF) open 1.0 175 21
2.0 394 47
Open, 0.5 49 5.5
0.1 μF 1.0 98 11
2.0 212 23
1 nF, 0.5 45 5.5
0.1 μF 1.0 93 11
2.0 200 24
W-CDMA RL 1 nF, 0.5 6.4 0.8
(3.4 dB CF) open 1.0 19 2.6
2.0 52 6.6
Open, 0.5 4.5 0.6
0.1 μF 1.0 16 2.2
2.0 36 4.9
1 nF, 0.5 3.1 0.5
0.1 μF 1.0 9.6 1.4
2.0 27 3.9
CDMA2000 DL 1 nF, 0.5 67 8.6
(6.7 dB CF) open 1.0 148 19
2.0 339 43
Open, 0.5 28 3.9
0.1 μF 1.0 56 7.9
2.0 119 17
1 nF, 0.5 26 3.7
0.1 μF 1.0 52 7.7
2.0 116 17
W-CDMA UL 1 nF, 0.5 204 32
TM1-64, 1 CR open 1.0 396 64
2.0 840 140
Open, 0.5 60 11
0.1 μF 1.0 112 21
2.0 227 42
1 nF, 0.5 56 11
0.1 μF 1.0 114 21
2.0 243 45
POWER CONSUMPTION, ENABLE, AND POWERON/POWER-OFF RESPONSE TIME
The quiescent current consumption of the ADL5501 varies with
the size of the input signal from approximately 1.1 mA for no
signal up to 6.2 mA at an input level of 0.7 V rms (10 dBm,
re: 50 Ω). If the input is driven beyond this point, the supply
current increases sharply (as shown in Figure 6). There is little
variation in quiescent current with power supply voltage.
The ADL5501 can be disabled either by pulling ENBL (Pin 5) to
COMM (Pin 4) or by removing the supply power to the device.
Disabling the device via the ENBL function reduces the leakage
current to less than 1 μA.
If the input of the ADL5501 is driven while the device is disabled
(ENBL = COMM), the leakage current of less than 1 μA increases
as a function of input level. When the device is disabled, the
output impedance increases to approximately 33.5 kΩ.
The turn-on time and pulse response is strongly influenced by
the size of the square-domain filter and output shunt capacitor.
Figure 45 shows a plot of the output response to an RF pulse on
the RFIN pin, with a 0.1 μF output filter capacitor and no
square-domain filter capacitor. The falling edge is particularly
dependent on the output shunt capacitance, as shown in Figure 45.
PULSED RFIN
400mV rms RF INPUT
250mV rms
160mV rms
VRMS (500mV/DIV)
70mV rms
2ms/DIV
Figure 45. Output Response to Various RF Input Pulse Levels,
Supply = 3 V, Frequency = 900 MHz,
Square-Domain Filter Open, Output Filter = 0.1 μF
06056-045
To improve the falling edge of the enable and pulse responses,
a resistor can be placed in parallel with the output shunt capacitor.
The added resistance helps to discharge the output filter capacitor.
Although this method reduces the power-off time, the added
load resistor also attenuates the output (see the Output Drive
Capability and Buffering section).
PULSED RFIN
400mV rms RF INPUT
250mV rms
160mV rms
VRMS (500mV/DIV)
Figure 46. Output Response to Various RF Input Pulse Levels,
Square-Domain Filter Open, Output Filter = 0.1 μF with Parallel 1 kΩ
70mV rms
2ms/DIV
Supply = 3 V, Frequency = 900 MHz,
06056-046
The square-domain filter improves the rms accuracy for high
crest factors (see the Selecting the Square-Domain Filter and
Output Low-Pass Filter section), but it can hinder the response
time. For optimum response time and low ac residual, both the
square-domain filter and the output filter should be used.
Rev. B | Page 20 of 28
Page 21
ADL5501
The square-domain filter at FLTR can be reduced to improve
response time, and the remaining ac residual can be decreased
by using the output filter, which has a smaller time constant.
OUTPUT DRIVE CAPABILITY AND BUFFERING
The ADL5501 is capable of sourcing an output current of approximately 3 mA. The output current is sourced through the on-chip,
100 Ω series resistor; therefore, any load resistor forms a voltage
divider with this on-chip resistance.
It is recommended that the ADL5501 drive high resistive loads
to preserve output swing. If an application requires driving a low
resistance load, a simple buffering circuit can be used, as shown
in Figure 49. Similar circuits can be used to increase or decrease
the nominal conversion gain (see Figure 47 and Figure 48). In
Figure 48, the AD8031 buffers a resistive divider to give half of
the slope. In Figure 47, the op amp gain of two doubles the slope.
Using other resistor values, the slope can be changed to an arbitrary
value. The AD8031 rail-to-rail op amp, used in these examples,
can swing from 50 mV to 4.95 V on a single 5 V supply and
operates at supply voltages down to 2.7 V. If high output current
is required (>10 mA), the AD8051, which also has rail-to-rail
capability, can be used down to a supply voltage of 3 V. It can
deliver up to 45 mA of output current.
5V
100pF0.1µF
VRMS OUTPUT OFFSET
The ADL5501 has a ±1 dB error detection range of about 30 dB,
as shown in Figure 10 to Figure 12 and Figure 16 to Figure 18.
The error is referred to the best-fit line defined in the linear region
of the output response. Below an input power of −20 dBm, the
response is no longer linear and begins to lose accuracy. In addition, depending on the supply voltage, saturation of the output
limits the detection accuracy above 10 dBm. Calibration points
should be chosen in the linear region, avoiding the nonlinear
ranges at the high and low extremes.
Figure 50 shows the distribution of the output response vs. the
input power for multiple devices. The ADL5501 loses accuracy at
low input powers as the output response begins to fan out. As the
input power is reduced, the spread of the output response increases
along with the error. Although some devices follow the ideal linear
response at very low input powers, not all devices continue the
ideal linear regression to a near 0 V y-intercept. Some devices
exhibit output responses that rapidly decrease, and some flatten
out. With no RF signal applied, the ADL5501 has a typical output
offset of 50 mV (with a maximum of 150 mV).
10
1
AD8031
5kΩ
5kΩ
0.01µF
12.6V/V rms
06056-047
VPOS
VRMS
ADL5501
COMM
Figure 47. Output Buffering Options, Slope of 12.6 V/V rms at 900 MHz
5V
VPOS
100pF0.1µF
VRMS
4kΩ
0.01µF
ADL5501
COMM
5kΩ
AD8031
3.2V/V rms
Figure 48. Output Buffering Options, Slope of 3.2 V/V rms at 900 MHz
100pF0.1µF
VPOS
VRMS
ADL5501
COMM
0.01µF
AD8031
5V
6.3V/V rms
OUTPUT (V)
0.1
0.01
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-050
Figure 50. Output vs. Input Level Distribution of 50 Devices,
Frequency = 900 MHz, Supply = 5.0 V
06056-048
Figure 49. Output Buffering Options, Slope of 6.3 V/V rms at 900 MHz
06056-049
Rev. B | Page 21 of 28
Page 22
ADL5501
DEVICE CALIBRATION AND ERROR CALCULATION
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy.
In general, calibration is performed by applying two input power
levels to the ADL5501 and measuring the corresponding output
voltages. The calibration points are generally chosen to be within
the linear operating range of the device. The best-fit line is characterized by calculating the conversion gain (or slope) and intercept
using the following equations:
Gain = (V
Intercept = V
where:
V
is the rms input voltage to RFIN.
IN
is the voltage output at VRMS.
V
RMS
After gain and intercept are calculated, an equation can be
written that allows calculation of an (unknown) input power
based on the measured output voltage.
V
= (V
IN
For an ideal (known) input power, the law conformance error of
the measured data can be calculated as
ERROR (dB) =
20 × log [(V
Figure 51 includes a plot of the error at 25°C, the temperature
at which the ADL5501 is calibrated. Note that the error is not
zero; this is because the ADL5501 does not perfectly follow the
ideal linear equation, even within its operating region. The
error at the calibration points is, however, equal to zero by
definition.
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5
Figu re 51. Error from Linear Reference vs. Input at −4 0°C, +2 5°C, a nd
+85°C vs. +25°C Linear Reference, Frequency = 1900 MHz, Supply = 5.0 V
Figure 51 also includes error plots for the output voltage at
−40°C and +85°C. These error plots are calculated using the
gain and intercept at +25°C. This is consistent with calibration in a mass-production environment where calibration at
temperature is not practical.
− V
)/(V
− V
RMS2
RMS
RMS1
IN2
− (Gain × V
RMS1
− Intercept)/Gain (4)
RMS, MEASURED
− Intercept)/(Gain × V
–40°C
INPUT (dBm)
) (2)
IN1
) (3)
IN1
)] (5)
IN, IDEAL
+85°C
+25°C
10 15
06056-051
CALIBRATION FOR IMPROVED ACCURACY
Another way of presenting the error function of the ADL5501
is shown in Figure 52. In this case, the dB error at hot and cold
temperatures is calculated with respect to the transfer function
at ambient. This is a key difference in comparison to the previous
plots. Up until now, the errors were calculated with respect to
the ideal linear transfer function at ambient. When this alternative technique is used, the error at ambient becomes equal to
zero by definition (see Figure 52).
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5
Figure 52. Error from +25°C Output Voltage at −40°C, +25°C, and +85°C
After Ambient Normalization, Frequency = 1900 MHz, Supply = 5.0 V
This plot is a useful tool for estimating temperature drift at a
particular power level with respect to the (nonideal) response at
ambient. The linearity and dynamic range tend to be improved
artificially with this type of plot because the ADL5501 does not
perfectly follow the ideal linear equation (especially outside of
its linear operating range). Achieving this level of accuracy in
an end application requires calibration at multiple points in the
operating range of the device.
In some applications, very high accuracy is required at just one
power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA)
is most critical at or close to full power. The ADL5501 offers a
tight error distribution in the high input power range, as shown
in Figure 52. The high accuracy range, centered around 9 dBm at
1900 MHz, offers 7 dB of ±0.1 dB detection error over temperature.
Multiple point calibration at ambient temperature in the reduced
range offers precise power measurement with near 0 dB error
from −40°C to +85°C.
The high accuracy range center varies over frequency. At
1900 MHz, the region is centered at approximately 9 dBm.
At higher frequencies, the high accuracy range is centered
at higher input powers (see Figure 13 through Figure 15 and
Figure 19 through Figure 21).
+85°C
–40°C
INPUT (dBm)
+25°C
10 15
06056-052
Rev. B | Page 22 of 28
Page 23
ADL5501
DRIFT OVER A REDUCED TEMPERATURE RANGE
Figure 53 shows the error over temperature for a 1.9 GHz input
signal. Error due to drift over temperature consistently remains
within ±0.25 dB and begins to exceed this limit only when the
ambient temperature goes above +25°C and below −10°C. For
all frequencies using a reduced temperature range, higher
measurement accuracy is achievable.
ERROR (dB)
1.00
0.75
0.50
0.25
–0.25
–0.50
+85°C
+70°C
+50°C
+35°C
+25°C
0
+15°C
0°C
–10°C
–25°C
–40°C
Due to the repeatability of the performance from part to part,
compensation can be applied to reduce the effects of temperature
drift and linearity error. To detect larger dynamic ranges at
lower frequencies, the transfer function at ambient can be
calibrated, thus eliminating the linearity error. This technique
is discussed in detail in the Calibration for Improved Accuracy
section. Figure 55 shows that the dynamic range within ±0.5 dB
error improves to 30 dB by using this method.
3
2
1
0
ERROR (dB)
–1
–0.75
–1.00
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm rms)
06056-100
Figure 53. Typical Drift at 1.9 GHz for Various Temperatures
OPERATION BELOW 100 MHz
The ADL5501 works at frequencies below 100 MHz but exhibits a
slightly higher linearity error. Figure 54 shows the error distribution
of 12 devices at 50 MHz over temperature. When compared to
an ideal linear transfer function at ambient, the error of the
ADL5501 over temperature remains within ±0.5 dB for the
central 20 dB of the dynamic range. At the higher input power
levels, the error grows as the response becomes nonlinear. The
typical slope and intercept at 50 MHz are 4.5 V/V rms and
0.04 V, respectively.
3
2
1
0
ERROR (dB)
–1
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
Figure 54. Temperature Drift Distributions for 12 Devices at −40°C, +25°C,
and +85°C vs. +25°C Linear Reference, Frequency = 50 MHz, Supply = 5.0 V
INPUT (dBm)
06056-053
–2
–3
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
06056-054
Figure 55. Output Delta from +25°C Output Voltage for
12 Devices at −40°C and +85°C, Frequency = 50 MHz, Supply = 5.0 V
EVALUATION BOARD
Figure 56 shows the schematic of the ADL5501 evaluation
board. The layout and silkscreen of the evaluation board layers
are shown in Figure 57 and Figure 58. The board is powered by
a single supply in the 2.7 V to 5.5 V range. The power supply is
decoupled by 100 pF and 0.1 μF capacitors. Table 5 details the
various configuration options of the evaluation board.
Problems caused by impedance mismatch can arise when the
evaluation board is used to examine ADL5501 performance.
One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source,
cable, and cable interconnection, as well as those occurring on
the evaluation board, can cause these problems.
A simple (and common) example of such a problem is triple
travel due to mismatch at both the source and the evaluation
board. Here the signal from the source reaches the evaluation
board, and mismatch causes a reflection. When that reflection
reaches the source mismatch, it causes a new reflection, which
travels back to the evaluation board, adding to the original signal
incident at the board. The resulting voltage varies with both
cable length and frequency dependence on the relative phase of
the initial and reflected signals. Placing the 3 dB pad at the input of
the board improves the match at the board and, thus, reduces
the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable length and
other fixture issues. In an actual application when the distance
between the ADL5501 and the source is short and well defined,
this 3 dB attenuator is not needed.
Rev. B | Page 23 of 28
Page 24
ADL5501
C1
100pFC20.1µF
VPOS
(OPEN)
RFIN
C3
ADL5501
1 6
2 5
3 4
VPOS
FLTR
RFIN
VRMS
ENBL
COMM
TO EDGE
CONNECTOR
R3
0Ω
100nF
VPOS
R1
(OPEN)
TO EDGE
CONNECT OR
R5
(OPEN)
C4
SW1
R2
(OPEN)
R4
49.9Ω
VRMS
ENBL
06056-056
Figure 56. Evaluation Board Schematic
Table 5. Evaluation Board Configuration Options
Component Description Default Condition
GND, VPOS Ground and supply vector pins. Not applicable
C1, C2 Power supply decoupling. The nominal supply decoupling of 100 pF and 0.1 μF.
C1 = 100 pF (Size 0402)
C2 = 0.1 μF (Size 0402)
C3
Filter capacitor. The internal averaging capacitor can be augmented by placing additional
C3 = open (Size 0402)
capacitance in C3.
R2, R3, C4
R4, SW1
Output filtering. The combination of the internal 100 Ω output resistance and C4 produces a low-
pass filter to reduce output ripple. The output can also be scaled down using the resistor divider
pads, R3 and R2. In addition, resistors and capacitors can be placed in C4 and R2 to load test VRMS.
Device enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS,
and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded
R2 = open (Size 0402)
R3 = 0 Ω (Size 0402)
C4 = 100 nF (Size 0402)
R4 = 49.9 Ω (Size 0402)
SW1 = toward SW1 label
(through the 49.9 Ω resistor), putting the device in power-down mode. While in this switch position,
the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R4 serves as
a termination resistor for generators requiring a 50 Ω match.
R1, R5
Alternate interface. R1and R5 allow for VRMS and ENBL to be accessible from the edge
connector, which is used only for characterization.
R1 = open (Size 0402)
R5 = open (Size 0402)
06056-057
Figure 57. Layout of Evaluation Board, Component Side
Figure 58. Layout of Evaluation Board, Circuit Side
06056-058
Rev. B | Page 24 of 28
Page 25
ADL5501
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
0.30
0.15
4 5 6
3 2 1
0.65 BSC
2.10
1.80
1.10
0.80
SEATING
PLANE
0.40
0.10
0.22
0.08
0.46
0.36
0.26
1.35
1.25
1.15
PIN 1
1.30 BSC
1.00
0.90
0.70
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 59. 6-Lead Thin Shrink Small Outline Transistor Package [SC-70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADL5501AKSZ-R7
ADL5501AKSZ-R2
ADL5501-EVALZ
1
Z =RoHS Compliant Part.
1
–40°C to +85°C 6-Lead SC-70, 7” Tape and Reel KS-6 Q0Z 3,000
1
–40°C to +85°C 6-Lead SC-70, 7” Tape and Reel KS-6 Q0Z 250
1
Evaluation Board
Ordering
Quantity
Rev. B | Page 25 of 28
Page 26
ADL5501
NOTES
Rev. B | Page 26 of 28
Page 27
ADL5501
NOTES
Rev. B | Page 27 of 28
Page 28
ADL5501
NOTES
©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06056-0-3/09(B)
Rev. B | Page 28 of 28
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