Datasheet ADL5382 Datasheet (ANALOG DEVICES)

Quadrature Demodulator

ADL5382

Rev. A

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BIAS

GEN

ADL5382

0°

90°

1

24

CMRF CMRF

RFIP RFIN CMRF VPX

CML

VPA

COM

BIAS

VPL

VPL

VPL

VPB

VPB

QHI

QLO

IHI

ILO

LOIP LOIN CML CML COM

23 22 21 20 19

7 8 9 10 11 12

2

3

4

5

6

18

17

16

15

14

13

07208-001

Data Sheet

FEATURES

Operating RF and LO frequency: 700 MHz to 2.7 GHz
Input IP3

33.5 dBm @ 900 MHz

30.5 dBm @1900 MHz
Input IP2: >70 dBm @ 900 MHz
Input P1dB: 14.7 dBm @ 900 MHz
Noise figure (NF)

14.0 dB @ 900 MHz

15.6 dB @ 1900 MHz
Voltage conversion gain: ~4 dB
Quadrature demodulation accuracy

Phase accuracy: ~0.2°

Amplitude balance: ~0.05 dB
Demodulation bandwidth: ~370 MHz
Baseband I/Q drive: 2 V p-p into 200 Ω
Single 5 V supply

700 MHz to 2.7 GHz

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

Cellular W-CDMA/CDMA/CDMA2000/GSM
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX

GENERAL DESCRIPTION

The ADL5382 is a broadband quadrature I-Q demodulator that
covers an RF input frequency range from 700 MHz to 2.7 GHz.
With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at
900 MHz, the ADL5382 demodulator offers outstanding dynamic
range suitable for the demanding infrastructure direct-conversion
requirements. The differential RF inputs provide a well-behaved
broadband input impedance of 50 Ω and are best driven from a
1:1 balun for optimum performance.

Excellent demodulation accuracy is achieved with amplitude and
phase balances ~0.05 dB and ~0.2°, respectively. The demodulated
in-phase (I) and quadrature (Q) differential outputs are fully
buffered and provide a voltage conversion gain of ~4 dB. The
buffered baseband outputs are capable of driving a 2 V p-p
differential signal into 200 Ω.

The fully balanced design minimizes effects from second-order
distortion. The leakage from the LO port to the RF port is
<−65 dBc. Differential dc offsets at the I and Q outputs are typically
<10 mV. Both of these factors contribute to the excellent IIP2
specifications which is >60 dBm.

The ADL5382 operates off a single 4.75 V to 5.25 V supply. The
supply current is adjustable with an external resistor from the
BIAS pin to ground.

The ADL5382 is fabricated using the Analog Devices, Inc.,
advanced Silicon-Germanium bipolar process and is available
in a 24-lead exposed paddle LFCSP.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

ADL5382 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Distributions for fRF = 900 MHz ............................................... 10

Distributions for fRF = 1900 MHz ............................................. 11

Distributions for fRF = 2700 MHz ............................................. 12

Circuit Description ......................................................................... 13

LO Interface................................................................................. 13

V-to-I Converter ......................................................................... 13

Mixers........................................................................................... 13

Emitter Follower Buffers ........................................................... 13

Bias Circuit .................................................................................. 13

Applications Information .............................................................. 14

Basic Connections ...................................................................... 14

Power Supply ............................................................................... 14

Local Oscillator (LO) Input ...................................................... 14

RF Input ....................................................................................... 15

Baseband Outputs ...................................................................... 15

Error Vector Magnitude (EVM) Performance ........................... 16

Low IF Image Rejection ............................................................. 17

Example Baseband Interface ..................................................... 17

Characterization Setups ................................................................. 21

Evaluation Board ............................................................................ 23

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/12—Rev. 0 to Rev. A

Added θ

Added EPAD Note to Figure 2 ........................................................ 6

Updated Outline Dimensions ....................................................... 27

3/08—Revision 0: Initial Version

= 3°C/W to Table 2......................................................... 5

JC

Rev. A | Page 2 of 28

Data Sheet ADL5382

OPERATING CONDITIONS

Quadrature Phase Error

At 900 MHz

0.2 Degrees

Output Swing

Differential 200 Ω load

2

V p-p

DYNAMIC PERFORMANCE at RF = 900 MHz

Input P1dB

14.4 dBm

SPECIFICATIONS

VS = 5 V, TA = 25°C, fLO = 900 MHz, fIF = 4.5 MHz, PLO = 0 dBm, BIAS pin open, ZO = 50 Ω, unless otherwise noted. Baseband outputs
differentially loaded with 450 Ω. Loss of the balun used to drive the RF port was de-embedded from these measurements.

Table 1.

Parameter Condition Min Typ Max Unit

LO and RF Frequency Range 0.7 2.7 GHz

LO INPUT LOIP, LOIN

Input Return Loss LO driven differentially through a balun at 900 MHz −11 dB
LO Input Level −6 0 +6 dBm

I/Q BASEBAND OUTPUTS QHI, QLO, IHI, ILO

Voltage Conversion Gain 450 Ω differential load on I and Q outputs at 900 MHz 3.9 dB
200 Ω differential load on I and Q outputs at 900 MHz 3.0 dB
Demodulation Bandwidth 1 V p-p signal, 3 dB bandwidth 370 MHz

I/Q Amplitude Imbalance 0.05 dB
Output DC Offset (Differential) 0 dBm LO input at 900 MHz ±5 mV
Output Common Mode VPOS − 2.8 V

0.1 dB Gain Flatness 50 MHz

Peak Output Current Each pin 12 mA

POWER SUPPLIES VPA, VPL, VPB, VPX

Voltage 4.75 5.25 V
Current BIAS pin open 220 mA

R

Conversion Gain 3.9 dB
Input P1dB 14.7 dBm
Second-Order Input Intercept (IIP2) −5 dBm each input tone 73 dBm
Third-Order Input Intercept (IIP3) −5 dBm each input tone 33.5 dBm
LO to RF RFIN, RFIP terminated in 50 Ω −92 dBm
RF to LO LOIN, LOIP terminated in 50 Ω −89 dBc
IQ Magnitude Imbalance 0.05 dB
IQ Phase Imbalance 0.2 Degrees
LO to IQ RFIN, RFIP terminated in 50 Ω −43 dBm
Noise Figure 14.0 dB
Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away 19.9 dB

DYNAMIC PERFORMANCE at RF = 1900 MHz

Conversion Gain 3.9 dB

Second-Order Input Intercept (IIP2) −5 dBm each input tone 65 dBm
Third-Order Input Intercept (IIP3) −5 dBm each input tone 30.5 dBm
LO to RF RFIN, RFIP terminated in 50 Ω −71 dBm
RF to LO LOIN, LOIP terminated in 50 Ω −78 dBc
IQ Magnitude Imbalance 0.05 dB
IQ Phase Imbalance 0.2 Degrees
LO to IQ RFIN, RFIP terminated in 50 Ω −41 dBm
Noise Figure 15.6 dB
Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away 20.5 dB

= 4 kΩ 196 mA

BIAS

Rev. A | Page 3 of 28

ADL5382 Data Sheet

Third-Order Input Intercept (IIP3)

−5 dBm each input tone

28.3 dBm

Parameter Condition Min Typ Max Unit

DYNAMIC PERFORMANCE at RF = 2700 MHz RFIP, RFIN

Conversion Gain 3.3 dB
Input P1dB 14.5 dBm
Second-Order Input Intercept (IIP2) −5 dBm each input tone 52 dBm

LO to RF RFIN, RFIP terminated in 50 Ω, 1xLO appearing at RF port −70 dBm
RF to LO LOIN, LOIP terminated in 50 Ω −55 dBc
IQ Magnitude Imbalance 0.16 dB
IQ Phase Imbalance 0.1 Degrees
LO to IQ RFIN, RFIP terminated in 50 Ω, 1xLO appearing at BB port −42 dBm
Noise Figure 17.6 dB

Rev. A | Page 4 of 28

Data Sheet ADL5382

Operating Temperature Range

−40°C to +85°C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (VPA, VPL, VPB, VPX) 5.5 V
LO Input Power 13 dBm (re: 50 Ω)
RF Input Power 15 dBm (re: 50 Ω)
Internal Maximum Power Dissipation 1230 mW
θJA 54°C/W
θJC 3°C/W
Maximum Junction Temperature 150°C

Storage Temperature Range −65°C to +125°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 28

ADL5382 Data Sheet

1

24

CMRF CMRF RFIP

ADL5382

TOP VIEW

(Not to S cale)

RFIN CMRF VPX

CML

VPA

COM

BIAS

VPL

VPL

VPL

VPB

VPB

QHI

QLO

IHI

ILO

LOIP LOIN CML CML COM

23 22 21 20 19

7 8 9 10 11 12

2

3

4

5

6

18

17

16

15

14

13

07208-002

NOTES

1. CONNECT THE E X P OSED PAD TO A LOW IMP E DANCE
THERMAL AND ELECTRICAL GROUND PLANE.

1, 4 to 6,

VPA, VPL, VPB, VPX

Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

17 to 19
2, 7, 10 to 12,

COM, CML, CMRF Ground. Connect to a low impedance ground plane.

to the board ground using appropriate-sized capacitors.

20, 23, 24
3 BIAS Bias Control. A resistor (R

) can be connected between BIAS and COM to reduce the mixer core

BIAS

current. The default setting for this pin is open.

8, 9 LOIP, LOIN Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended

balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance.

13 to 16 ILO, IHI, QLO, QHI I Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 Ω differential output

impedance (25 Ω per pin). The bias level on these pins is equal to VPOS − 2.8 V. Each output pair can
swing 2 V p-p (differential) into a load of 200 Ω. Output 3 dB bandwidth is 370 MHz.

21, 22 RFIN, RFIP RF Input. A single-ended 50 Ω signal can be applied to the RF inputs through a 1:1 balun (recommended

balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and
RFIN (recommended values = 33 nH).

EP Exposed Paddle. Connect to a low impedance thermal and electrical ground plane.

Rev. A | Page 6 of 28

Data Sheet ADL5382

0

5

10

15

20

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

GAIN

INPUT P1d B

07208-003

RF FREQUE NCY ( M Hz )

GAIN (dB) , IP1dB (d Bm)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

10

20

30

40

50

60

70

80

INPUT IP 3 ( I AND Q CHANNELS)

I CHANNEL
Q CHANNEL

INPUT IP2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-004

RF FREQUE NCY ( M Hz )

IIP3, IIP2 (dBm)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

–2.0

–1.5

–1.0

0

–0.5

0.5

1.0

1.5

2.0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-005

RF FREQUE NCY ( M Hz )

GAIN MIS M ATCH (dB)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

10 100 1000

07208-006

BASEBAND FREQUE NCY ( M Hz )

BASEBAND RESPONS E ( dB)

12

13

14

15

16

17

18

19

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-007

RF FREQUE NCY ( M Hz )

NOISE FIGURE (dB)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

–4

–3

–2

–1

0

1

2

3

4

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-008

RF FREQUE NCY ( M Hz )

QUADRATURE PHASE E RROR (Degrees)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, LO drive level = 0 dBm, R

= open, RF input balun loss is de-embedded, unless otherwise noted.

BIAS

Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs.

RF Frequency

Figure 4. Input Third-Order Intercept (IIP3) and

Input Second-Order Intercept Point (IIP2) vs. RF Frequency

Figure 6. Normalized IQ Baseband Frequency Response

Figure 7. Noise Figure vs. RF Frequency

Figure 5. IQ Gain Mismatch vs. RF Frequency

Figure 8. IQ Quadrature Phase Error vs. RF Frequency

Rev. A | Page 7 of 28

ADL5382 Data Sheet

0

5

10

15

20

–6 –5 –4

–3 –2 –1 0 1 2 3 4 5 6

20

35

50

65

80

IIP3, IIP2 (dBm)

GAIN

IIP3

NOISE FIGURE

IP1dB

IIP2, I CHANNEL

IIP2, Q CHANNEL

07208-009

LO LEVEL (dBm)

GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB)

INPUT IP3

NOISE FIGURE

SUPPLY CURRENT

10

14

18

22

26

30

34

1 10 100

160

170

180

190

200

210

220

230

240

250

SUPPLY CURRENT (mA)

07208-010

R

BIAS

(kΩ)

IIP3 (d Bm) AND NOISE FI GURE (dB)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

13

15

17

19

21

23

25

27

29

–30 –25 –20 –15 –10 –5 0 5

07208-011

RF BLOCKER INPUT POW E R ( dBm)

NOISE FIGURE (dB)

900MHz

1900MHz

2

4

6

8

10

12

14

16

18

15

25

35

45

55

65

75

0

20

–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6

IIP3, IIP2 (dBm)

GAIN

IIP3

NOISE FIGURE

IIP2, I CHANNEL

IIP2, Q CHANNEL

07208-012

LO LEVEL (dBm)

GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB)

IP1dB

8

12

16

20

24

28

32

INPUT IP3

NOISE FIGURE

1 10 100

07208-013

R

BIAS

(kΩ)

IIP3 (d Bm) AND NOISE FI GURE (dB)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

1 10 100

07208-014

R

BIAS

(kΩ)

GAIN (dB) , IP1dB (d Bm) ,

IIP2 I AND Q CHANNEL (dBm)

0

10

20

30

40

50

60

70

80

900MHz: GAIN
900MHz: IP1d B
900MHz: IIP 2, I CHANNEL
900MHz: IIP 2, Q CHANNEL
1900MHz: GAIN
1900MHz: IP1d B
1900MHz: IIP 2, I CHANNEL
1900MHz: IIP 2, Q CHANNEL

Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.

LO Level, f

Figure 10. IIP3, Noise Figure, and Supply Current vs. R

= 900 MHz

RF

, fRF = 900 MHz

BIAS

Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.

LO Level, f

Figure 13. IIP3 and Noise Figure vs. R

= 1900 MHz

RF

, fRF = 1900 MHz

BIAS

Figure 11. Noise Figure vs. Input Blocker Level, f

(RF Blocker 5 MHz Offset)

= 900 MHz, 1900 MHz

RF

Rev. A | Page 8 of 28

Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs.

R

, fRF = 900 MHz, 1900MHz

BIAS

Data Sheet ADL5382

IIP2, I AND Q CHANNELS (dBm)

07208-015

BASEBAND FREQUE NCY ( M Hz )

IP1dB, IIP3 (dBm)

0

5

10

15

20

25

30

35

40

0 10 20 30 40 50

60

65

70

75

80

85

IIP2

IIP3

I CHANNEL
Q CHANNEL

IP1dB

TA = –40°C
T

A

= +25°C

T

A

= +85°C

–80

–70

–60

–50

–40

–30

–20

–10

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-016

LO FREQUENCY (MHz)

LEAKAGE (dBm)

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-017

RF FREQUE NCY ( M Hz )

RETURN LOS S ( dB)

–100

–90

–80

–70

–60

–50

–40

–30

–20

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-018

LO FREQUENCY (MHz)

LEAKAGE (dBm)

–100

–90

–80

–70

–60

–50

–40

–30

–20

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-019

RF FREQUE NCY ( M Hz )

LEAKAGE (dBc)

–30

–25

–20

–15

–10

–5

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-020

LO FREQUENCY (MHz)

RETURN LOS S ( dB)

Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency

Figure 16. LO-to-BB Leakage vs. LO Frequency

Figure 18. LO-to-RF Leakage vs. LO Frequency

Figure 19. RF-to-LO Leakage vs. RF Frequency

Figure 17. RF Port Return L oss vs. RF Frequency Measured on a Characterization

Board through an ETC1-1-13 Balun with 33 nH Bias Inductors

Figure 20. LO Port Return Loss vs. LO Frequency Measured on

Characterization Board through an ETC1-1-13 Balun

Rev. A | Page 9 of 28

ADL5382 Data Sheet

0

20

40

60

80

100

31 32 33 34 35 36 37

07208-021

INPUT IP 3 ( dBm)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

0

20

40

60

80

100

07208-022

INPUT P1d B ( dBm)

PERCENTAGE ( %)

12 13 14 15 16 17

TA = –40°C
T

A

= +25°C

T

A

= +85°C

0

20

40

60

80

100

07208-023

GAIN MIS M ATCH (dB)

PERCENTAGE ( %)

–0.2 –0.1 0 0.1 0.2

TA = –40°C
T

A

= +25°C

T

A

= +85°C

0

20

40

60

80

100

07208-024

INPUT IP 2 ( dBm)

PERCENTAGE ( %)

45 50 55 60 65 70 75 80 85

TA = –40°C
T

A

= +25°C

T

A

= +85°C

I CHANNEL
Q CHANNEL

12.5 13.0 13.5 14.0 14.5 15.0 15.5

0

20

40

60

80

100

07208-025

NOISE FIGURE (dB)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

–1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00

0

20

40

60

80

100

07208-026

QUADRATURE PHASE E RROR (Degrees)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

DISTRIBUTIONS FOR fRF = 900 MHz

Figure 21. IIP3 Distributions, fRF = 900 MHz

Figure 22. IP1dB Distributions, fRF = 900 MHz

Figure 24. IIP2 Distributions for I Channel and Q Channel, fRF = 900 MHz

Figure 25. Noise Figure Distributions, fRF = 900 MHz

Figure 23. IQ Gain Mismatch Distributions, fRF = 900 MHz

Figure 26. IQ Quadrature Phase Error Distributions, fRF = 900 MHz

Rev. A | Page 10 of 28

Data Sheet ADL5382

28 29 30 31 32 33

0

20

40

60

80

100

07208-027

INPUT IP 3 ( dBm)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

TA = +85°C

12 13 14 15 16 17

0

20

40

60

80

100

07208-028

INPUT P1d B ( dBm)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

TA = +85°C

–0.2 –0.1 0 0.1 0.2

0

20

40

60

80

100

07208-029

GAIN MIS M ATCH (dB)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

45 50 55 60 65 70 75 80 85

0

20

40

60

80

100

07208-030

INPUT IP 2 ( dBm)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

I CHANNEL
Q CHANNEL

14.0 14.5 15.0 15.5 16.0 16.5 17.0

0

20

40

60

80

100

07208-031

NOISE FIGURE (dB)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

–1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00

0

20

40

60

80

100

07208-032

QUADRATURE PHASE E RROR (Degrees)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

DISTRIBUTIONS FOR fRF = 1900 MHz

Figure 27. IIP3 Distributions, fRF = 1900 MHz

Figure 28. IP1dB Distributions, fRF = 1900 MHz

Figure 30. IIP2 Distributions for I Channel and Q Channel, fRF = 1900 MHz

Figure 31. Noise Figure Distributions, fRF = 1900 MHz

Figure 29. IQ Gain Mismatch Distributions, fRF = 1900 MHz

Figure 32. IQ Quadrature Phase Error Distributions, fRF = 1900 MHz

Rev. A | Page 11 of 28

ADL5382 Data Sheet

26 27 28 29 30 31

0

20

40

60

80

100

07208-033

INPUT IP 3 ( dBm)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

12 13 14 15 16 17

0

20

40

60

80

100

07208-034

INPUT P1d B ( dBm)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

–0.1 0 0.1 0.2 0.3

0

20

40

60

80

100

07208-035

GAIN MIS M ATCH (dB)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

0

20

40

60

80

100

07208-036

INPUT IP 2 ( dBm)

PERCENTAGE ( %)

45 50 55 60 65 70 75 80 85

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

I CHANNEL
Q CHANNEL

16.0 16.5 17.0 17.5 18.0 18.5 19.0

0

20

40

60

80

100

07208-037

NOISE FIGURE (dB)

PERCENTAGE ( %)

T

A

= –40°C

T

A

= +25°C

T

A

= +85°C

–1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00

0

20

40

60

80

100

07208-038

QUADRATURE PHASE E RROR (Degrees)

PERCENTAGE ( %)

TA = –40°C
T

A

= +25°C

T

A

= +85°C

DISTRIBUTIONS FOR fRF = 2700 MHz

Figure 33. IIP3 Distributions, fRF = 2700 MHz

Figure 34. IP1dB Distributions, fRF = 2700 MHz

Figure 36. IIP2 Distributions for I Channel and Q Channel, fRF = 2700 MHz

Figure 37. Noise Figure Distributions, fRF = 2700 MHz

Figure 35. IQ Gain Mismatch Distributions, fRF = 2700 MHz

Figure 38. IQ Quadrature Phase Error Distributions, fRF = 2700 MHz

Rev. A | Page 12 of 28

Data Sheet ADL5382

RFIP

RFIN

BIAS

POLYPHASE

QUADRATURE

PHASE SPLITTER

IHI

ILO

LOIP

LOIN

QHI

QLO

07208-039

CIRCUIT DESCRIPTION

The ADL5382 can be divided into five sections: the local
oscillator (LO) interface, the RF voltage-to-current (V-to-I)
converter, the mixers, the differential emitter follower outputs,
and the bias circuit. A detailed block diagram of the device is
shown in Figure 39.

Figure 39. Block Diagram

The LO interface generates two LO signals at 90° of phase
difference to drive two mixers in quadrature. RF signals are
converted into currents by the V-to-I converters that feed into
the two mixers. The differential I and Q outputs of the mixers
are buffered via emitter followers. Reference currents to each
section are generated by the bias circuit. A detailed description
of each section follows.

LO INTERFACE

The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase, which splits the LO signal into two differential
signals in quadrature. Each quadrature LO signal then passes
through a limiting amplifier that provides the mixer with a
limited drive signal. For optimal performance, the LO inputs
must be driven differentially.

V-TO-I CONVERTER

The differential RF input signal is applied to a resistively
degenerated common base stage, which converts the differential
input voltage to output currents. The output currents then
modulate the two half frequency LO carriers in the mixer stage.

MIXERS

The ADL5382 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.

EMITTER FOLLOWER BUFFERS

The output emitter followers drive the differential I and Q
signals off-chip. The output impedance is set by on-chip 25 Ω
series resistors that yield a 50 Ω differential output impedance
for each baseband port. The fixed output impedance forms a
voltage divider with the load impedance that reduces the effective
gain. For example, a 500 Ω differential load has 1 dB lower
effective gain than a high (10 kΩ) differential load impedance.

BIAS CIRCUIT

A band gap reference circuit generates the proportional-to­absolute temperature (PTAT) as well as temperature-independent
reference currents used by different sections. The mixer current
can be reduced via an external resistor between the BIAS pin
and ground. When the BIAS pin is open, the mixer runs at
maximum current and therefore the greatest dynamic range.
The mixer current can be reduced by placing a resistance to
ground; therefore, reducing overall power consumption, noise
figure, and IIP3. The effect on each of these parameters is
shown in Figure 10, Figure 13, and Figure 14.

Rev. A | Page 13 of 28

ADL5382 Data Sheet

LO INPUT

ETC1-1-13

LOIP

LOIN

1000pF

8

1000pF

07208-040

9

33nH 33nH

100pF 100pF0.1µF

100pF

1000pF

0.1µF

0.1µF

V

POS

V

POS

LO

V

POS

1

ADL5382

CMRF

CMRF

RFIP

RFIN

CMRF

VPX

CML

LOIP

LOIN

CML

CML

COM

24 23 22 21 20 19

7 8 9 10 11 12

2

3

4

5

6

VPA

COM

BIAS

VPL

VPL

VPL

18

17

16

15

14

13

VPB

QHI

QLO

IHI

ILO

VPB

QHI

QLO

IHI

ILO

1000pF

RFC

07208-041

ETC1-1-13

1000pF

1000pF

ETC1-1-13

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 41 shows the basic connections schematic for the ADL5382.

POWER SUPPLY

The nominal voltage supply for the ADL5382 is 5 V and is
applied to the VPA, VPB, VPL, and VPX pins. Ground should
be connected to the COM, CML, and CMRF pins. The exposed
paddle on the underside of the package should also be soldered
to a low thermal and electrical impedance ground plane. If the
ground plane spans multiple layers on the circuit board, these
layers should be stitched together with nine vias under the
exposed paddle. The Application Note AN-772 discusses the
thermal and electrical grounding of the LFCSP in detail. Each
of the supply pins should be decoupled using two capacitors;
recommended capacitor values are 100 pF and 0.1 µF.

LOCAL OSCILLATOR (LO) INPUT

For optimum performance, the LO port should be driven
differentially through a balun. The recommended balun is
the M/A-COM ETC1-1-13. The LO inputs to the device should
be ac-coupled with 1000 pF capacitors. The LO port is designed
for a broadband 50 Ω match from 700 MHz to 2.7 GHz. The
LO return loss can be seen in Figure 20. Figure 40 shows the LO
input configuration.

Figure 40. Differential LO Drive

The recommended LO drive level is between −6 dBm and +6 dBm.
The applied LO frequency range is between 700 MHz and 2.7 GHz.

Figure 41. Basic Connections Schematic

Rev. A | Page 14 of 28

Data Sheet ADL5382

RF INPUT

RFIN

ETC1-1-13

33nH

33nH

RFIP

1000pF

1000pF

21

22

07208-042

–10

–12

–14

–16

–18

–20

–22

–24

0.7 0.9 1.1 1.5 1.71.3 1.9 2.1 2.3 2.5 2.7 2.9

S11 (dB)

FREQUENCY ( GHz)

07208-043

QHI

QLO

IHI

ILO

QHI

QLO

IHI

ILO

16

15

14

13

07208-044

RF INPUT

The RF inputs have a differential input impedance of
approximately 50 Ω. For optimum performance, the RF port
should be driven differentially through a balun. The recommended
balun is the M/A-COM ETC1-1-13. The RF inputs to the device
should be ac-coupled with 1000 pF capacitors. Ground-referenced
choke inductors must also be connected to RFIP and RFIN (the
recommended value is 33 nH, Coilcraft 0603CS-33NX) for
appropriate biasing. Several important aspects must be taken
into account when selecting an appropriate choke inductor for
this application. First, the inductor must be able to handle the
approximately 40 mA of standing dc current being delivered
from each of the RF input pins (RFIP, RFIN). The suggested
0603 inductor has a 600 mA current rating. The purpose of the
choke inductors is to provide a very low resistance dc path to
ground and high ac impedance at the RF frequency so as not to
affect the RF input impedance. A choke inductor that has a self­resonant frequency greater than the RF input frequency ensures
that the choke is still looking inductive and therefore has a more
predictable ac impedance (jωL) at the RF frequency. Figure 42
shows the RF input configuration.

The differential RF port return loss is characterized as shown in
Figure 43.

Figure 43. Differential RF Port Return Loss

BASEBAND OUTPUTS

The baseband outputs QHI, QLO, IHI, and ILO are fixed
impedance ports. Each baseband pair has a 50 Ω differential
output impedance. The outputs can be presented with differential
loads as low as 200 Ω (with some degradation in gain) or high
impedance differential loads (500 Ω or greater impedance yields
the same excellent linearity) that is typical of an ADC. The
TCM9-1 9:1 balun converts the differential IF output to single­ended. When loaded with 50 Ω, this balun presents a 450 Ω
load to the device. The typical maximum linear voltage swing
for these outputs is 2 V p-p differential. The bias level on these
pins is equal to VPOS − 2.8 V. The output 3 dB bandwidth is
370 MHz. Figure 44 shows the baseband output configuration.

Figure 42. RF Input

Figure 44. Baseband Output Configuration

Rev. A | Page 15 of 28

ADL5382 Data Sheet

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–65–85 –75 –55 –45 –35

–25 –15 –5

07208-045

RF INPUT P OWER (dBm)

EVM (dB)

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–65 –60 –55 –50 –45 –40

–35 –30 –25 –20 –15 –10 –5 0 5 10

07208-046

RF INPUT P OWER (dBm)

EVM (dB)

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–75 –70 –65 –60 –55 –50 –45 –40 –35 –30

–25 –20 –15 –10 –5

0Hz

7.5MHz

5MHz

07208-047

RF INPUT P OWER (dBm)

EVM (dB)

2.5MHz

ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE

EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver
would have all constellation points at the ideal locations; however,
various imperfections in the implementation (such as magnitude
imbalance, noise floor, and phase imbalance) cause the actual
constellation points to deviate from the ideal locations.

The ADL5382 shows excellent EVM performance for various
modulation schemes. Figure 45 shows the EVM performance of
the ADL5382 with a 16 QAM, 200 kHz low IF.

Figure 45. EVM, RF = 900 MHz, IF = 200 kHz vs.

RF Input Power for a 16 QAM 160 ksym/s Signal

Figure 46 shows the zero-IF EVM performance of a 10 MHz
IEEE 802.16e WiMAX signal through the ADL5382. The
differential dc offsets on the ADL5382 are in the order of a few
millivolts. However, ac coupling the baseband outputs with
10 µF capacitors eliminates dc offsets and enhances EVM
performance. With a 10 MHz BW signal, 10 µF ac coupling
capacitors with the 500 Ω differential load results in a high-pass
corner frequency of ~64 Hz, which absorbs an insignificant
amount of modulated signal energy from the baseband signal.
By using ac-coupling capacitors at the baseband outputs, the dc
offset effects, which can limit dynamic range at low input power
levels, can be eliminated.

Figure 46. EVM, RF = 2.6 GHz, IF = 0 Hz vs. RF Input Power for a 16 QAM

10 MHz Bandwidth Mobile WiMAX Signal (AC-Coupled Baseband Outputs)

Figure 47 exhibits multiple W-CDMA low-IF EVM
performance curves over a wide RF input power range into the
ADL5382. In the case of zero-I F, t he noise contribution by the
vector signal analyzer becomes predominant at lower power
levels, making it difficult to measure SNR accurately.

Figure 47. EVM, RF = 1900 MHz, IF = 0 Hz, 2.5 MHz, 5 MHz, and 7.5 MHz vs. RF

Input Power for a W-CDMA Signal (AC-Coupled Baseband Outputs)

Rev. A | Page 16 of 28

Data Sheet ADL5382

0°

0°

SIN

ω

LO

t

COS

ω

LO

t

ω

IF

ω

IF

ω

LSB

ω

USB

–

ω

IF

0 +

ω

IF

0 +

ω

IF

0 +

ω

IF

–

ω

IF

0 +

ω

IF

ω

LO

–90°

+90°

07208-048

700 900 1100 1300 1500 1700 1900 2100 2300

2500 2700

0

10

20

30

40

50

60

70

07208-049

RF FREQUE NCY ( M Hz )

IMAGE REJE CTION (dB)

2.5MHz LOW IF

5MHz LOW IF

7.5MHz LOW IF

Figure 48. Illustration of the Image Problem

LOW IF IMAGE REJECTION

The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels. Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the down conversion process.
Figure 48 illustrates the image problem. If the upper sideband
(lower sideband) is the desired band, a 90° shift to the Q channel
(I channel) cancels the image at the lower sideband (upper
sideband). Phase and gain balance between I and Q channels
are critical for high levels of image rejection.

Figure 49 shows the excellent image rejection capabilities of
the ADL5382 for low IF applications, such as W-CDMA. The
ADL5382 exhibits image rejection greater than 45 dB over a
broad frequency range.

Figure 49. Image Rejection vs. RF Frequency for a W-CDMA Signal,

IF = 2.5 MHz, 5 MHz, and 7.5 MHz

EXAMPLE BASEBAND INTERFACE

In most direct conversion receiver designs, it is desirable to
select a wanted carrier within a specified band. The desired
channel can be demodulated by tuning the LO to the appropriate
carrier frequency. If the desired RF band contains multiple
carriers of interest, the adjacent carriers would also be down
converted to a lower IF frequency. These adjacent carriers can
be problematic if they are large relative to the wanted carrier as
they can overdrive the baseband signal detection circuitry. As a
result, it is often necessary to insert a filter to provide sufficient
rejection of the adjacent carriers.

It is necessary to consider the overall source and load impedance
presented by the ADL5382 and ADC input to design the filter
network. The differential baseband output impedance of the
ADL5382 is 50 Ω. The ADL5382 is designed to drive a high
impedance ADC input. It may be desirable to terminate the
ADC input down to lower impedance by using a terminating
resistor, such as 500 Ω. The terminating resistor helps to better
define the input impedance at the ADC input at the cost of a
slightly reduced gain (see the Circuit Description section for
details on the emitter-follower output loading effects). The order
and type of filter network depends on the desired high frequency
rejection required, pass-band ripple, and group delay. Filter
design tables provide outlines for various filter types and orders,
illustrating the normalized inductor and capacitor values for a
1 Hz cutoff frequency and 1 Ω load. After scaling the normalized
prototype element values by the actual desired cut-off frequency
and load impedance, the series reactance elements are halved to
realize the final balanced filter network component values.

Rev. A | Page 17 of 28

ADL5382 Data Sheet

V

S

R

S

2

R

S

R

L

R

S

2

R

L

2

R

L

2

433pF

V

S

RS = 50Ω

R

L

= 500Ω

0.54µH

0.27µH

0.27µH

433pF

BALANCED

CONFIGURATION

DENORMALIZED

SINGLE-ENDED

EQUIVALENT

V

S

RS = 50Ω

= 0.1

R

L

= 500Ω

L

N

= 0.074H

C

N

14.814F

NORMALIZED

SINGLE-ENDED

CONFIGURATION

= 25Ω

= 25Ω

= 250Ω

= 250Ω

f

C

= 10.9MHz

f

C

= 1Hz

07208-050

10

5

–20

–15

–10

–5

0

0 3.53.02.52.01.51.00.5

MAGNITUDE RESPONSE (dB)

FREQUENCY (MHz)

07208-051

900

800

700

600

500

400

300

200

100

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

DELAY (ns)

FREQUENCY (MHz)

07208-052

As an example, a second-order Butterworth, low-pass filter
design is shown in Figure 50 where the differential load impedance
is 500 Ω and the source impedance of the ADL5382 is 50 Ω. The
normalized series inductor value for the 10-to-1, load-to-source
impedance ratio is 0.074 H, and the normalized shunt capacitor
is 14.814 F. For a 10.9 MHz cutoff frequency, the single-ended
equivalent circuit consists of a 0.54 µH series inductor followed
by a 433 pF shunt capacitor.

The balanced configuration is realized as the 0.54 µH inductor
is split in half to realize the network shown in Figure 50.

Figure 51 and Figure 52 show the measured frequency response
and group delay of the filter.

Figure 50. Second-Order Butterworth, Low-Pass Filter Design Example

A complete design example is shown in Figure 53. A sixth-order
Butterworth differential filter having a 1.9 MHz corner frequency
interfaces the output of the ADL5382 to that of an ADC input.
The 500 Ω load resistor defines the input impedance of the
ADC. The filter adheres to typical direct conversion W-CDMA
applications, where 1.92 MHz away from the carrier IF frequency,
1 dB of rejection is desired and 2.7 MHz away 10 dB of rejection
is desired.

Figure 51. Sixth-Order Baseband Filter Response

Figure 52. Sixth-Order Baseband Filter Group Delay

Rev. A | Page 18 of 28

Data Sheet ADL5382

100pF 0.1µF

100pF0.1µF

0.1µF 100pF

V

POS

V

POS

V

POS

1

ADL5382

CMRF

CMRF

RFIP

RFIN

CMRF

VPX

CML

LOIP

LOIN

CML

CML

COM

24 23 22 21 20 19

7 8 9 10 11 12

2

3

4

5

6

VPA

COM

BIAS

VPL

VPL

VPL

18

17

16

15

14

13

VPB

VPB

QHI

QLO

IHI

ILO

C

AC

10µF

C

AC

10µF

27µH

27µH

270pF

27µH

27µH

100pF

10µH

10µH

68pF

500Ω

C

AC

10µF

C

AC

10µF

27µH

27µH

270pF

27µH

27µH

100pF

10µH

10µH

68pF

500Ω

ADC INPUT

ADC INPUT

07208-053

33nH 33nH

1000pF

LO

1000pF

RFC

ETC1-1-13

1000pF

1000pF

ETC1-1-13

Figure 53. Sixth-Order Low-Pass Butterworth, Baseband Filter Schematic

Rev. A | Page 19 of 28

ADL5382 Data Sheet

10µH

10µH

680pF

8µH

8µH

100pF

200Ω

50Ω

07208-054

–15

–10

–5

0

–20

5

07208-055

FREQUENCY (MHz)

MAGNITUDE RESPONSE (dB)

3.83.43.02.62.21.81.41.00.60.2

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.00.2

200

300

400

500

600

700

800

100

900

07208-056

FREQUENCY (MHz)

DELAY (ns)

As the load impedance of the filter increases, the filter design
becomes more challenging in terms of meeting the required
rejection and pass band specifications. In the previous W­CDMA example, the 500 Ω load impedance resulted in the
design of a sixth-order filter that has relatively large inductor
values and small capacitor values. If the load impedance is 200 Ω,
the filter design becomes much more manageable. As shown in
Figure 54, the resultant inductor and capacitor values become
much more practical.

Figure 54. Fourth-Order Low-Pass W-CDMA Filter Schematic

Figure 55 and Figure 56 illustrate the magnitude response and
group delay response of the fourth-order filter, respectively.

Figure 55. Fourth-Order Low-Pass W-CDMA Filter Magnitude Response

Figure 56. Fourth-Order Low-Pass W-CDMA Filter Group Delay Response

Rev. A | Page 20 of 28

Data Sheet ADL5382

CHARACTERIZATION SETUPS

Figure 57 to Figure 59 show the general characterization bench
setups used extensively for the ADL5382. The setup shown in
Figure 59 was used to do the bulk of the testing and used
sinusoidal signals on both the LO and RF inputs. An automated
Agilent VEE program was used to control the equipment over
the IEEE bus. This setup was used to measure gain, IP1dB, IIP2,
IIP3, I/Q gain match, and quadrature error. The ADL5382
characterization board had a 9-to-1 impedance transformer on
each of the differential baseband ports to do the differential-to­single-ended conversion, which presented a 450 Ω differential load
to each baseband port, when interfaced with 50 Ω test equipment.
For all measurements of the ADL5382, the loss of the RF input
balun (the M/A-COM ETC1-1-13 was used on RF input during
characterization) was de-embedded.

SNS

CONTROL

OUTPUT

The two setups shown in Figure 57 and Figure 58 were used for
making NF measurements. Figure 57 shows the setup for
measuring NF with no blocker signal applied while Figure 58
was used to measure NF in the presence of a blocker. For both
setups, the noise was measured at a baseband frequency of
10 MHz. For the case where a blocker was applied, the output
blocker was at a 15 MHz baseband frequency. Note that great
care must be taken when measuring NF in the presence of a
blocker. The RF blocker generator must be filtered to prevent its
noise (which increases with increasing generator output power)
from swamping the noise contribution of the ADL5382. At least
30 dB of attention at the RF and image frequencies is desired.
For example, assume a 915 MHz signal applied to the LO inputs of
the ADL5382. To obtain a 15 MHz output blocker signal, the RF
blocker generator is set to 930 MHz and the filters tuned such
that there is at least 30 dB of attenuation from the generator at
both the desired RF frequency (925 MHz) and the image RF
frequency (905 MHz). Finally, the blocker must be removed
from the output (by the 10 MHz low-pass filter) to prevent the
blocker from swamping the analyzer.

AGILENT N8974A

NOISE FI GURE ANALYZE R

Q

I

IEEE

R1

50Ω

FROM SNS PORT

LOW-PASS

FILTER

INPUT

PC CONTR OLLE R

IEEE

07208-057

HP 6235A

POWER SUPPLY

AGILENT 8665B

SIGNAL GE NERATOR

RF

GND

ADL5382

CHAR BOARD

V

POS

LO

6dB PAD

Figure 57. General Noise Figure Measurement Setup

Rev. A | Page 21 of 28

ADL5382 Data Sheet

R&S FSEA30

SPECTRUM ANAL Y ZER

HP 6235A

POWER SUPPLY

AGILENT 8665B

SIGNAL GENERATOR

LOW-PASS

FILTER

R&S SMT03

SIGNAL GENERATOR

ADL5382

CHAR BOARD

RF

LO

Q

I

GND
V

POS

6dB PAD

6dB PAD

6dB PAD

R1

50Ω

BAND-PASS

CAVITY FILTER

BAND-PASS

TUNABLE FILTER

BAND-REJECT

TUNABLE FILTER

HP87405

LOW NOISE

PREAMP

07208-058

R&S FSEA30

SPECTRUM ANAL Y ZER

HP 8508A

VECTOR VOLTMETER

R&S SMT06

AGILENT E3631

PWER SUPPLY

AGILENT E8257D

SIGNAL GENERATOR

PC CONTROLLER

R&S SMT06

IEEE IEEE IEEE IEEE

IEEE

IEEE

ADL5382

CHAR BOARD

RF

LO

Q

I

GND
V

POS

6dB PAD

6dB PAD

6dB PAD

6dB PAD

SWITCH
MATRIX

RF

AMPLIFIER

VP GND

OUTIN

3dB PAD

3dB PAD

3dB PAD

3dB PAD

RF

RF

AGILENT

11636A

INPUT CHANNEL S

A AND B

RF

INPUT

IEEE

07208-059

Figure 58. Measurement Setup for Noise Figure in the Presence of a Blocker

Figure 59. General Characterization Setup

Rev. A | Page 22 of 28

Data Sheet ADL5382

RFC

C11

C8

R14

R16

R10

C12

R15

T2

T3

R9

R11

C9

C10

C2C1

C3 C4

R1

R2

VPOS

VPOS

LO

C7C6

V

POS

T1

T4

1

ADL5382

CMRF

CMRF

RFIP

RFIN

CMRF

VPX

CML

LOIP

LOIN

CML

CML

COM

24 23 22 21 20 19

7 8 9 10 11 12

2

3

4

5

6

VPA

COM

BIAS

VPL

VPL

VPL

18

17

16

15

14

13

VPB

Q OUTPUT OR QHI

QLO

I OUTPUT OR IHI

ILO

VPB

QHI

QLO

IHI

ILO

R8 R7

L2 L1

R6

R3

R4

R13

C13

R5

R12

07208-060

EVALUATION BOARD

The ADL5382 evaluation board is available. The board can be
used for single-ended or differential baseband analysis. The default
configuration of the board is for single-ended baseband analysis.

Figure 60. Evaluation Board Schematic

Rev. A | Page 23 of 28

ADL5382 Data Sheet

Table 4. Evaluation Board Configuration Options

Component Function Default Condition

VPOS, GND Power Supply and Ground Vector Pins. Not applicable
R1, R3, R6 Power Supply Decoupling. Shorts or power supply decoupling resistors. R1, R3, R6 = 0 Ω (0603)
C1, C2, C3,

C4, C8, C9
C6, C7,

C10, C11
R4, R5,

R9 to R16

The user can reconfigure the board to use full differential baseband outputs. R9 to R12

L1, L2,
R7, R8

T2, T3 IF Output Interface. TCM9-1 converts a differential high impedance IF output to a single-

C12, C13 Decoupling Capacitors. C12 and C13 are the decoupling capacitors used to reject noise

T4 LO Input Interface. The LO is driven differentially. ETC1-1-13 is a 1:1 RF balun that

T1 RF Input Interface. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input

R2 R

These capacitors provide the required decoupling up to 2.7 GHz. C2, C4, C8 = 100 pF (0402)

C1, C3, C9 = 0.1 µF (0603)

AC Coupling Capacitors. These capacitors provide the required ac coupling from
700 MHz to 2.7 GHz.

Single-Ended Baseband Output Path. This is the default configuration of the evaluation
board. R14 to R16 and R4, R5, and R13 are populated for appropriate balun interface.

C6, C10, C11 = 1000 pF (0402)
C7 = open

R4, R5, R13 to R16 = 0 Ω (0402)
R9 to R12 = open

R9, R10 and R11, R12 are not populated. Baseband outputs are taken from QHI and IHI.

provide a means to bypass the 9:1 TCM9-1 transformer to allow for differential baseband
outputs. Access the differential baseband signals by populating R9 to R12 with 0 Ω and
not populating R4, R5, R13 to R16. This way the transformer does not need to be
removed. The baseband outputs are taken from the SMAs of Q_HI, Q_LO, I_HI, and I_LO.

Input Biasing. Inductance and resistance sets the input biasing of the common
base input stage. The default value is 33 nH.

L1, L2 = 33 nH (0603CS-33NX,
Coilcraft)
R7, R8 = 0 Ω (0402)

T2, T3 = TCM9-1, 9:1

ended output. When loaded with 50 Ω, this balun presents a 450 Ω load to the device.

(Mini-Circuits)

The center tap can be decoupled through a capacitor to ground.

C12, C13 = 0.1 µF (0402)

on the center tap of the TCM9-1.

T4 = ETC1-1-13, 1:1 (M/A-COM)

converts the single-ended RF input to differential signal.

T1 = ETC1-1-13, 1:1 (M/A-COM)

to differential signal.

. Optional bias setting resistor. See the Bias Circuit section to see how to use this feature. R2 = open

BIAS

Rev. A | Page 24 of 28

Data Sheet ADL5382

07208-061

07208-062

Figure 61. Evaluation Board Top Layer

Figure 62. Evaluation Board Top Layer Silkscreen

Rev. A | Page 25 of 28

ADL5382 Data Sheet

07208-063

07208-064

Figure 63. Evaluation Board Bottom Layer

Figure 64. Evaluation Board Bottom Layer Silkscreen

Rev. A | Page 26 of 28

Data Sheet ADL5382

COMPLIANT

TO

JEDEC STANDARDS MO-220-VGGD- 2

04-09-2012-A

1

0.50

BSC

PIN 1
INDICATOR

2.50 REF

0.50

0.40

0.30

TOP VIEW

12° MAX

0.80 MAX

0.65 TYP

SEATING

PLANE

COPLANARITY

0.08

1.00

0.85

0.80

0.30

0.23

0.18

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

2.45

2.30 SQ

2.15

24

7

19

12

13

18

6

0.60 MAX

0.60 MAX

PIN 1

INDICATOR

4.10

4.00 SQ

3.90

3.75 BSC
SQ

EXPOSED

PAD

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

BOTTOM VIEW

ADL5382ACPZ-R7

–40°C to +85°C

24-Lead LFCSP_VQ, 7” Tape and Reel

CP-24-2

1,500

OUTLINE DIMENSIONS

Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Ordering Quantity

ADL5382ACPZ-WP –40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64
ADL5382-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 27 of 28

ADL5382 Data Sheet

©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D07208-0-5/12(A)

Rev. A | Page 28 of 28