Datasheet ADL5373 Datasheet (ANALOG DEVICES)

2300 MHz to 3000 MHz

FEATURES

Output frequency range: 2300 MHz to 3000 MHz
Modulation bandwidth: >500 MHz (3 dB)
Output third-order intercept: 26 dBm @ 2500 MHz
1 dB output compression: 13.8 dBm @ 2500 MHz
Noise floor: −157.1 dBm/Hz @ 2500 MHz
Sideband suppression: −57 dBc @ 2500 MHz
Carrier feedthrough: −32 dBm @ 2500 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP

APPLICATIONS

WiMAX/broadband wireless access systems
Satellite modems

GENERAL DESCRIPTION

The ADL5373 supports a frequency of operation from 2300 MHz
to 3000 MHz and is a pin-compatible member of the fixed gain
quadrature modulator (F-MOD) family designed for use from
300 MHz to 4000 MHz. The ADL5373 provides excellent phase
accuracy and amplitude balance enabling high performance
intermediate frequency or direct radio frequency modulation
for communications systems.

The ADL5373 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low
IF-to-RF applications and in broadband digital predistortion
transmitters.

Quadrature Modulator

ADL5373

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

LOIP

LOIN

QBBN

QBBP

The ADL5373 accepts two differential baseband inputs that
are mixed with a local oscillator (LO) to generate a single­ended output.

The ADL5373 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available
in a 24-lead, exposed paddle, Pb-free LFCSP. Performance is
specified over a −40°C to +85°C temperature range. A Pb-free
evaluation board is available.

QUADRATURE

PHASE

SPLITTER

Figure 1.

VOUT

06664-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

ADL5373

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

Circuit Description..................................................................... 11

Basic Connections.......................................................................... 12

Power Supply and Grounding................................................... 12

Baseband Inputs.......................................................................... 12

LO Input ...................................................................................... 12

RF Output.................................................................................... 12

Optimization............................................................................... 13

Applications Information.............................................................. 14

DAC Modulator Interfacing ..................................................... 14

Limiting the AC Swing.............................................................. 14

Filtering........................................................................................ 14

Using the AD9779 Auxiliary DAC for Carrier Feedthrough

Nulling ......................................................................................... 15

WiMAX Operation .................................................................... 15

LO Generation Using PLLs ....................................................... 16

Transm i t DAC O p tions ............................................................. 16

Modulator/Demodulator Options ........................................... 16

Evaluation Board ............................................................................ 17

Characterization Setup .................................................................. 18

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Changes to Features and General Description ............................. 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Figure 3, Figure 4, and Figure 6 to Figure 8.............. 7

Changes to Figure 9 to Figure 14.................................................... 8

Changes to Figure 15 to Figure 20.................................................. 9

Changes to Figure 21 to Figure 23................................................ 10

Changes to Optimization Section and Figure 27 ....................... 13

Changes to Figure 35...................................................................... 15

Changes to WiMAX Operation Section and Figure 36............. 16

Changes to Evaluation Board Section.......................................... 17

Changes to Characterization Setup Section................................ 18

6/07—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADL5373

SPECIFICATIONS

VS = 5 V, TA = 25°C, LO = 0 dBm1, baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias,
baseband I/Q frequency (f

Table 1.

Parameter Conditions Min Typ Max Unit

OPERATING FREQUENCY RANGE Low frequency 2300 MHz

High frequency 3000 MHz

LO = 2300 MHz

Output Power VIQ = 1.4 V p-p differential 4.2 dBm
Output P1dB 11.0 dBm
Carrier Feedthrough −35 dBm
Sideband Suppression −57 dBc
Quadrature Error <0.2 Degrees
I/Q Amplitude Balance 0.06 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
WiMAX 802.16e

LO = 2500 MHz

Output Power VIQ = 1.4 V p-p differential 7.1 dBm
Output P1dB 13.8 dBm
Carrier Feedthrough −32 dBm
Sideband Suppression −57 dBc
Quadrature Error 0.3 Degrees
I/Q Amplitude Balance 0.06 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor

WiMAX 802.16e

LO = 2700 MHz

Output Power VIQ = 1.4 V p-p differential 7.7 dBm
Output P1dB 13.8 dBm
Carrier Feedthrough −33 dBm
Sideband Suppression −54 dBc
Quadrature Error <0.2 Degrees
I/Q Amplitude Balance 0.07 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
WiMAX 802.16e

LO INPUTS

LO Drive Level

1

Input Return Loss See Figure 9 for a plot of return loss vs. frequency −6 dB

) = 1 MHz, unless otherwise noted.

BB

− P(fLO ± (2 × fBB)), P

OUT

− P(fLO ± (3 × fBB)), P

OUT

10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal,
30 MHz carrier offset, P

− P(fLO ± (2 × fBB)), P

OUT

− P(fLO ± (3 × fBB)), P

OUT

I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset

10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal,
30 MHz carrier offset, P

− P(fLO ± (2 × fBB)), P

OUT

− P(fLO ± (3 × fBB)), P

OUT

10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal,
30 MHz carrier offset, P

Characterization performed at typical level −6 0 +6 dBm

= 4.6 dBm −58 dBc

OUT

= 4.6 dBm −49 dBc

OUT

= −1.5 dBm per tone 56 dBm

OUT

= −1.5 dBm per tone 25 dBm

OUT

−158.6 dBm/Hz

= −10 dBm, PLO = 0 dBm

OUT

= 7.1 dBm −57 dBc

OUT

= 7.1 dBm −47 dBc

OUT

= 1.1 dBm per tone 58 dBm

OUT

= 1.1 dBm per tone 26 dBm

OUT

−157.1 dBm/Hz

−157.4 dBm/Hz

= −10 dBm, PLO = 0 dBm

OUT

= 7.7 dBm −55 dBc

OUT

= 7.7 dBm −47 dBc

OUT

= 1.6 dBm per tone 57 dBm

OUT

= 1.6 dBm per tone 25 dBm

OUT

−155.3 dBm/Hz

= −10 dBm, PLO = 0 dBm

OUT

Rev. A | Page 3 of 20

ADL5373

Parameter Conditions Min Typ Max Unit

BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN

I and Q Input Bias Level 500 mV
Input Bias Current

Current sourcing from each baseband input with a bias of
500 mV dc

2

Input Offset Current 0.1 μA
Differential Input Impedance fBB = 1 MHz 40||1.5 kΩ||pF
Bandwidth

LO = 2500 MHz, baseband input = 700 mV p-p sine wave on
500 mV dc

0.1 dB 70 MHz
1 dB 350 MHz

POWER SUPPLIES Pin VPS1 and Pin VPS2

Voltage 4.75 5.25 V
Supply Current 174 mA

1

Driven through Johanson Technology balun (Model 2450BL15B050)

2

See V-to-I Converter section for architecture information.

45 μA

Rev. A | Page 4 of 20

ADL5373

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPSx 5.5 V
IBBP, IBBN, QBBP, and QBBN 0 V to 2 V
LOIP and LOIN 13 dBm
Internal Power Dissipation 1119 mW
θJA (Exposed Paddle Soldered Down) 54°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 20

ADL5373

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QBBP

COM4

QBBN

COM4

IBBN

IBBP

2422232120

19

COM1
COM1

VPS1
VPS1
VPS1
VPS1

1
2
3
4
5
6

ADL5373

TOP VIEW

(Not to Scale)

798

101112

LOIP

LOIN

COM2

COM2

COM3

VPS5

18

VPS4

17

VPS3

16

VPS2

15

VPS2

14

VOUT

13

COM3

06664-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 7, 10 to 12, 21, 22 COM1 to COM4 Input Common Pins. Connect to ground plane via a low impedance path.
3 to 6, 14 to 18 VPS1 to VPS5

Positive Supply Voltage Pins. All pins should be connected to the same supply (V
ensure adequate external bypassing, connect 0.1 μF capacitors between each pin and
ground. Adjacent power supply pins of the same name can share one capacitor (see
Figure 25).

8, 9 LOIP, LOIN

13 VOUT

50 Ω Differential Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
See

Figure 8 for LO input impedance.

Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The
output is ground referenced.

19, 20, 23, 24 IBBP, IBBN, QBBN, QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs
must be dc-biased to 500 mV dc and must be driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a
differential drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and
must be externally biased.

Exposed Paddle Connect to the ground plane via a low impedance path.

). To

S

Rev. A | Page 6 of 20

ADL5373

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, LO = 0 dBm, baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias,
baseband I/Q frequency (f

10

9

TA = –40°C

8

7

6

5

4

3

SSB OUTPUT POWER (dBm)

2

1

0

2300 3000

2400 2500 2600 2700 2800 2900

Figure 3. Single Sideband (SSB) Output Power (P

LO Frequency (f

) = 1 MHz, unless otherwise noted.

BB

TA = +25°C

TA = +85°C

LO FREQUENCY (MHz)

) vs.

) and Temperature

LO

OUT

17

16

TA = –40°C

15

14

13

12

11

10

9

1dB OUTPUT COMPRESSI ON (dBm)

8

06664-003

7

2300 3000

2400 2500 2600 2700 2800 2900

TA = +25°C

TA = +85°C

LO FREQUENCY (MHz)

06664-006

Figure 6. SSB Output P1dB Compression Point (OP1dB) vs.

f

and Temperature

LO

10

9

8

7

VS = 5.25V

6

5

4

3

SSB OUTPUT POWER (dBm)

2

1

0
2300 3000

Figure 4. Single Sideband (SSB) Output Power (P

5

0

VS = 5.0V

VS = 4.75V

2400 2500 2600 2700 2800 2900

LO FREQUENCY (MHz)

f

and Supply

LO

OUT

) vs.

17

16

15

14

13

12

11

10

9

1dB OUTPUT COMPRESSI ON (dBm)

8

06664-004

7

2300 3000

2400 2500 2600 2700 2800 2900

VS = 5.0V

LO FREQUENCY (MHz)

VS = 5.25V

VS = 4.75V

06664-007

Figure 7. SSB Output P1dB Compression Point (OP1dB) vs.

f

and Supply

LO

90

120

2300MHz

150

3000MHz

2300MHz

60

30

0180

OUTPUT PO WER VARIANCE (d B)

–5

1 10 100 1000

BASEBAND FREQUENCY (M Hz)

Figure 5. I and Q Input Bandwidth Normalized to

Gain @ 1 MHz (f

= 2500 MHz)

LO

06664-005

Rev. A | Page 7 of 20

300

330

06664-008

210

240

3000MHz

S11 OF LO
S22 OF OUTPUT

270

Figure 8. Smith Chart of LOIP (LOIN AC-Coupled to Ground) S11 and

VOUT S22 (f

from 2300 MHz to 3000 MHz)

LO

ADL5373

–

0

–5

–10

–15

RETURN LOSS (d B)

–20

–25

2300 2400 2500 2600 2700 2800 2900 3000

LO FREQ UENCY (MHz)

Figure 9. Return Loss (S11) of LOIP with LOIN AC-Coupled to Ground vs. f

0

–10

–20

–30

–40

–50

TA = –40°C

TA = +25°C

TA = +85°C

0

–10

–20

–30

–40

–50

–60

SIDEBAND SUPPRESSION (dBc)

–70

06664-009

–80

TA = +25°C

2300 3000

2400 2500 2600 2700 2800 2900

LO

Figure 12. Sideband Suppression vs. f

TA = –40°C

LO FREQUENCY (MHz)

TA = +85°C

and Temperature;

LO

06664-012

Multiple Devices Shown

0

–10

–20

–30

–40

–50

TA = +85°C

TA = –40°C

–60

CARRIER FEEDTHRO UGH (dBm)

–70

–80

2300 3000

2400 2500 2600 2700 2800 2900

LO FREQUENCY (MHz)

Figure 10. Carrier Feedthrough vs. f

Multiple Devices Shown

0

–10

–20

–30

–40

–50

–60

CARRIER FEEDTHROUG H (dBm)

–70

–80

2300 3000

TA = +85°C

2400 2500 2600 2700 2800 2900

LO FREQUENCY (MHz)

Figure 11. Carrier Feedthrough vs. f

Multiple Devices Shown

and Temperature;

LO

TA = –40°C

TA = +25°C

and Temperature after Nulling at 25°C;

LO

–60

SIDEBAND SUPPRESSION (dBc)

–70

06664-010

Figure 13. Sideband Suppression vs. f

TA = +25°C

–80

2300 3000

2400 2500 2600 2700 2800 2900

LO FREQUENCY (MHz)

and Temperature afte r Nulli ng at 25°C;

LO

06664-013

Multiple Devices Shown

20

–30

–40

–50

–60

SIDEBAND SUPPRESSI ON

–70

DISTORTI ON, CARRIER FE EDTHROUGH,

06664-011

SECOND-ORDER DISTORTI ON, THIRD-O RDER

–80

CARRIER

FEEDTHROUG H (dBm)

SSB OUTPUT

POWER (d Bm)

SECOND-ORDER

DISTORTION (dBc)

0.2 3.4

0.6 1.0 1.4 1.8 2. 2 2. 6 3. 0

BASEBAND INPUT VO LTAGE ( V p-p)

THIRD-ORDER

DISTORTION (dBc)

SIDEBAND

SUPPRESSION (dBc)

15

10

5

0

–5

–10

–15

SSB OUTPUT POWER (dBm)

06664-014

Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. Baseband Differential Input Level

OUT

= 2300 MHz)

(f

LO

Rev. A | Page 8 of 20

ADL5373

–

–

–

–

20

–30

–40

–50

CARRIER

FEEDTHROUG H (dBm)

SSB OUTPUT P OWER (d Bm)

SIDEBAND

SUPPRESSION (dBc)

15

10

5

0

30

TA = –40°C

25

TA = +25°C

20

15

TA = +85°C

–60

SIDEBAND SUPPRESSI ON

DISTORTI ON, CARRIER FE EDTHROUGH,

SECOND-ORDER DISTORTI ON, THIRD-O RDER

THIRD-ORDER

–70

DISTORTION (dBc)

–80

0.2 3.4

0.61.01.41.82.22.63.0

BASEBAND INPUT VOLTAGE (V p-p)

SECOND-ORDER

DISTORTION (dBc)

Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

20

–30

THIRD-ORDER
DISTORTION

–40

T

= +85°C

A

–50

–60

SECOND-ORDER

THIRD-ORDER DIS TORTION (dBc)

–70

SECOND-ORDER DIS TORTIO N AND

DISTORTI ON
T

= +85°C

A

–80

2300 3000

2400 2500 2600 2700 2800 2900

Figure 16. Second- and Third-Order Distortion vs. f

vs. Baseband Differential Input Level

OUT

(f

= 2700 MHz)

LO

THIRD-ORDER
DISTORTION
T

= –40°C

A

SECOND-ORDER
DISTORTI ON
T

= +25°C

A

LO FREQUE NCY (MHz)

THIRD-ORDER
DISTORTI ON
T

= +25°C

A

SECOND-ORDER
DISTORTION
T

= –40°C

A

and Temperature

LO

(Baseband I/Q Amplitude = 1.4 V p-p Differential)

–5

–10

–15

10

SSB OUTPUT POWER (dBm)

06664-015

06664-016

5

OUTPUT THIRD-ORDER INTE RCEPT (dBm)

0

2300 3000

2400 2500 2600 2700 2800 2900

LO FREQUENCY (MHz)

Figure 18. OIP3 vs. f

80

70

TA = +25°C

60

50

40

30

20

10

OUTPUT SECO ND-ORDER INTERCEPT (dBm)

0

2300 3000

TA = +85°C

2400 2500 2600 2700 2800 2900

Figure 19. OIP2 vs. f

and Temperature

LO

TA = –40°C

LO FREQUENCY (MHz)

and Temperature

LO

06664-018

06664-019

20

CARRIER

–30

–40

SUPPRESSION (dBc)

–50

–60

–70

SECOND-ORDER DIS TORTIO N, CARRIER

FEEDTHROUG H, SIDEBAND SUPPRESSION

–80

1M 100M

FEEDTHROUG H (dBm)

SIDEBAND

SECOND-ORDER

DISTORTION (dBc)

BASEBAND FREQUENCY (Hz)

10M

Figure 17. Second-Order Distortion, Carrier Feedthrough, and Sideband

Suppression vs. f

(fLO = 2500 MHz)

BB

SECOND-ORDER DISTORTION, THIRD-ORDER

06664-017

Rev. A | Page 9 of 20

20

–30

–40

–50

SIDEBAND SUPPRESSION

–60

DISTORTI ON, CARRIER FEEDT HROUGH,

–70

–6 6

CARRIER

FEEDTHROUGH (dBm)

–5–4–3–2–1012345

SSB OUTPUT POWER (dBm)

THIRD-ORDER

DISTORTION (dBc)

SIDEBAND SUPPRESSION (dBc)

SECOND-ORDER

DISTORTION (dBc)

LO AMPLIT UDE (dBm)

5

4

3

2

1

0

Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. LO Amplitude (fLO = 2300 MHz)

OUT

SSB OUTPUT PO WER (dBm)

06664-020

ADL5373

–

20

SSB OUTPUT POWER (dBm)

–30

THIRD-ORDER

–40

–50

SIDEBAND SUPPRESSION

–60

DISTORTI ON, CARRIER FEEDT HROUGH,

SECOND-ORDER DISTORTION, THIRD-ORDER

–70

–6 6

DISTORTION (dBc)

–5–4–3–2–1012345

LO AMPLIT UDE (dBm)

CARRIER
FEEDTHROUGH (dBm)

SIDEBAND SUPPRESSIO N (dBc)

SECOND-ORDER

DISTORTION (dBc)

Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

0.20

0.19

VS = 5.25V

0.18

VS = 5.0V

0.17

VS = 4.75V

0.16

0.15

0.14

0.13

SUPPLY CURRENT (A)

0.12

0.11

0.10
–40 85

vs. LO Amplitude (fLO = 2700 MHz)

OUT

25

TEMPERATURE ( °C)

Figure 22. Power Supply Current vs. Temperature

25

8

20

7

15

6

QUANTITY

10

5

SSB OUTPUT PO WER (dBm)

4

3

06664-021

5

0

–158.1

–157.9

–157.7

–157.5

–157.3

–157.1

NOISE AT 20M Hz OFFS ET (dBm/Hz )

–156.9

Figure 23. 20 MHz Offset Noise Floor Distribution at f

f

= 2500MHz

LO

–156.7

–156.5

–156.3

–156.1

–155.9

–155.7

06664-023

= 2500 MHz

LO

(I/Q Amplitude = 0 mV p-p with 500 mV dc Bias)

06664-022

Rev. A | Page 10 of 20

ADL5373

THEORY OF OPERATION

CIRCUIT DESCRIPTION

Overview

The ADL5373 can be divided into five circuit blocks: the LO
interface, the baseband voltage-to-current (V-to-I) converter,
the mixers, the differential-to-single-ended (D-to-S) stage, and
the bias circuit. A detailed block diagram of the device is shown
in

Figure 24.

LOIP

LOIN

IBBP

IBBN

QBBP

QBBN

The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I and Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the output balun, which provides a single-ended output.
The bias cell generates reference currents for the V-to-I stage.

LO Interface

The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. For optimal performance, the LO should be
driven differentially. Each quadrature LO signal then passes
through a limiting amplifier that provides the mixer with a
limited drive signal.

PHASE

SPLITTER

Σ

Figure 24. Block Diagram

VOUT

6664-024

V-to-I Converter

The differential baseband inputs (QBBP, QBBN, IBBN, and
IBBP) consist of the bases of the PNP transistors, which present
a high impedance. The voltages applied to these pins drive the
V-to-I stage that converts baseband voltages into currents. The
differential output currents of the V-to-I stages feed each of
their respective Gilbert cell mixers. The dc common-mode
voltage at the baseband inputs sets the currents in the two mixer
cores. Varying the baseband common-mode voltage influences the
current in the mixer and affects overall modulator performance.
The recommended dc voltage for the baseband common-mode
voltage is 500 mV dc.

Mixers

The ADL5373 has two double balanced mixers: one for the
in-phase channel (I-channel) and one for the quadrature channel
(Q-channel). Both mixers are based on the Gilbert cell design of
four cross-connected transistors. The output currents from the
two mixers sum together into a load. The signal developed across
this load is used to drive the D-to-S stage.

D-to-S Stage

The output D-to-S stage consists of an on-chip balun that
converts the differential signal to a single-ended signal. The
balun presents high impedance to the output (VOUT); therefore, a
matching network may be needed at the output for optimal
power transfer.

Bias Circuit

An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage.

Rev. A | Page 11 of 20

ADL5373

BASIC CONNECTIONS

Figure 25 shows the basic connections for the ADL5373.

QBBP QBBN IBBN IBBP

C16

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

1

2

3

4

5

6

GND

RLOP
OPEN

CLOP

100pF

QBBP

COM4

QBBN

2423222120

Z1

F-MOD

EXPOSED PADDLE

789

LOIP

LOIN

COM2

CLON
100pF

34

2

5

NC

6

1

T1

JOHANSON

TECHNOLOG Y
2450BL15B050

COM4

IBBN

101112

COM2

COM3

RLON
OPEN

LO

IBBP

COM3

19

VPS5

18

VPS4

17

VPS3

16

VPS2

15

VPS2

14

VOUT

13

COUT
100pF

C13

0.1µF

0.1µF

C15

0.1µF

C14

0.1µF

C11

OPEN

VPOS

VOUT

Figure 25. Basic Connections for the ADL5373

POWER SUPPLY AND GROUNDING

All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. Locate these capacitors as close as possible
to the device. The power supply can range between 4.75 V and

5.25 V.

06664-025

The COM1, COM2, COM3, and COM4 pins should be tied to
the same ground plane through low impedance paths. Solder the
exposed paddle on the underside of the package to a low
thermal and electrical impedance ground plane. If the ground
plane spans multiple layers on the circuit board, they should be
stitched together with nine vias under the exposed paddle.
Application Note AN-772 describes the thermal and electrical
grounding of the LFCSP in detail.

BASEBAND INPUTS

The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. Bias the nominal drive level of

1.4 V p-p differential (700 mV p-p on each pin) to a common­mode level of 500 mV dc.

The dc common-mode bias level for the baseband inputs can
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5373 input range and on the top end by the output compliance
range on most DACs from Analog Devices.

LO INPUT

The LO input should be driven differentially. The recommended
balun for the ADL5373 is the Johanson Technology model
2450BL15B050. The LO pins should be ac-coupled to the balun.

The nominal LO drive of 0 dBm can be increased to up to 6 dBm
to realize an improvement in the noise performance of the
modulator. If the LO source cannot provide the 0 dBm level,
operation at a reduced power below 0 dBm is acceptable.
Reduced LO drive results in slightly increased modulator noise.
The effect of LO power on sideband suppression and carrier
feedthrough is shown in

Figure 20 and Figure 21.

RF OUTPUT

The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.

Figure 8 for S22

Rev. A | Page 12 of 20

ADL5373

–

–

OPTIMIZATION

The carrier feedthrough and sideband suppression performance
of the ADL5373 can be improved by using optimization
techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator, the quantities (V
are equal to zero, which results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5373 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (V
and (V

QOPP

− V

) offsets. The I-channel offset is held constant

QOPN

while the Q-channel offset is varied until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant, while the offset on the
I-channel is adjusted until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 26 shows the relationship of carrier feedthrough vs. dc
offset as null.

60

–64

–68

–72

–76

–80

CARRIER FEEDTHRO UGH (dBm)

–84

–88

–300 –240 –180 –120 –60 0 60 120 180 240 300

Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 2500 MHz

Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied,

= V

V

IOPP

V

IOPP

When an offset of +V

V

IOPP

V

IOPN

V

IOPP

= 500 mV, or

IOPN

− V

= V

IOPN

IOS

IOS

= 500 mV + V

= 500 mV − V

− V

= V

IOPN

IOS

The same applies to the Q channel.

− V

IOPP

VP – VN OFFSET (µV)

IOPN

) and (V

QOPP

IOPP

− V

− V

= 0 V

is applied to the I-channel inputs,

/2, and

IOS

/2, such that

IOS

QOPN

IOPN

)

)

06664-026

It is often desirable to perform a one-time carrier null calibra­tion. This is usually performed at a single frequency.

Figure 27
shows how carrier feedthrough varies with LO frequency over a
range of ±100 MHz on either side of a null at 2600 MHz.

30

–40

–50

–60

–70

CARRIER FEEDTHROUGH (dBm)

–80

–90

2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

LO FREQUENCY (MHz)

06664-041

Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 2600 MHz

Sideband Suppression Optimization

Sideband suppression results from relative gain and relative
phase offsets between the I channel and Q channel and can
be suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by
the gain and phase imbalances.

0

–10

2.5dB

–20

1.25dB

0.5dB

–30

0.25dB

–40

0.125dB

0.05dB

–50

0.025dB

–60

0.0125dB

–70

SIDEBAND SUPPRESSI ON (dBc)

0dB

–80

–90

0.01 0.1 1 10 100

PHASE ERROR (Deg rees)

06664-028

Figure 28. Sideband Suppression vs. Quadrature Phase Error for

Various Quadrature Amplitude Offsets

Figure 28 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.

The sideband suppression nulling can be performed either
through adjusting the gain for each channel or through the
modification of the phase and gain of the digital data coming
from the digital signal processor.

Rev. A | Page 13 of 20

ADL5373

APPLICATIONS INFORMATION

DAC MODULATOR INTERFACING

The ADL5373 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 mA to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.

Driving the ADL5373 with a TxDAC®

An example of the interface using the AD9779 TxDAC is shown

Figure 29. The baseband inputs of the ADL5373 require a dc

in
bias of 500 mV. The average output current on each of the outputs
of the

AD9779 is 10 mA. Therefore, a single 50 Ω resistor to
ground from each of the DAC outputs results in an average current
of 10 mA flowing through each of the resistors, thus producing
the desired 500 mV dc bias for the inputs to the ADL5373.

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

Figure 29. Interface Between the

Ground to Establish the 500 mV DC Bias for the ADL5373 Baseband Inputs

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

19

IBBP

20

IBBN

23

QBBN

24

QBBP

06664-029

AD9779 and ADL5373 with 50 Ω Resistors to

The AD9779 output currents have a swing that ranges from
0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage
swing going into the ADL5373 baseband inputs ranges from
0 V to 1 V. A full-scale sine wave out of the

AD9779 can be
described as a 1 V p-p single-ended (or 2 V p-p differential)
sine wave with a 500 mV dc bias.

LIMITING THE AC SWING

There are situations in which it is desirable to reduce the ac
voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the interface.
This resistor is placed in the shunt between each side of the
differential pair, as shown in
reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.

Figure 30. It has the effect of

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

Figure 30. AC Voltage Swing Reduction Through the Introduction

of a Shunt Resistor Between a Differential Pair

The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing.

Figure 31 shows the
relationship between the swing limiting resistor and the peak­to-peak ac swing that it produces when 50 Ω bias setting
resistors are used.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

DIFFERENTIAL SWING (V p-p)

0.4

0.2

0

10 100 1000 10000

RL (Ω)

06664-031

Figure 31. Relationship Between the AC Swing Limiting Resistor and the

Peak-to-Peak Voltage Swing with 50 Ω Bias Setting Resistors

FILTERING

It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing that was described in the
AC Swing

section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting resistors
and the ac swing limiting resistor, which establishes the input
and output impedances for the filter.

Limiting the

06664-030

Rev. A | Page 14 of 20

ADL5373

–

–

An example is shown in Figure 32 with a third-order, Bessel
low-pass filter with a 3 dB frequency of 10 MHz. Matching input
and output impedances makes the filter design easier, so the
shunt resistor chosen is 100 Ω, producing an ac swing of
1 V p-p differential. The frequency response of this filter is
shown in

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

Figure 33.

LPI

C1I

C1Q

771.1nH

350.1pF
C2I

LNI

771.1nH

LNQ

771.1nH

350.1pF

C2Q

LPQ

771.1nH

93

RBIP

50Ω

53.62nF

RBIN

50Ω

92

84

RBQN

50Ω

53.62nF

RBQP

50Ω

83

Figure 32. DAC Modulator Interface with

10 MHz Third-Order Bessel Filter

RSLI
100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

0

–10

–20

GROUP DELAY

–30

MAGNITUDE (dB)

–40

–50

–60

1 10 100

FREQUENCY (MHz)

MAGNITUDE

Figure 33. Frequency Response for DAC Modulator Interface

with 10 MHz Third-Order Bessel Filter

36

30

24

18

12

GROUP DELAY (ns)

6

0

06664-033

USING THE AD9779 AUXILIARY DAC FOR CARRIER FEEDTHROUGH NULLING

The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator.
to use the auxiliary DACs, which adds four resistors to the
interface.

Figure 34 shows the interface required

AUX1_P

AD9779 F-MOD

OUT1_P

OUT1_N

AUX1_N

AUX2_N

OUT2_N

OUT2_P

AUX2_P

06664-032

WiMAX OPERATION

Figure 35 shows the first and second adjacent channel power
ratios (10 MHz offset and 20 MHz offset), and the 30 MHz
offset noise floor vs. output power for a 10 MHz 1024-OFDMA
waveform at 2600 MHz.

ADJACENT AND ALTERNATE

CHANNEL POWER RAT IOS (d B)

Figure 35. Adjacent and Alternate Channel Power Ratios and 30 MHz Offset

Noise Floor vs. Channel Power for a 10 MHz 1024-OFDMA Waveform at

Figure 35 illustrates that optimal performance is achieved when
the output power from the modulator is −10 dBm or greater.
The noise floor rises with increasing output power, but at less
than half the rate at which ACPR degrades. Therefore, operating
at powers greater than −10 dBm can improve the signal-to­noise ratio.

90

500Ω

93

92

500Ω

500Ω

89

500Ω

87

84

RBQN

RBQP

83

86

RBIP

50Ω

RBIN

50Ω

50Ω

50Ω

250Ω

53.62nF
C1I

250Ω

250Ω

53.62nF
C1Q

250Ω

LPI

771.1nH

350.1pF

LNI

771.1nH

LNQ

771.1nH

350.1pF
C2Q

LPQ

771.1nH

C2I

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

Figure 34. DAC Modulator Interface with Auxiliary DAC Resistors

62

–64

–66

–68

–70

–72

–74

–76

–78

ADJACENT CHANNEL

POWER RATIO

30MHz OFF SET

NOISE FLOOR

ALTERNATE CHANNEL

POWER RATI O

–18 –16 –14 –12 –10 –8 –6 –4 –2

OUTPUT PO WER (dBm)

2600 MHz; LO Power = 0 dBm

151

–152

–153

–154

–155

–156

–157

–158

–159

06664-034

30MHz OFFSET NOISE FLOOR (dBm/Hz)

06664-035

Rev. A | Page 15 of 20

ADL5373

Figure 36 shows the error-vector magnitude (EVM) vs. output
power for a 10 MHz, 1024-OFDMA waveform at 2600 MHz.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

ERROR VECTOR MAGNITUDE (%)

0.2

0

–19 –17 –15 –13 –11 –9 –7 –5 –3

OUTPUT PO WER (dBm)

Figure 36. Error Vector Magnitude (EVM) vs. Output Power for 10 MHz,

1024-OFDMA Waveform at 2600 MHz; LO Power = 0 dBm

6664-036

LO GENERATION USING PLLs

Analog Devices has a line of PLLs that can be used for generating
the LO signal.
frequency and phase noise performance.

Table 4 lists the PLLs together with their maximum

TRANSMIT DAC OPTIONS

The AD9779 recommended in the previous sections of this data
sheet is not the only DAC that can be used to drive the ADL5373.
There are other appropriate DACs, depending on the level of
performance required.
Analog Devices.

Table 6. Dual TxDAC Selection Table

Part Resolution (Bits) Update Rate (MSPS Minimum)

AD9709 8 125
AD9761 10 40
AD9763 10 125
AD9765 12 125
AD9767 14 125
AD9773 12 160
AD9775 14 160
AD9777 16 160
AD9776 12 1000
AD9778 14 1000
AD9779 16 1000

All DACs listed have nominal bias levels of 0.5 V and use the
same simple DAC modulator interface that is shown in

Table 6 lists the dual TxDACs offered by

Figure 32.

Table 4. Analog Devices PLL Selection Table

Part

Frequency

(MHz)

f

IN

Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)

ADF4110 550 −91 @ 540 MHz
ADF4111 1200 −87 @ 900 MHz
ADF4112 3000 −90 @ 900 MHz
ADF4113 4000 −91 @ 900 MHz
ADF4116 550 −89 @ 540 MHz
ADF4117 1200 −87 @ 900 MHz
ADF4118 3000 −90 @ 900 MHz

The ADF4360 comes as a family of chips, with nine operating
frequency ranges. A device is chosen depending on the local
oscillator frequency required. Although the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5373, it can be a cheaper alternative
to a separate PLL and VCO solution.

Tabl e 5 shows the options

available.

Table 5.

ADF4360 Family Operating Frequencies

Part Output Frequency Range (MHz)

ADF4360-0 2400 to 2725
ADF4360-1 2050 to 2450
ADF4360-2 1850 to 2150
ADF4360-3 1600 to 1950
ADF4360-4 1450 to 1750
ADF4360-5 1200 to 1400
ADF4360-6 1050 to 1250
ADF4360-7 350 to 1800
ADF4360-8 65 to 400

MODULATOR/DEMODULATOR OPTIONS

Tabl e 7 lists other Analog Devices modulators and demodulators.

Table 7. Modulator/Demodulator Options

Modulator/

Part No.

Demodulator

AD8345 Modulator 140 to 1000
AD8346 Modulator 800 to 2500
AD8349 Modulator 700 to 2700
ADL5390 Modulator 20 to 2400

ADL5385 Modulator 50 to 2200
ADL5370 Modulator 300 to 1000
ADL5371 Modulator 500 to 1500
ADL5372 Modulator 1500 to 2500
ADL5374 Modulator 3000 to 4000
AD8347 Demodulator 800 to 2700
AD8348 Demodulator 50 to 1000
AD8340 Vector modulator 700 to 1000
AD8341 Vector modulator 1500 to 2400

Frequency
Range (MHz)

Comments

External
quadrature

Rev. A | Page 16 of 20

ADL5373

EVALUATION BOARD

A populated RoHS-compliant evaluation board is available for
evaluation of the ADL5373. The ADL5373 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the

Power Supply and Grounding
section). The evaluation board has no components on the
underside so heat can be applied to the underside for easy
removal and replacement of the ADL5373.

QBBP QBBN IBBN IBBP

RFNQ

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

RFPQ

CFPQ
OPEN

0Ω

RTQ

OPEN

1

2

3

4

5

6

CFNQ

0Ω

OPEN

QBBP

COM4

QBBN

2423222120

F-MOD

EXPOSED PADDLE

789

OPEN

Z1

CFNI

COM4

IBBN

101112

RFNI0ΩRFPI

0Ω

RTI

CFPI

OPEN

OPEN

IBBP

19

18

17

16

15

14

13

VPS5

VPS4

VPS3

VPS2

VPS2

VOUT

COUT
100pF

C13

0.1µF

C16

0.1µF

C15

0.1µF

C14

0.1µF

L12

0Ω

L11

0Ω

C11

OPEN

VOUT

VPOS

Figure 38. Evaluation Board Layout, Top Layer

Yup in g Toh

06664-038

LOIP

LOIN

GND

RLOP
OPEN

CLOP
100pF

COM2

NC

JOHANSON
TECHNOLOGY
2450BL15B050

COM2

COM3

COM3

CLON
100pF

RLON
OPEN

34

2

5

6

1

LO

T1

6664-037

Figure 37. ADL5373 Evaluation Board Schematic

Table 8. Evaluation Board Configuration Options

Component Description Default Condition

VPOS, GND Power Supply and Ground Clip Leads. Not applicable
RFPI, RFNI, RFPQ, RFNQ, CFPI,

CFNI, CFPQ, CFNQ, RTQ, RTI

Baseband Input Filters. These components can be used to
implement a low-pass filter for the baseband signals. See
the Filtering section.

RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = open (0402)
RTQ, RTI = open (0402)

Rev. A | Page 17 of 20

ADL5373

CHARACTERIZATION SETUP

AEROFLEX IFR 3416

250kHz TO 6GHz SIGNAL G ENERATOR

FREQ 4MHz LEVEL 0dBm

BIAS 0.5V
BIAS 0.5V

AGILENT 34401A

VPOS +5V

AGILENT E3631A
POWER SUPPLY

5.000 0.175A

6V

+

MULTIMETER

0.175 ADC

±25V

–

+

COM

GAIN 0.7V
GAIN 0.7V

CONNECT TO BACK OF UNIT

I/AM Q/F M

I OUT Q OUT

90°

–

IQ

Figure 39. Characterization Bench Setup

The primary setup used to characterize the ADL5373 is shown

Figure 39. This setup was used to evaluate the product as a

in
single-sideband modulator. The Aeroflex signal generator supplied
the LO and differential I and Q baseband signals to the device
under test, DUT. The typical LO drive was 0 dBm. The I-channel is
driven by a sine wave, and the Q-channel is driven by a cosine
wave. The lower sideband is the single-sideband (SSB) output.

RF

OUT

0°

F-MOD

IP

IN

QP

QN

The majority of characterization for the ADL5373 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the V
offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT.

R AND S SPECTRUM ANALYZER

FSU 20Hz TO 8GHz

LO

+6dBm

F-MOD TEST SETUP

LO

OUTPUT

OUT

GNDVPOS

RF

IN

6664-039

IOS

and V

QOS

Rev. A | Page 18 of 20

ADL5373

TEKTRONI X AFG3252

DUAL FUNCTIO N

ARBITRARY FUNCTI ON GENERATOR

R AND S SMT 06

1MHz

CH1

AMP L 700 mV p- p
PHASE 0°

1MHz

CH2

AMP L 700 mV p- p
PHASE 90°

AGILENT E3631A

POWER SUPPLY

5.000 0.350A

6V

–

VPOS +5V

+

VPOS +5V

AGILENT E3631A

POWER SUPPLY

FREQ 4MHz TO 4GHz

CH1 OUTP UT

CH2 OUTP UT

0°

±25V

–

+

COM

–5V

+5V

90°

IQ

SINGLE-T O-DIFF ERENTIAL

CIRCUIT BOARD

F-MOD TES T RACK

Q IN AC

Q IN DCCM

TSEN GND

VPOSB VPOSA

IN1

AGND

VN1 VP1

I IN DCCM

I IN AC

IN1

SIGNAL GE NERATOR

LEVEL 0dBm

IP

IN

QP

QN

F-MOD

CHAR BD

IP

LO

IN

QP

OUT

QN

GND

VPOS

R AND S FSEA 30

SPECTRUM ANALYZER

RF

OUT

LO

OUTPUT

0.500 0.010A

6V ±25V

–

+

VCM = 0.5V

AGILENT 34401A

MULTIMETER

0.200 ADC

–

+

COM

Figure 40. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling

The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5373 is shown in

Figure 40.
The interface board has circuitry that converts the single-ended
I input and Q input from the arbitrary function generator to
differential I and Q baseband signals with a dc bias of 500 mV.

RF

IN

100MHz TO 4GHz

+6dBm

06664-040

Undesired sideband nulling was achieved through an iterative
process of adjusting amplitude and phase on the Q-channel. See
the

Sideband Suppression Optimization section for detailed

information on sideband nulling.

Rev. A | Page 19 of 20

ADL5373

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADL5373ACPZ-R7
ADL5373ACPZ-WP
ADL5373-EVALZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 1,500

1

−40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64

1

Evaluation Board

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06664-0-2/08(A)

T

Rev. A | Page 20 of 20

TTT