Datasheet ADL5372 Datasheet (ANALOG DEVICES)

1500 MHz to 2500 MHz

FEATURES

Output frequency range: 1500 MHz to 2500 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 14 dBm @ 1900 MHz
Noise floor: −158 dBm/Hz
Sideband suppression: −45 dBc @ 1900 MHz
Carrier feedthrough: −45 dBm @ 1900 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP_VQ

APPLICATIONS

Cellular communication systems

CDMA2000/GSM/WCDMA
WiMAX/broadband wireless access systems
Satellite modems

GENERAL DESCRIPTION

The ADL5372 is a member of the fixed-gain quadrature modulator
(F-MOD) family designed for use from 1500 MHz to 2500 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.

The ADL5372 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low
IF-to-RF applications and in broadband digital predistortion
transmitters.

Quadrature Modulator

ADL5372

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

LOIP

LOIN

QBBN

QBBP

The ADL5372 accepts two differential baseband inputs and a
single-ended, local oscillator (LO) and generates a single­ended output.

The ADL5372 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in
a 24-lead, exposed-paddle, Pb-free, LFCSP. Performance is
specified over a −40°C to +85°C temperature range. A Pb-free
evaluation board is available.

QUADRATURE

PHASE

SPLITTER

Figure 1.

VOUT

06511-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADL5372

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

Circuit Description..................................................................... 11

Basic Connections ..........................................................................12

Optimization............................................................................... 13

Applications Information .............................................................. 14

DAC Modulator Interfacing ..................................................... 14

Limiting the AC Swing .............................................................. 14

Filtering........................................................................................ 14

Using the AD9779 Auxiliary DAC for Carrier Feedthrough

Nulling ......................................................................................... 15

GSM Operation .......................................................................... 15

WCDMA Operation.................................................................. 16

WiMAX Operation .................................................................... 16

LO Generation Using PLLs....................................................... 16

Transmit DAC Options ............................................................. 17

Modulator/Demodulator Options ........................................... 17

Evaluation Board............................................................................ 18

Characterization Setup .................................................................. 19

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

12/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5372

SPECIFICATIONS

VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f

Table 1.

Parameter Conditions Min Typ Max Unit

OPERATING FREQUENCY RANGE Low frequency 1500 MHz

High frequency 2500 MHz

LO = 1900 MHz

Output Power VIQ = 1.4 V p-p differential 7.1 dBm
Output P1dB 14.2 dBm
Carrier Feedthrough −45 dBm
Sideband Suppression −45 dBc
Quadrature Error 0.21 Degrees
I/Q Amplitude Balance 0.09 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor

GSM 6 MHz carrier offset, P
WCDMA

LO = 2150 MHz

Output Power VIQ = 1.4 V p-p differential 7.2 dBm
OutputP1dB 14 dBm
Carrier Feedthrough −41 dBm
Sideband Suppression −44 dBc
Quadrature Error 0.27 Degrees
I/Q Amplitude Balance 0.12 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor

WCDMA

LO = 2400 MHz

Output Power VIQ = 1.4 V p-p differential 5.6 dBm
OutputP1dB 12.4 dBm
Carrier Feedthrough −36 dBm
Sideband Suppression −40 dBc
Quadrature Error 0.6 Degrees
I/Q Amplitude Balance 0.13 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor

WiMAX

) = 1 MHz, unless otherwise noted.

BB

− (fLO + (2 × fBB)), P

OUT

− (fLO + (3 × fBB)), P

OUT

= 6.2 dBm −50 dBc

OUT

= 6.2 dBm −47 dBc

OUT

= 1 dBm per tone 54 dBm

OUT

= 1 dBm per tone 27 dBm

OUT

I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 1960 MHz

= 5 dBm, PLO = 6 dBm; LO = 1960 MHz −158 dBc/Hz

OUT

Single carrier, 20 MHz carrier offset, P
P

= 0 dBm; LO = 1966 MHz

LO

− (fLO + (2 × fBB)), P

OUT

− (fLO + (3 × fBB)), P

OUT

= 6.2 dBm −59 dBc

OUT

= 6.2 dBm −48 dBc

OUT

OUT

OUT

= −10 dBm,

OUT

= 1 dBm per tone 65 dBm
= 1 dBm per tone 26.5 dBm

I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset

Single carrier, 20 MHz carrier offset, P

= −10 dBm, PLO = 0 dBm;

OUT

LO = 2140 MHz

− (fLO + (2 × fBB)), P

OUT

− (fLO + (3 × fBB)), P

OUT

= 6.2 dBm −54 dBc

OUT

= 6.2 dBm −48 dBc

OUT

= 1 dBm per tone 57 dBm

OUT

= 1 dBm per tone 24.5 dBm

OUT

I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 2350 MHz

10 MHz carrier bandwidth (256 subcarriers), 64 QAM signal,
70 MHz carrier offset, P

= −10 dBm, PLO = 0 dBm; LO = 2350 MHz

OUT

−158 dBm/Hz

−157.6 dBm/Hz

−158 dBm/Hz

−157.5 dBm/Hz

−158.5 dBm/Hz

−158 dBm/Hz

Rev. 0 | Page 3 of 24

ADL5372

Parameter Conditions Min Typ Max Unit

LO INPUTS

LO Drive Level
Input Return Loss See Figure 9 for a plot of return loss vs. frequency −12 dB

BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN

I and Q Input Bias Level 500 mV
Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc2 45 μA
Input Offset Current 0.1 μA
Differential Input Impedance 2900 kΩ
Bandwidth (0.1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 70 MHz
Bandwidth (1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 350 MHz

POWER SUPPLIES Pin VPS1 and Pin VPS2

Voltage 4.75 5.25 V
Supply Current 165 mA

1

High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.

2

See V-to-I Converter section for architecture information.

1

Characterization performed at typical level −6 0 +6 dBm

Rev. 0 | Page 4 of 24

ADL5372

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V to 2 V
LOIP and LOIN 13 dBm
Internal Power Dissipation 1100 mW
θJA (Exposed Paddle Soldered Down) 54°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5372

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QBBP

COM4

QBBN

COM4

IBBN

IBBP

2422232120

19

COM1
COM1

VPS1
VPS1
VPS1
VPS1

1
2
3
4
5
6

F-MOD

TOP VIEW

(Not to Scale)

798

101112

LOIP

LOIN

COM2

COM2

COM3

VPS5

18

VPS4

17

VPS3

16

VPS2

15

VPS2

14

VOUT

13

COM3

06511-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 7, 10 to 12,

COM1 to COM4 Input Common Pins. Connect to ground plane via a low impedance path.

21, 22
3 to 6, 14 to 18 VPS1 to VPS5

Positive Supply Voltage Pins. All pins should be connected to the same supply (V
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 25).

8, 9 LOIP, LOIN

50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
AC-couple LOIN to ground and drive LO through LOIP.

13 VOUT

Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output
is ground referenced.

19, 20, 23, 24 IBBP, IBBN, QBBN, QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs
must be dc-biased to 500 mV dc and must be driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential
drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be
externally biased.

Exposed Paddle Connect to ground plane via a low impedance path.

). To ensure

S

Rev. 0 | Page 6 of 24

ADL5372

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f

9

8

7

6

5

4

3

SSB OUTPUT P OWER (d Bm)

2

1

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

9

8

7

6

5

4

3

SSB OUTPUT POWER (d Bm)

2

1

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

TA = –40°C

TA = +85°C

LO FREQUENCY (MHz)

Figure 3. Single Sideband (SSB) Output Power (P

LO Frequency (f

VS = 5V

VS = 5.25V

LO FREQUENCY (MHz)

Figure 4. Single Sideband (SSB) Output Power (P

LO Frequency (f

5

) = 1 MHz, unless otherwise noted.

BB

TA = +25°C

) vs.

) and Temperature

LO

) and Supply

LO

OUT

VS = 4.75V

) vs.

OUT

16

TA = –40°C

14

12

10

TA = +85°C

8

6

OUTPUT P1dB (dBm)

4

2

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

06511-003

Figure 6. SSB Output P1dB Compression Point (OP1dB) vs. f

16

14

12

10

8

6

OUTPUT P1d B (dBm)

4

2

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

06511-004

Figure 7. SSB Output P1dB Compression Point (OP1dB) vs. f

150

VS = 5V

120

S11 OF LOIP
S22 OF OUTPUT

TA = +25°C

LO FREQUENCY (MHz)

VS = 5.25V

LO FREQUENCY (MHz)

90

1500MHz

and Temperature

LO

VS = 4.75V

and Supply

LO

60

30

06511-006

06511-007

0

OUTPUT PO WER VARIANCE (d B)

–5

1 10 100 1000

BASEBAND FREQUENCY (M Hz)

Figure 5. I and Q Input Bandwidth Normalized to

Gain @ 1 MHz (f

= 1900 MHz)

LO

06511-005

Rev. 0 | Page 7 of 24

2500MHz

210

240

1500MHz

270

2500MHz

300

Figure 8. Smith Chart of LOIP S11 and VOUT S22

(f

from 1600 MHz to 2500 MHz)

LO

330

0180

06511-043

ADL5372

–

0

0

–5

–10

–15

RETURN LOSS ( dB)

–20

–25

1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

LO FREQ UENCY (MHz)

Figure 9. Return Loss (S11) of LOIP

0

–10

–20

TA = –40°C

–30

–40

–50

–60

CARRIER FEEDTHRO UGH (dBm)

–70

–80

1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

Figure 10. Carrier Feedthrough vs. f

TA = +25°C

TA = +85°C

LO FREQUENCY (MHz)

and Temperature

LO

Multiple Devices Shown

–10

–20

–30

–40

SIDEBAND SUPPRESSI ON (dBc)

–50

–60

1500 1600 1700 1800 1900 2000 2100 2200 2300 24 00 2500

6511-009

TA = +25°C

Figure 12. Sideband Suppression vs. f

TA = –40°C

LO FREQUENCY (MHz)

LO

TA = +85°C

and Temperature

06511-012

Multiple Devices Shown

0

–10

–20

–30

–40

–50

–60

–70

SIDEBAND SUPPRESSION (dBc)

–80

–90

1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

06511-010

Figure 13. Sideband Suppression vs. f

TA = +85°C

TA = –40°C

LO FREQUENCY (MHz)

TA = +25°C

and Temperature after Nulling at 25°C

LO

06511-041

Multiple Devices Shown

0

–10

–20

–30

–40

–50

–60

–70

CARRIER FEEDTHROUG H (dBm)

–80

–90

1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

Figure 11. Carrier Feedthrough vs. f

TA = +85°C

LO FREQUENCY (MHz)

and Temperature after Nulling at 25°C

LO

TA = +25°C

Multiple Devices Shown

TA = –40°C

6511-040

20

–30

–40

–50

–60

SIDEBAND SUPPRESSI ON

–70

DISTORT ION, CARRIER F EEDTHROUG H,

SECOND-ORDER DI STORTI ON, THI RD-ORDER

–80

CARRIER

FEEDTHROUGH (dBm)

THIRD ORDER (d Bc)

0.20.61.01.41.82.22.63.03.4

SSB OUTPUT POWER (d Bm)

SIDEBAND SUPPRESSION (dBc)

SECOND ORDER (d Bc)

BASEBAND INPUT VO LTAGE (V p–p)

Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. Baseband Differential Input Level

OUT

(f

= 1900 MHz)

LO

15

10

5

0

–5

–10

–15

SSB OUTPUT POWER (dBm)

06511-014

Rev. 0 | Page 8 of 24

ADL5372

–

–

R

–

–

20

–30

–40

CARRIER

FEEDTHROUGH (dBm)

SSB OUTPUT POWER (d Bm)

15

10

5

30

25

20

TA = –40°C

TA = +25°C

TA = +85°C

–50

–60

SIDEBAND SUPPRESSION

–70

DISTORT ION, CARRIE R FEEDTHROUGH,

SECOND-ORDER DI STORT ION, THIRD-ORDER

–80

0.20.61.01.41.82.22.63.03.4

THIRD ORDER (d Bc)

BASEBAND INPUT VO LTAGE (V p-p)

SIDEBAND SUPPRESSION (dBc)

SECOND ORDER (d Bc)

Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

20

–30

THIRD ORDER

T

–40

–50

–60

DISTORT ION (dBc)

–70

SECOND-ORDER AND T HIRD-ORDE

–80

1500 2500

= +85°C

A

SECOND ORDER

T

= +85°C

A

SECOND ORDER

1600 1700 1800 1900 2000 2100 2200 2300 2400

Figure 16. Second- and Third-Order Distortion vs. f

vs. Baseband Differential Input Level

OUT

= 2150 MHz)

(f

LO

THIRD ORDER

T

= +25°C

A

THIRD ORDER

T

= –40°C

A

T

= –40°C

A

LO FREQUENCY (MHz)

SECOND ORDER

T

= +25°C

A

and Temperature

LO

(Baseband I/Q Amplitude = 1.4 V p-p Differential)

20

–25

–30

–35

–40

THIRD ORDER (d Bc)

–45

SSB OUTPUT P OWER (d Bm)

SIDEBAND SUPPRESSION (dBc)

0

–5

–10

–15

8

7.5

7

6.5

6

5.5

15

10

SSB OUTPUT PO WER (dBm)

06511-015

5

OUTPUT THIRD-ORDER INT ERCEPT (dBm)

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

LO FREQUENCY (MHz)

06511-018

Figure 18. OIP3 vs. Frequency and Temperature

80

70

60

50

40

TA = –40°C

30

20

10

OUTPUT SECO ND-ORDER INTERCEPT (dBm)

0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500

06511-016

TA = +25°C

LO FREQUENCY (MHz)

TA = +85°C

6511-019

Figure 19. OIP2 vs. Frequency and Temperature

20

–30

FEEDTHROUG H (dBm)

–40

–50

SSB OUTPUT POWER (d Bm)

CARRIER

SIDEBAND SUPPRESSION (dBc)

THIRD ORDER (d Bc)

8

7

6

5

–50

SIDEBAND SUPPRESSI ON

CARRIER FEEDTHRO UGH (dBm)

–55

DISTORTION, CARRIER F EEDTHROUGH,

SECOND-ORDER DIST ORTIO N, THIRD-ORDER

–60

1M 10M 100M

BASEBAND FREQUENCY (Hz)

SECOND ORDER (dBc)

Figure 17. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. fBB and Temperature (fLO = 1900 MHz)

OUT

5

4.5

4

SSB OUTPUT POWER (dBm)

6511-017

SIDEBAND SUPPRESSION

–60

DISTORTION, CARRIER F EEDTHROUGH,

SECOND-ORDER DISTORTI ON, THIRD-ORDER

–70

SECOND ORDER (d Bc)

–6 –4 –2 0 2 4 6

LO AMPLITUDE (dBm)

4

SSB OUTPUT P OWER (d Bm)

3

06511-020

Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. LO Amplitude (fLO = 1900 MHz)

OUT

Rev. 0 | Page 9 of 24

ADL5372

–

20

SSB OUTP UT POW ER (dBm)

–30

–40

–50

SIDEBAND SUP PRESSI ON (dBc)

SIDEBAND SUPPRESSION

–60

DISTORTION, CARRIER FEEDTHROUGH,

SECOND-O RDER DISTORTIO N, THIRD-ORDER

–70

–6–4–20246

LO AMPLITUDE (dBm)

CARRIER

FEEDTHROUGH (dBm)

THIRD ORDER (dBc)

SECOND ORDER (dBc)

Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

0.20

0.19

0.18

0.17

0.16

0.15

0.14

0.13

SUPPLY CURRENT (A)

0.12

0.11

0.10
–40 –15 10 35 60 85

vs. LO Amplitude (fLO = 2150 MHz)

OUT

VS = 5.25V

VS = 5V

VS = 4.75V

TEMPERATURE (° C)

Figure 22. Power Supply Current vs. Temperature

22

8

7

6

5

4

SSB OUTPUT POWER (dBm)

3

06511-021

20

18

16

14

12

10

QUANTITY

8

6

4

2

0

–159.1

–158.7

–158.9

NOISE AT 20M Hz OFFS ET (dBm/Hz )

–158.3

–158.5

–158.1

Figure 23. 20 MHz Offset Noise Floor Distribution at f

f

= 1960MHz

LO

–157.9

–157.7

–157.5

–157.3

= 1960 MHz

LO

–157.1

06511-023

(I/Q Amplitude = 0 mV p-p with 500 mV dc Bias)

06511-042

Rev. 0 | Page 10 of 24

ADL5372

THEORY OF OPERATION

CIRCUIT DESCRIPTION

Overview

The ADL5372 can be divided into five circuit blocks: the LO
interface, the baseband voltage-to-current (V-to-I) converter,
the mixers, the differential-to-single-ended (D-to-S) stage, and
the bias circuit. A detailed block diagram of the device is shown
in

Figure 24.

LOIP

LOIN

IBBP

IBBN

QBBP

QBBN

The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I and Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the output balun, which provides a single-ended output.
The bias cell generates reference currents for the V-to-I stage.

LO Interface

The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. The LO can be driven either single-ended or
differentially. When driven single-ended, the LOIN pin should
be ac grounded via a capacitor. Each quadrature LO signal then
passes through a limiting amplifier that provides the mixer with
a limited drive signal.

PHASE

SPLITTER

Σ

Figure 24. Block Diagram

OUT

6511-024

V-to-I Converter

The differential baseband inputs (QBBP, QBBN, IBBN, and
IBBP) consist of the bases of PNP transistors, which present a
high impedance. The voltages applied to these pins drive the
V-to-I stage that converts baseband voltages into currents. The
differential output currents of the V-to-I stages feed each of their
respective Gilbert-cell mixers. The dc common-mode voltage at
the baseband inputs sets the currents in the two mixer cores.
Varying the baseband common-mode voltage influences the
current in the mixer and affects overall modulator performance.
The recommended dc voltage for the baseband common-mode
voltage is 500 mV dc.

Mixers

The ADL5372 has two double-balanced mixers: one for the
in-phase channel (I-channel) and one for the quadrature
channel (Q-channel). Both mixers are based on the Gilbert-cell
design of four cross-connected transistors. The output currents
from the two mixers sum together into a load. The signal
developed across this load is used to drive the D-to-S stage.

D-to-S Stage

The output D-to-S stage consists of an on-chip balun that
converts the differential signal to a single-ended signal. The
balun presents high impedance to the output (VOUT). Hence, a
matching network may be needed at the output for optimal
power transfer.

Bias Circuit

An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage.

Rev. 0 | Page 11 of 24

ADL5372

BASIC CONNECTIONS

Figure 25 shows the basic connections for the ADL5372.

QBBP QBBN IBBN IBBP

C16

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

1

2

3

4

5

6

GND

CLOP

100pF

QBBP

COM4

QBBN

COM4

2423222120

Z1

F-MOD

EXPOSED PADDLE

789

COM2

LO

LOIP

LOIN

101112

COM2

CLON
100pF

IBBN

COM3

COM3

IBBP

19

18

17

16

15

14

13

VPS5

VPS4

VPS3

VPS2

VPS2

VOUT

COUT
100pF

C13

0.1µF

0.1µF

C15

0.1µF

C14

0.1µF

C11

OPEN

VPOS

VOUT

Figure 25. Basic Connections for the ADL5372

Power Supply and Grounding

All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.

The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note

AN-772 discusses the

thermal and electrical grounding of the LFCSP in detail.

06511-025

Baseband Inputs

The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of

1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.

The dc common-mode bias level for the baseband inputs may
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5372 input range and on the top end by the output compliance
range on most DACs from Analog Devices.

LO Input

A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.

The nominal LO drive of 0 dBm can be increased to up to 6 dBm
to realize an improvement in the noise performance of the
modulator. This improvement is tempered by degradation in
the sideband suppression performance (see

Figure 20) and,
therefore, should be used judiciously. If the LO source cannot
provide the 0 dBm level, then operation at a reduced power
below 0 dBm is acceptable. Reduced LO drive results in slightly
increased modulator noise. The effect of LO power on sideband
suppression and carrier feedthrough is shown in
effect of LO power on GSM noise is shown in

Figure 20. The

Figure 35.

RF Output

The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see

Figure 8 for S22
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.

Rev. 0 | Page 12 of 24

ADL5372

–

–

OPTIMIZATION

The carrier feedthrough and sideband suppression performance
of the ADL5372 can be improved by using optimization
techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator, the quantities (V
are equal to zero, which results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero; and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5372 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (V
and (V

QOPP

− V

) offsets. The I-channel offset is held constant

QOPN

while the Q-channel offset is varied until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant, while the offset on the
I-channel is adjusted until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 26 shows the relationship of carrier feedthrough vs. dc
offset as null.

60

–64

–68

–72

–76

–80

CARRIER FEEDTHRO UGH (dBm)

–84

–88

–300 –240 –180 –120 –60 0 60 120 180 240 300

Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 1900 MHz

Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied

= V

V

IOPP

V

IOPP

When an offset of +V

V

IOPP

V

IOPN

V

IOPP

= 500 mV, or

IOPN

− V

= V

IOPN

IOS

IOS

= 500 mV + V

= 500 mV − V

− V

= V

IOPN

IOS

The same applies to the Q channel.

− V

IOPN

) and (V

IOPP

VP – VN OFFSET (µV)

QOPP

IOPP

− V

− V

= 0 V

is applied to the I-channel inputs

/2, and

IOS

/2, such that

IOS

QOPN

IOPN

)

)

06511-045

It is often desirable to perform a one-time carrier null calibra­tion. This is usually performed at a single frequency.

Figure 27
shows how carrier feedthrough varies with LO frequency over a
range of ±50 MHz on either side of a null at 1900 MHz.

30

–35

–40

–45

–50

–55

–60

–65

–70

CARRIER FEEDTHRO UGH (dBm)

–75

–80

1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950

LO FREQUENCY (MHz)

06511-022

Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 1900 MHz

Sideband Suppression Optimization

Sideband suppression results from relative gain and relative
phase offsets between the I-channel and Q-channel and can
be suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by
the gain and phase imbalances.

0

–10

2.5dB

–20

1.25dB

0.5dB

–30

0.25dB

–40

0.125dB

0.05dB

–50

0.025dB

–60

0.0125dB

–70

SIDEBAND SUPPRESSI ON (dBc)

0dB

–80

–90

0.01 0. 1 1 10 100

PHASE ERROR (Deg rees)

06511-028

Figure 28. Sideband Suppression vs. Quadrature Phase Error for

Various Quadrature Amplitude Offsets

Figure 28 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.

The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.

Rev. 0 | Page 13 of 24

ADL5372

APPLICATIONS INFORMATION

DAC MODULATOR INTERFACING

The ADL5372 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.

Driving the ADL5372 with a TxDAC®

An example of the interface using the AD9779 TxDAC is shown

Figure 29. The baseband inputs of the ADL5372 require a dc

in
bias of 500 mV. The average output current on each of the
outputs of the

AD9779 is 10 mA. Therefore, a single 50 Ω
resistor to ground from each of the DAC outputs results in an
average current of 10 mA flowing through each of the resistors,
thus producing the desired 500 mV dc bias for the inputs to the
ADL5372.

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

Figure 29. Interface Between the

Ground to Establish the 500 mV DC Bias for the ADL5372 Baseband Inputs

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

19

IBBP

20

IBBN

23

QBBN

24

QBBP

06511-029

AD9779 and ADL5372 with 50 Ω Resistors to

The AD9779 output currents have a swing that ranges from 0 to
20 mA. With the 50 Ω resistors in place, the ac voltage swing
going into the ADL5372 baseband inputs ranges from 0 V to 1 V.
A full-scale sine wave out of the

AD9779 can be described as a
1 V p-p single-ended (or 2 V p-p differential) sine wave with a
500 mV dc bias.

LIMITING THE AC SWING

There are situations in which it is desirable to reduce the ac
voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the interface.
This resistor is placed in the shunt between each side of the
differential pair, as shown in
reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.

Figure 30. It has the effect of

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

Figure 30. AC Voltage Swing Reduction Through the Introduction

of a Shunt Resistor Between Differential Pair

The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing.

Figure 31 shows the
relationship between the swing-limiting resistor and the peak­to-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

DIFFERENTIAL SWING (V p-p)

0.4

0.2

0

10 100 1000 10000

RL (Ω)

06511-031

Figure 31. Relationship Between the AC Swing-Limiting Resistor and the

Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors

FILTERING

It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing that was discussed in the
AC Swing

section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting
resistors and the ac swing-limiting resistor. Doing so establishes
the input and output impedances for the filter.

Limiting the

06511-030

Rev. 0 | Page 14 of 24

ADL5372

–

–

An example is shown in Figure 32 with a third-order, elliptical,
low-pass filter with a 3 dB frequency of 3 MHz. Matching input
and output impedances makes the filter design easier, so the
shunt resistor chosen is 100 Ω, producing an ac swing of
1 V p-p differential.

C1I

C1Q

LPI

2.7nH

1.1nF

LNI

2.7nH

LNQ

2.7nH

1.1nF

LPQ

2.7nH

C2I

C2Q

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

93

92

84

83

RBIP

50Ω

RBIN

50Ω

RBQN

50Ω

RBQP

50Ω

1.1nF

1.1nF

Figure 32. DAC Modulator Interface with

3 MHz Third-Order, Elliptical Low-Pass Filter

USING THE AD9779 AUXILIARY DAC FOR CARRIER FEEDTHROUGH NULLING

The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator.
to use the auxiliary DACs. This adds four resistors to the
interface.

AUX1_P

AD9779 F-MOD

OUT1_P

OUT1_N

AUX1_N

AUX2_N

OUT2_N

OUT2_P

AUX2_P

90

500Ω

93

92

89

500Ω

87

500Ω

84

83

86

500Ω

Figure 33. DAC Modulator Interface with Auxiliary DAC Resistors

Figure 33 shows the interface required

RBIP

50Ω

RBIN

50Ω

RBQN

50Ω

RBQP

50Ω

250Ω

1.1nF

250Ω

250Ω

1.1nF

250Ω

C1I

C1Q

LPI

2.7nH

1.1nF

LNI

2.7nH

LNQ

2.7nH

1.1nF

LPQ

2.7nH

C2I

C2Q

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

06511-032

06511-033

GSM OPERATION

Figure 34 shows the GSM EVM, spectral mask, and noise vs. the
output power for the ADL5372 at 1960 MHz. For a given LO
amplitude, the performance is independent of output power.

4.0

3.5

3.0

2.5

2.0

1.5

PEAK AND RMS EVM (%)

1.0

0.5

0

–6 –4 –2 0 2 4 6

OUTPUT POWER (dBm)

250kHz

PEAK EVM

400kHz

600kHz

1.2MHz

RMS EVM

6 MHz NOISE FLOOR

Figure 34. GSM EVM and Spectral Performance vs. Channel Power at

1960 MHz vs. Output Power; LO Power = 0 dBm

Figure 35 shows the GSM EVM and noise performance vs. the
LO amplitude at 1960 MHz with an output power of 5 dBm.
Increasing the LO drive level improves the noise performance
but degrades EVM performance.

4.0

3.5

3.0

2.5

2.0

1.5
RMS EVM

PEAK AND RMS EVM (%)

1.0

0.5

0

–6 –4 –2 0 2 4 6

LO DRIVE (dBm)

PEAK EVM

6MHz NOISE F LOOR

Figure 35. GSM EVM and 6 MHz Noise Floor vs. LO Power at 1960 MHz;

Output Power = 5 dBm

Figure 35 illustrates that an LO amplitude of 3 dBm provides
the ideal operating point for noise and EVM for a GSM signal
at 1960 MHz.

30

–40

–50

–60

–70

–80

–90

–100

–110

80

–85

–90

–95

–100

–105

–110

–115

–120

SPECTRAL MASK (d Bc/30kHz)

250kHz, 400kHz, 600kHz AND 1200kHz

6MHz OFFS ET NOIS E FLOOR (dBc/100kHz)

6MHz OFF SET NOI SE FLO OR (dBc/100 kHz)

06511-026

06511-027

Rev. 0 | Page 15 of 24

ADL5372

–

–

–

–

–

–

WCDMA OPERATION

The ADL5372 is suitable for operation in a WCDMA
environment, providing better than 72.5 dB of adjacent channel
power ratio (ACPR) at an output power of −10 dBm, with a
20 MHz noise floor of −157 dBm/Hz.

Figure 36 and Figure 37
show the ACPR and 20 MHz offset noise floor of the ADL5372
vs. the output power at LO frequencies of 1966 MHz and
2140 MHz, respectively.

70

–72

–74

–76

–78

POWER RATI OS (dB)

–80

ADJACENT AND ALTERNATE CHANNEL

–82

–14 –13 –12 –11 –10 –9 –8 –7

ALTERNATE CPR

ADJACENT CPR

20MHz NOISE F LOOR

P

(dBm)

OUT

Figure 36. WCDMA Adjacent and Alternate Channel Power ratios and

20 MHz Offset Noise Floor vs. Output Power at 1966 MHz; LO Power = 0 dBm

70

–72

–74

–76

–78

POWE R RATIO S (dB)

–80

ADJACENT AND ALTERNATE CHANNEL

–82

–14 –13 –12 –11 –10 –9 –8 –7

ADJACENT CPR

20MHz NOISE F LOOR

P

(dBm)

OUT

ALTERNATE CPR

Figure 37. WCDMA Adjacent and Alternate Channel Power and 20 MHz

Offset Noise Floor vs. Output Power at 2140 MHz; LO Power = 0 dBm

155.5

–156.0

–156.5

–157.0

–157.5

–158.0

–158.5

155.5

–156.0

–156.5

–157.0

–157.5

–158.0

–158.5

WiMAX OPERATION

Figure 38 demonstrates the ACPR vs. the output power for the
ADL5372 at 2350 MHz. The following test conditions were
applied: a 10 MHz wide 64-QAM OFDM signal with 256
subcarriers, and a raised cosine filter with an α = 0.2.

58

–60

–62

–64

–66

ACPR (dB)

–68

–70

–72

–16 –14 –12 –10 –8 –6 –4 –2

ACPR

70MHz OFFSET NOISE FLOOR

OUTPUT PO WER (dBm)

153

–154

–155

–156

–157

–158

–159

–160

70MHz OFFSET NOISE FLOOR (dBm/Hz)

06511-046

Figure 38. WiMAX ACPR and Noise Floor vs. Output Power at 2350 MHz;

LO Power = 0 dBm

LO GENERATION USING PLLS

Analog Devices has a line of PLLs that can be used for generating

20MHz OFFSET NOIS E FLOO R (dBm/Hz)

the LO signal.
frequency and phase noise performance.

Table 4. Analog Devices PLL Selection Table

06511-034

Part Frequency FIN (MHz)

ADF4110 550 −91 @ 540 MHz
ADF4111 1200 −87 @ 900 MHz
ADF4112 3000 −90 @ 900 MHz
ADF4113 4000 −91 @ 900 MHz
ADF4116 550 −89 @ 540 MHz
ADF4117 1200 −87 @ 900 MHz
ADF4118 3000 −90 @ 900 MHz

The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One is chosen, depending on the local

20MHz OFFSET NOISE FLOOR (dBm/Hz)

oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5372, it can be a cheaper alternative

06511-035

to a separate PLL and VCO solution.
available.

Table 5.

Part Output Frequency Range (MHz)

ADF4360-0 2400 to 2725
ADF4360-1 2050 to 2450
ADF4360-2 1850 to 2150
ADF4360-3 1600 to 1950
ADF4360-4 1450 to 1750
ADF4360-5 1200 to 1400
ADF4360-6 1050 to 1250
ADF4360-7 350 to 1800
ADF4360-8 65 to 400

Table 4 lists the PLLs together with their maximum

Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)

Tabl e 5 shows the options

ADF4360 Family Operating Frequencies

Rev. 0 | Page 16 of 24

ADL5372

TRANSMIT DAC OPTIONS

The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
ADL5372. There are other appropriate DACs, depending on the
level of performance required.
offered by Analog Devices.

Table 6. Dual TxDAC Selection Table

Part Resolution (Bits) Update Rate (MSPS Minimum)

AD9709 8 125
AD9761 10 40
AD9763 10 125
AD9765 12 125
AD9767 14 125
AD9773 12 160
AD9775 14 160
AD9777 16 160
AD9776 12 1000
AD9778 14 1000
AD9779 16 1000

Table 6 lists the dual TxDACs

All DACs listed have nominal bias levels of 0.5 V and use the
same simple DAC modulator interface that is shown in

Figure 32.

MODULATOR/DEMODULATOR OPTIONS

Tabl e 7 lists other Analog Devices modulators and demodulators.

Table 7. Modulator/Demodulator Options

Modulator/

Part No.

AD8345 Modulator 140 to 1000
AD8346 Modulator 800 to 2500
AD8349 Modulator 700 to 2700
ADL5390 Modulator 20 to 2400 External quadrature
ADL5385 Modulator 50 to 2200
ADL5370 Modulator 300 to 1000
ADL5371 Modulator 500 to 1500
ADL5373 Modulator 2300 to 3000
ADL5374 Modulator 3000 to 4000
AD8347 Demodulator 800 to 2700
AD8348 Demodulator 50 to 1000
AD8340

AD8341

Demodulator

Vector
modulator

Vector
modulator

Frequency
Range (MHz)

700 to 1000

1500 to 2400

Comments

Rev. 0 | Page 17 of 24

ADL5372

EVALUATION BOARD

Populated RoHS-compliant evaluation boards are available for
evaluation of the ADL5372. The ADL5372 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the
section). The evaluation board is designed without any
components on the underside so heat can be applied to the
underside for easy removal and replacement of the ADL5372.

QBBP QBBN IBBN IBBP

RFNQ

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

RFPQ

0Ω

CFPQ

OPEN

1

2

3

4

5

6

CFNQ

0Ω

OPEN

RTQ

OPEN

QBBP

QBBN

2423222120

F-MOD

EXPOSED PADDLE

789

OPEN

COM4

Z1

Power Supply and Grounding

RFNI0ΩRFPI

CFNI

COM4

IBBN

101112

RTI

OPEN

IBBP

19

0Ω

CFPI

OPEN

18

17

16

15

14

13

VPS5

VPS4

VPS3

VPS2

VPS2

VOUT

COUT
100pF

C13

0.1µF

C16

0.1µF

C15

0.1µF

C14

0.1µF

L12

0Ω

L11

0Ω

OPEN

C11

VOUT

06511-037

Figure 40. Evaluation Board Layout, Top Layer

VPOS

LOIP

LOIN

COM2

COM3

CLON
100pF

COM3

06511-036

GND

CLOP

100pF

LO

COM2

Figure 39. ADL5372 Evaluation Board Schematic

Table 8. Evaluation Board Configuration Options

Component Description Default Condition

VPOS, GND Power Supply and Ground Clip Leads. Not applicable
RFPI, RFNI, RFPQ, RFNQ, CFPI,

CFNI, CFPQ, CFNQ, RTQ, RTI

Baseband Input Filters. These components can be used to
implement a low-pass filter for the baseband signals. See
the

Filtering section.

RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = Open (0402)
RTQ, RTI = Open (0402)

Rev. 0 | Page 18 of 24

ADL5372

CHARACTERIZATION SETUP

AEROFLEX IFR 3416

250kHz TO 6GHz SIGNAL G ENERATOR

FREQ 4MHz LEVEL 0dBm

BIAS 0.5V
BIAS 0.5V

AGILENT 34401A

VPOS +5V

AGILENT E3631A
POWER SUPPLY

5.000 0.175A

MULTIMETER

0.175 ADC

GAIN 0.7V
GAIN 0.7V

CONNECT TO BACK OF UNIT

I OUT Q OUT

90°

I/AM Q/F M

IQ

RF

OUT

IP

IN

QP

QN

0°

FMOD

R AND S SPECTRUM ANALYZER

FSU 20Hz TO 8GHz

LO

+6dBm

FMOD TEST SETUP

LO

OUTPUT

OUT

GNDVPOS

RF

IN

6V

+

±25V

–

–

+

COM

Figure 41. Characterization Bench Setup

The primary setup used to characterize the ADL5372 is shown
in

Figure 41. This setup was used to evaluate the product as a
single-sideband modulator. The Aeroflex signal generator supplied
the LO and differential I and Q baseband signals to the device
under test, DUT. The typical LO drive was 0 dBm. The I-channel is
driven by a sine wave, and the Q-channel is driven by a cosine
wave. The lower sideband is the single sideband (SSB) output.

6511-038

The majority of characterization for the ADL5372 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the V

IOS

and V

QOS

offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT.
Feedthrough Nulling

section for the definitions of V

See the Carrier

and V

IOS

QOS

.

Rev. 0 | Page 19 of 24

ADL5372

TEKTRONI X AFG3252

DUAL FUNCTIO N

ARBITRARY FUNCTI ON GENERATOR

R AND S SMT 06

1MHz

CH1

AMP L 700 mV p- p
PHASE 0°

1MHz

CH2

AMP L 700 mV p- p
PHASE 90°

AGILENT E3631A
POWER SUPPLY

5.000 0. 350A

6V

–

VPOS +5V

+

VPOS +5V

AGILENT E3631A

POWER SUPPLY

FREQ 4MHz TO 4GHz

CH1 OUTP UT

CH2 OUTP UT

0°

±25V

–

+

COM

–5V

+5V

90°

IQ

SINGLE TO DIFFERENTIAL

CIRCUIT BOARD

FMOD TEST RACK

Q IN AC

Q IN DCCM

TSEN GND

VPOSB VPOSA

IN1

AGND

VN1 VP1

I IN DCCM

I IN AC

IN1

SIGNAL GE NERATOR

LEVEL 0dBm

IP

IN

QP

QN

FMOD

CHAR BD

IP

LO

IN

QP

OUT

QN

GND

VPOS

R AND S FSEA 30

SPECTRUM ANALYZER

RF

OUT

LO

OUTPUT

0.500 0. 010A

6V ±25V

–

+

VCM = 0.5V

AGILENT 34401A

MULTIMETER

0.200 ADC

–

+

COM

Figure 42. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling

The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5372 is shown in

Figure 42.
The interface board has circuitry that converts the single-ended
I input and Q input from the arbitrary function generator to
differential I and Q baseband signals with a dc bias of 500 mV.

RF

IN

100MHz TO 4GHz

+6dBm

06511-039

Undesired sideband nulling was achieved through an iterative
process of adjusting amplitude and phase on the Q-channel. See
Sideband Suppression Optimization section for a detailed
discussion on sideband nulling.

Rev. 0 | Page 20 of 24

ADL5372

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADL5372ACPZ-R2
ADL5372ACPZ-R7
ADL5372ACPZ-WP
ADL5372-EVALZ

1

Z = Pb-free part.

1

–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 250

1

–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 1,500

1

–40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64

1

Evaluation Board

Rev. 0 | Page 21 of 24

ADL5372

NOTES

Rev. 0 | Page 22 of 24

ADL5372

NOTES

Rev. 0 | Page 23 of 24

ADL5372

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06511-0-12/06(0)

T

Rev. 0 | Page 24 of 24

TTT