Datasheet ADL5371 Datasheet (ANALOG DEVICES)

500 MHz to 1500 MHz

FEATURES

Output frequency range: 500 MHz to 1500 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 14.4 dBm @ 900 MHz
Noise floor: −158.6 dBm/Hz @ 915 MHz
Sideband suppression: −55 dBc @ 900 MHz
Carrier feedthrough: −50 dBm @ 900 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP

APPLICATIONS

Cellular communication systems at 900 MHz

CDMA2000/GSM
WiMAX/broadband wireless access systems
Cable communication equipment
Satellite modems

GENERAL DESCRIPTION

The ADL5371 is a member of the fixed-gain quadrature modulator
(F-MOD) family designed for use from 500 MHz to 1500 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.

The ADL5371 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low IF­to-RF applications and in broadband digital predistortion
transmitters.

Quadrature Modulator

ADL5371

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

LOIP

LOIN

QBBN

QBBP

The ADL5371 accepts two differential baseband inputs and
a single-ended local oscillator (LO) and generates a single­ended output.

The ADL5371 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in a
24-lead, exposed-paddle, Pb-free, LFCSP. Performance is specified
over a −40°C to +85°C temperature range. A Pb-free evaluation
board is available.

QUADRATURE

PHASE

SPLITTER

Figure 1.

VOUT

06510-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

ADL5371

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 10

Circuit Description..................................................................... 10

Basic Connections ..........................................................................11

Power Supply and Grounding................................................... 11

Baseband Inputs.......................................................................... 11

LO Input ...................................................................................... 11

RF Output.................................................................................... 11

Optimization............................................................................... 12

Applications Information.............................................................. 13

DAC Modulator Interfacing ..................................................... 13

Limiting the AC Swing .............................................................. 13

Filtering........................................................................................ 13

Using the AD9779 Auxiliary DAC for Carrier Feedthrough

Nulling ......................................................................................... 14

GSM Operation .......................................................................... 14

LO Generation Using PLLs....................................................... 15

Transmit DAC Options ............................................................. 15

Modulator/Demodulator Options ........................................... 15

Evaluation Board............................................................................ 16

Characterization Setup .................................................................. 17

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

1/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADL5371

SPECIFICATIONS

VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f

Table 1.

Parameter Conditions Min Typ Max Unit

ADL5371 Low frequency 500 MHz
High frequency 1500 MHz

Output Power, P

OUT

Output P1dB 14.4 dBm
Carrier Feedthrough −50 dBm
Sideband Suppression −55 dBc
Quadrature Error 0.1 Degrees
I/Q Amplitude Balance −0.03 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor

GSM 6 MHz carrier offset, P

LO INPUTS

LO Drive Level

1

Input Return Loss See Figure 9 for the return loss vs. frequency plot −7 dB

BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN

I/Q Input Bias Level 500 mV
Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc
Input Offset Current 0.1 μA
Differential Input Impedance 2900 kΩ
Bandwidth (0.1 dB) 70 MHz
Bandwidth (1 dB) 350 MHz

POWER SUPPLIES Pin VPS1, Pin VPS2, Pin VPS3, Pin VPS4, and Pin VPS5

Voltage 4.75 5.25 V
Supply Current 175 200 mA

1

Higher LO drive reduces noise at a 6 MHz carrier offset in GSM applications.

2

See the V-to-I Converter section for architecture information.

) = 1 MHz, LO frequency = 900 MHz, unless otherwise noted.

BB

7.6 dBm

− (fLO + (2 × fBB)), P

OUT

− (fLO + (3 × fBB)), P

OUT

I/Q inputs = 0 V differential with a 500 mV common-mode bias,

= 6.2 dBm −56 dBc

OUT

= 6.2 dBm −50 dBc

OUT

= 1.6 dBm per tone 57 dBm

OUT

= 1.6 dBm per tone 27 dBm

OUT

−158.6 dBm/Hz

20 MHz carrier offset

= 5 dBm, PLO = 6 dBm, LO = 940 MHz −158.5 dBc/Hz

OUT

Characterization performed at typical level −6 0 +6 dBm

2

45 μA

Rev. 0 | Page 3 of 20

ADL5371

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V to 2 V
LOIP and LOIN 13 dBm
Internal Power Dissipation 1188 mW
θJA (Exposed Paddle Soldered Down) 54°C/W
Maximum Junction Temperature 152°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 4 of 20

ADL5371

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QBBP

COM4

QBBN

COM4

IBBN

IBBP

2422232120

19

COM1
COM1

VPS1
VPS1
VPS1
VPS1

1
2
3
4
5
6

F-MOD

TOP VIEW

(Not to Scale)

798

101112

LOIP

LOIN

COM2

COM2

COM3

VPS5

18

VPS4

17

VPS3

16

VPS2

15

VPS2

14

VOUT

13

COM3

06510-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2 COM1 Input Common Pins. Connect to ground plane via a low impedance path.
7, 10 COM2 Input Common Pins. Connect to ground plane via a low impedance path.
11, 12 COM3 Input Common Pins. Connect to ground plane via a low impedance path.
21, 22 COM4 Input Common Pins. Connect to ground plane via a low impedance path.
3 to 6 VPS1

Positive Supply Voltage Pins. All pins should be connected to the same supply (V
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).

14, 15 VPS2

Positive Supply Voltage Pins. All pins should be connected to the same supply (V
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).

16 to 18 VPS3 to VPS5

Positive Supply Voltage Pins. All pins should be connected to the same supply (V
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).

8, 9 LOIP, LOIN

50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
AC-couple LOIN to ground and drive LO through LOIP.

13 VOUT

Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output is
ground referenced.

19, 20, 23, 24

IBBP, IBBN,
QBBN, QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to 500 mV dc and must be driven from a low impedance source. Nominal characterized
ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a
500 mV dc bias. These inputs are not self-biased and must be externally biased.

Exposed Paddle Connect to ground plane via a low impedance path.

). To ensure

S

). To ensure

S

). To ensure

S

Rev. 0 | Page 5 of 20

ADL5371

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f

10

9

8

7

6

5

4

3

SSB OUTPUT P OWER (dBm)

2

1

0

10

9

8

7

6

5

4

3

SSB OUTPUT POWER (dBm)

2

1

0

TA = –40°C

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQUENCY (MHz)

Figure 3. Single Sideband (SSB) Output Power (P

LO Frequency (f

VS = 5.0V

VS = 4.75V

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQUENCY (MHz)

Figure 4. Single Sideband (SSB) Output Power (P

LO Frequency (f

5

) = 1 MHz, unless otherwise noted.

BB

TA = +85°C

TA = +25°C

) vs.

) and Temperature

LO

VS = 5.25V

) and Supply

LO

OUT

OUT

) vs.

16

15

TA = –40°C

14

13

12

11

10

9

8

1dB OUTPUT COMPRESSI ON (dBm)

7

6

500 600 700 800 900 1000 1100 1200 1300 1400 1500

6510-003

Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. f

16

15

14

13

12

11

10

9

8

1dB OUTPUT COMPRESSI ON (dBm)

7

6

500 600 700 800 900 1000 1100 1200 1300 1400 150 0

6510-004

Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. f

120

TA = +85°C

LO FREQ UENCY (MHz)

VS = 5.0V

VS = 5.25V

LO FREQ UENCY (MHz)

90

TA = +25°C

VS = 4.75V

and Temperature

LO

and Supply

LO

60

06510-006

06510-007

0

OUTPUT PO WER VARIANCE (d B)

–5

1 10 100 1000

BASEBAND FREQUENCY (M Hz)

Figure 5. I/Q Input Bandwidth Normalized to

Gain @ 1 MHz (f

= 900 MHz)

LO

06510-005

Rev. 0 | Page 6 of 20

150

210

S11 OF LOIP
S22 OF OUTPUT

240

500MHz

1500MHz

1500MHz

500MHz

270

Figure 8. Smith Chart of LOIP S11 and VOUT S22

from 500 MHz to 1500 MHz)

(f

LO

300

30

330

0180

06510-008

ADL5371

–

0

–5

–10

–15

RETURN LOSS (dB)

–20

–25

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQUENCY (MHz)

Figure 9. Return Loss (S11) of LOIP

6510-009

0

–10

–20

TA = +85°C

–30

–40

–50

–60

–70

SIDEBAND SUPPRESSION (dBc)

–80

–90

500 600 700 800 900 1000 1100 1200 1300 1400 1500

TA = +25°C

TA = –40°C

LO FREQ UENCY (MHz)

Figure 12. Sideband Suppression vs.

and Temperature (Multiple Devices Shown)

f

LO

06510-012

0

–10

–20

CARRIER FEEDTHRO UGH (dBm)

–30

–40

–50

–60

–70

–80

–90

TA = +25°C

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQ UENCY (MHz)

TA = –40°C

TA = +85°C

Figure 10. Carrier Feedthrough vs.

and Temperature (Multiple Devices Shown)

f

LO

0

–10

–20

–30

TA = +85°C

–40

–50

–60

–70

CARRIER FEEDTHROUG H (dBm)

–80

–90

500 600 700 800 900 1000 1100 1200 1300 1400 1500

TA = +25°C

LO FREQ UENCY (MHz)

TA = –40°C

0

–10

–20

–30

TA = +85°C

–40

–50

–60

–70

SIDEBAND SUPPRESSION (dBc)

–80

–90

06510-010

TA = +25°C

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQUENCY (MHz)

Figure 13. Sideband Suppression vs. f

TA = –40°C

and Temperature After

LO

06510-013

Nulling at 25°C (Mu ltiple Devic es Show n)

20

–30

–40

–50

–60

SIDEBAND SUPPRESSION

–70

DISTORTION, CARRIE R FEEDTHROUG H,

SECOND-ORDER DI STORTI ON, THI RD-ORDER

–80

6510-011

CARRIER

FEEDTHROUG H (dBm)

THIRD-ORDER ( dBc)

0.20.61.01.41.82.22.63.03.4

SSB OUTPUT P OWER (d Bm)

SIDEBAND SUPPRESSION (dBc)

SECOND-ORDER (dBc)

BASEBAND INPUT VO LTAGE ( V p-p)

15

10

5

0

–5

–10

–15

SSB OUTPUT PO WER (dBm)

06510-014

Figure 11. Carrier Feedthrough vs. f

Nulling at 25°C (Multiple Devices Shown)

and Temperature After

LO

Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

vs. Baseband Differential Input Level

OUT

= 900 MHz)

(f

LO

Rev. 0 | Page 7 of 20

ADL5371

–

–

–

20

–30

–40

–50

THIRD-ORDER

T

= +85°C

A

THIRD-ORDER

= +25°C

T

A

THIRD- ORDER

= –40°C

T

A

80

70

60

50

40

TA = –40°C

TA = +85°C

TA = +25°C

–60

SECOND-ORDER

= +25°C

T

THIRD-ORDER DI STORTION (dBc)

–70

SECOND-ORDER DISTORTI ON AND

SECOND-ORDER

= +85°C

T

A

–80

500 600 700 800 900 1000 1100 1200 1300 1400 1500

A

LO FREQUENCY (MHz)

Figure 15. Second- and Third-Order Distortion vs. f

SECOND-ORDER

= –40°C

T

A

and Temperature

LO

(Baseband I/Q Amplitude = 1.4 V p-p Differential)

20

–25

–30

–35

–40

–45

SUPPRESSION

–50

–55

SECOND-ORDER DIST ORTIO N, THIRD-ORDER

–60

DISTORTION, CARRIER F EEDTHROUGH, SIDEBAND

CARRIER

FEEDTHROUG H (dBm)

1M 10M 100M

BASEBAND FREQUENCY ( Hz)

SIDEBAND SUPPRESSION (dBc)

THIRD-ORDER ( dBc)

SECOND-ORDER (d Bc)

Figure 16. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

30

TA = –40°C

25

20

15

10

5

OUTPUT THIRD ORDER INTE RCEPT (dBm)

0

500 600 700 800 900 1000 1100 1200 1300 1400 1500

LO FREQUE NCY (MHz)

vs. fBB (fLO = 900 MHz)

OUT

TA = +85°C

TA = +25°C

Figure 17. OIP3 vs. Frequency and Temperature

30

20

10

OUTPUT SECO ND ORDER INTE RCEPT (dBm)

0

500 600 700 800 900 1000 1100 1200 1300 1400 1500

06510-015

LO FREQUENCY (MHz)

06510-019

Figure 18. OIP2 vs. Frequency and Temperature

20

SSB OUTPUT POWER (dBm)

–30

–40

–50

SIDEBAND SUPPRESSI ON

–60

DISTORTION, CARRIER F EEDTHROUGH,

SECOND-ORDER DIST ORTIO N, THIRD-ORDER

06510-016

SIDEBAND SUPP RESSION (dBc)

–70

–6 –4 –2 0 2 4 6–5 –3 –1 1 3 5

CARRIER

FEEDTHROUGH (dBm)

LO AMPL ITUDE ( dBm)

THIRD-ORDER (dBc)

SECOND-ORDER (dBc)

8

7

6

5

4

SSB OUTPUT POWER (dBm)

3

06510-020

Figure 19. Second- and Third-Order Distortion, Carrier Feedthrough,

Sideband Suppression, and SSB P

0.20

0.19

0.18

0.17

0.16

0.15

0.14

0.13

SUPPLY CURRENT (A)

0.12

0.11

0.10

06510-018

VS = 5.25V

VS = 5.0V

VS = 4.75V

–40 35 60–15 10 85

vs. LO Amplitude (fLO = 900 MHz)

OUT

TEMPERATURE (° C)

06510-022

Figure 20. Power Supply Current vs. Temperature

Rev. 0 | Page 8 of 20

ADL5371

25

20

15

QUANTITY

10

5

0

–159.6

–159.4

–159.2

–159.0

–158.8

NOISE AT 20MHz OFFSET (dBm/Hz)

–158.6

f

= 915MHz

LO

–158.4

–158.2

–158.0

–157.8

–157.6

06510-021

Figure 21. 20 MHz Offset Noise Floor Distribution at f

(I/Q Amplitude = 0 mV p-p with 500 mV dc Bias)

= 915 MHz

LO

Rev. 0 | Page 9 of 20

ADL5371

THEORY OF OPERATION

CIRCUIT DESCRIPTION

Overview

The ADL5371 can be divided into five circuit blocks: the LO
interface, the baseband voltage-to-current (V-to-I) converter,
the mixers, the differential-to-single-ended (D-to-S) converter,
and the bias circuit. A detailed block diagram of the device is
shown in

The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I/Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the output balun, which provides a single-ended output
interface. The bias cell generates a reference current for the
V-to-I stage .

LO Interface

The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. The LO can be driven either single-ended or
differentially. When driven single-ended, the LOIN pin should
be ac-grounded via a capacitor. Each quadrature LO signal then
passes through a limiting amplifier that provides the mixer with
a limited drive signal.

Figure 22.

LOIP

LOIN

IBBP

IBBN

QBBP

QBBN

PHASE

SPLITTER

Σ

Figure 22. Block Diagram

OUT

6510-023

V-to-I Converter

The differential baseband inputs (QBBP, QBBN, IBBN, and
IBBP) consist of the bases of PNP transistors, which present a
high impedance. The voltages applied to these pins drive the
V-to-I stage that converts baseband voltages into currents. The
differential output currents of the V-to-I stages feed each of
their respective Gilbert-cell mixers. The dc common-mode
voltage at the baseband inputs sets the currents in the two mixer
cores. Varying the baseband common-mode voltage varies the
current in the mixer and affects overall modulator performance.
The recommended dc voltage for the baseband common-mode
voltage is 500 mV dc.

Mixers

The ADL5371 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature
channel (Q channel). Both mixers are based on the Gilbert-cell
design of four cross-connected transistors. The output currents
from the two mixers sum together into an on-chip balun, which
converts the differential signal to single-ended.

D-to-S Stage

The output D-to-S stage consists of an on-chip balun that
converts the differential signal to a single-ended signal. The
balun presents high impedance to the output (VOUT).
Therefore, a matching network may be needed at the output for
optimal power transfer.

Bias Circuit

An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage.

Rev. 0 | Page 10 of 20

ADL5371

BASIC CONNECTIONS

Figure 23 shows the basic connections for the ADL5371.

QBBP Q BBN IBBN IBBP

C16

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

1

2

3

4

5

6

GND

CLOP

100pF

QBBP

COM4

QBBN

COM4

2423222120

Z1

F-MOD

EXPOSED PADDLE

789

COM2

LO

LOIP

LOIN

101112

COM2

CLON
100pF

IBBN

COM3

IBBP

19

COM3

18

17

16

15

14

13

VPS5

VPS4

VPS3

VPS2

VPS2

VOUT

COUT
100pF

C13

0.1µF

0.1µF

C15

0.1µF

C14

0.1µF

C11

OPEN

VPOS

VOUT

Figure 23. Basic Connections for the ADL5371

POWER SUPPLY AND GROUNDING

All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 µF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.

The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note
thermal and electrical grounding of the LFCSP in detail.

AN-772 discusses the

06510-024

BASEBAND INPUTS

The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of

1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.

The dc common-mode bias level for the baseband inputs range
from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5371 input range and on the top end by the output compliance
range on most DACs from Analog Devices.

LO INPUT

A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.

The nominal LO drive of 0 dBm can be increased to up to 7 dBm
to realize an improvement in the noise performance of the
modulator (see

Figure 33). This improvement is tempered by
degradation in the sideband suppression performance (see
Figure 19) and, therefore, should be used judiciously. If the LO
source cannot provide the 0 dBm level, operation at a reduced
power below 0 dBm is acceptable. Reduced LO drive results in
slightly increased modulator noise. The effect of LO power on
sideband suppression and carrier feedthrough is shown in
Figure 19. The effect of LO power on GSM noise is shown in
Figure 33.

RF OUTPUT

The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50  load. For applications requiring 50  output
impedance, external matching is needed (see
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.

Figure 8 for S22

Rev. 0 | Page 11 of 20

ADL5371

–

–

OPTIMIZATION

The carrier feedthrough and sideband suppression performance
of the ADL5371 can be improved by using optimization
techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator, the quantities (V
are equal to zero, which results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero, and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5371 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (V
and (V

QOPP

− V

) offsets. The I-channel offset is held constant

QOPN

while the Q-channel offset is varied until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant, while the offset on the I­channel is adjusted until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 24 shows the relationship of carrier feedthrough vs. dc
offset as null.

60

–64

–68

–72

–76

–80

CARRIER FEEDTHRO UGH (dBm)

–84

–88

–300 –240 –180 –120 –60 0 60 120 180 240 300

Figure 24. Typical Carrier Feedthrough vs. DC Offset Voltage

Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied,

= V

V

IOPP

V

IOPP

When an offset of +V

V

IOPP

V

IOPN

V

IOPP

= 500 mV, or

IOPN

− V

= V

IOPN

IOS

IOS

= 500 mV + V

= 500 mV − V

− V

= V

IOPN

IOS

= 0 V

The same applies to the Q channel inputs.

− V

IOPN

) and (V

IOPP

VP – VN OFFSET (µV)

QOPP

IOPP

− V

− V

QOPN

is applied to the I-channel inputs,

/2, and

IOS

/2, such that

IOS

IOPN

)

)

06510-025

It is often desirable to perform a one-time carrier null calibra­tion. This is usually performed at a single frequency.

Figure 25
shows how carrier feedthrough varies with LO frequency over a
range of ±50 MHz on either side of a null at 940 MHz.

40

–45

–50

–55

–60

–65

–70

–75

–80

CARRIER FEEDTHRO UGH (dBm)

–85

–90

890 900 910 920 930 940 950 960 97 0 980 990

LO FREQUENCY (MHz)

06510-026

Figure 25. Carrier Feedthrough vs. Frequency After Nulling at 940 MHz

Sideband Suppression Optimization

Sideband suppression results from relative gain and relative
phase offsets between the I/Q channels and can be suppressed
through adjustments to those two parameters.

Figure 26
illustrates how sideband suppression is affected by the gain and
phase imbalances.

0

–10

2.5dB

–20

1.25dB

0.5dB

–30

0.25dB

–40

0.125dB

0.05dB

–50

0.025dB

–60

0.0125dB

–70

SIDEBAND SUPPRESSI ON (dBc)

0dB

–80

–90

0.01 0.1 1 10 100

PHASE ERROR (Deg rees)

06510-027

Figure 26. Sideband Suppression vs. Quadrature Phase Error for Various

Quadrature Amplitude Offsets

Figure 26 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance more than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.

The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.

Rev. 0 | Page 12 of 20

ADL5371

APPLICATIONS INFORMATION

DAC MODULATOR INTERFACING

The ADL5371 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.

Driving the ADL5371 with a TxDAC®

An example of the interface using the AD9779 TxDAC is shown

Figure 27. The baseband inputs of the ADL5371 require a dc

in
bias of 500 mV. The average output current on each

AD9779
output is 10 mA. Therefore, a single 50 Ω resistor to ground
from each DAC output results in an average current of 10 mA
flowing through each resistor, thus producing the desired
500 mV dc bias for the inputs to the ADL5371.

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

Figure 27. Interface Between the

Ground to Establish the 500 mV dc Bias for the ADL5371 Baseband Inputs

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

19

IBBP

20

IBBN

23

QBBN

24

QBBP

06510-028

AD9779 and ADL5371 with 50 Ω Resistors to

The AD9779 output currents have a swing that ranges from 0 to
20 mA. With the 50 Ω resistors in place, the ac voltage swing
going into the ADL5371 baseband inputs ranges from 0 V to 1 V.
A full-scale sine wave out of the

AD9779 can be described as a
1 V p-p single-ended (or 2 V p-p differential) sine wave with a
500 mV dc bias.

LIMITING THE AC SWING

There are situations when it is desirable to reduce the ac voltage
swing for a given DAC output current. This can be achieved
through the addition of another resistor to the interface. This
resistor is placed in shunt between each side of the differential
pair, as shown in
swing without changing the dc bias already established by the
50 Ω resistors.

Figure 28. It has the effect of reducing the ac

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

93

RBIP

50Ω

RBIN

50Ω

92

84

RBQN

50Ω

RBQP

50Ω

83

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

Figure 28. AC Voltage Swing Reduction Through the Introduction

of a Shunt Resistor Between the Differential Pair

The value of this ac voltage swing-limiting resistor is chosen
based on the desired ac voltage swing.

Figure 29 shows the
relationship between the swing-limiting resistor and the peak­to-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

DIFFERENTIAL SWING (V p-p)

0.4

0.2

0

10 100 1000 10000

RL (Ω)

06510-030

Figure 29. Relationship Between the AC Swing-Limiting Resistor and the

Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors

FILTERING

It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing discussed in the
Swing

section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias-setting
resistors and the ac swing-limiting resistor. Doing so establishes
the input and output impedances for the filter.

Limiting the AC

06510-029

Rev. 0 | Page 13 of 20

ADL5371

–

–

Figure 30 shows an example of a third-order elliptical filter
with a 3 dB frequency of 3 MHz. Matching input and output
impedances makes the filter design easier, so the shunt resistor
chosen is 100 Ω, producing an ac swing of 1 V p-p differential.

C1I

C1Q

LPI

2.7nH

1.1nF

LNI

2.7nH

LNQ

2.7nH

1.1nF

LPQ

2.7nH

C2I

C2Q

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

AD9779 F-MOD

OUT1_P

OUT1_N

OUT2_N

OUT2_P

93

92

84

83

RBIP

50Ω

RBIN

50Ω

RBQN

50Ω

RBQP

50Ω

1.1nF

1.1nF

Figure 30. DAC Modulator Interface with 3 MHz Third-Order, Low-Pass Filter

USING THE AD9779 AUXILIARY DAC FOR CARRIER FEEDTHROUGH NULLING

The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator.
to use the auxiliary DACs. This adds four resistors to the
interface.

AUX1_P

AD9779 F-MOD

OUT1_P

OUT1_N

AUX1_N

AUX2_N

OUT2_N

OUT2_P

AUX2_P

90

500Ω

93

92

89

500Ω

87

500Ω

84

83

86

500Ω

Figure 31. DAC Modulator Interface with Auxiliary DAC Resistors

Figure 31 shows the interface required

RBIP

50Ω

RBIN

50Ω

RBQN

50Ω

RBQP

50Ω

250Ω

1.1nF

250Ω

250Ω

1.1nF

250Ω

C1I

C1Q

LPI

2.7nH

1.1nF

LNI

2.7nH

LNQ

2.7nH

1.1nF

LPQ

2.7nH

C2I

C2Q

RSLI

100Ω

RSLQ

100Ω

19

IBBP

20

IBBN

23

QBBN

24

QBBP

06510-031

06510-032

GSM OPERATION

Figure 32 shows the GSM/EDGE EVM and spectral mask
performance vs. output power for the ADL5371 at 940 MHz.
For a given LO amplitude, the performance is independent of
output power.

30

–40

–50

–60

–70

–80

–90

SPECTRAL MASK (dB c/30kHz)

–100

250kHz, 400kHz, 600kHz, AND 1200kHz

6MHz OFF SET NO ISE FL OOR (d Bc/100kHz)

–110

–6 6

250kHz

400kHz

6MHz NOIS E FLO OR

EVM RMS (%)

OUTPUT POWE R (dBm)

1200kHz

600kHz

EVM PEAK (%)

420–2–4

Figure 32. GSM/EDGE (8 PSK) EVM and Spectral Performance vs. Channel

Power at 940 MHz vs. Output Power; LO Power = 0 dBm

Figure 33 shows the GSM/EDGE EVM and 6 MHz offset noise
vs. LO amplitude at 940 MHz with an output power of 5 dBm.
Increasing the LO drive level improves the noise performance
with minimal degradation in EVM performance.

90

–95

–100

–105

–110

–115

–120

–125

6MHz OFFSET NOISE FLOOR (dBc/100kHz)

–130

–6 6

6MHz NOISE F LOOR

EVM PEAK (%)

EVM RMS (%)

420–2–4

LO DRIVE (dBm)

Figure 33. GSM/EDGE (8 PSK) EVM, Spectral Performance, and 6 MHz Noise

Floor vs. LO Power at 940 MHz; Output Power = 5 dBm

Figure 33 illustrates that an LO amplitude of 3 dBm provides
the ideal operating point for noise and EVM for a GSM/EDGE
signal at 940 MHz.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

PEAK AND RMS EVM (%)

06510-033

PEAK AND RMS EVM (%)

06510-034

Rev. 0 | Page 14 of 20

ADL5371

LO GENERATION USING PLLS

Analog Devices has a line of PLLs that can be used for
generating the LO signal.
their maximum frequency and phase noise performance.

Table 4. ADI PLL Selection Table

Part Frequency fIN (MHz)

ADF4110 550 −91 @ 540 MHz
ADF4111 1200 −87 @ 900 MHz
ADF4112 3000 −90 @ 900 MHz
ADF4113 4000 −91 @ 900 MHz
ADF4116 550 −89 @ 540 MHz
ADF4117 1200 −87 @ 900 MHz
ADF4118 3000 −90 @ 900 MHz

The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One is chosen, depending on the local
oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5371, it can be a cheaper alternative
to a separate PLL and VCO solution.
available.

Table 5.

Part Output Frequency Range (MHz)

ADF4360-0 2400 to 2725
ADF4360-1 2050 to 2450
ADF4360-2 1850 to 2150
ADF4360-3 1600 to 1950
ADF4360-4 1450 to 1750
ADF4360-5 1200 to 1400
ADF4360-6 1050 to 1250
ADF4360-7 350 to 1800
ADF4360-8 65 to 400

ADF4360 Family Operating Frequencies

Tabl e 4 lists the PLLs together with

Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)

Tabl e 5 shows the options

TRANSMIT DAC OPTIONS

The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
ADL5371. There are other appropriate DACs, depending on the
level of performance required.

Table 6 lists the dual TxDACs

offered by Analog Devices.

Table 6. Dual TxDAC Selection Table

Part Resolution (Bits) Update Rate (MSPS Minimum)

AD9709 8 125
AD9761 10 40
AD9763 10 125
AD9765 12 125
AD9767 14 125
AD9773 12 160
AD9775 14 160
AD9777 16 160
AD9776 12 1000
AD9778 14 1000
AD9779 16 1000

All DACs listed have nominal bias levels of 0.5 V and use the same
simple DAC-modulator interface that is shown in

Figure 29.

MODULATOR/DEMODULATOR OPTIONS

Tabl e 7 lists other Analog Devices modulators and demodulators.

Table 7. Modulator/Demodulator Options

Modulator/

Part

AD8345 Modulator 140 to 1000
AD8346 Modulator 800 to 2500
AD8349 Modulator 700 to 2700
ADL5390 Modulator 20 to 2400

ADL5385 Modulator 50 to 2200
ADL5370 Modulator 300 to 1000
ADL5372 Modulator 1500 to 2500
ADL5373 Modulator 2300 to 3000
ADL5374 Modulator 3000 to 4000
AD8347 Demodulator 800 to 2700
AD8348 Demodulator 50 to 1000
AD8340

AD8341

Demodulator

Vector
modulator

Vector
modulator

Frequency
Range (MHz)

700 to 1000

1500 to 2400

Comments

External
quadrature

Rev. 0 | Page 15 of 20

ADL5371

EVALUATION BOARD

Populated RoHS-compliant evaluation boards are available for
evaluation of the ADL5371. The ADL5371 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the
section). The evaluation board is designed without any
components on the underside so heat can be applied to the
underside for easy removal and replacement of the ADL5371.

QBBP Q BBN IBBN IBBP

RFNQ

VPOS

COM1

COM1

VPS1

VPS1

VPS1

VPS1

C12

0.1µF

RFPQ

0Ω

CFPQ
OPEN

1

2

3

4

5

6

CFNQ

0Ω

OPEN

RTQ

OPEN

QBBP

QBBN

2423222120

F-MOD

EXPOSED PADDLE

789

OPEN

COM4

Z1

Power Supply and Grounding

RFNI0ΩRFPI

CFNI

COM4

IBBN

101112

RTI

OPEN

IBBP

19

0Ω

CFPI

OPEN

18

17

16

15

14

13

VPS5

VPS4

VPS3

VPS2

VPS2

VOUT

COUT
100pF

C13

0.1µF

C16

0.1µF

C15

0.1µF

C14

0.1µF

L12

0Ω

L11

0Ω

C11

OPEN

VOUT

06510-037

Figure 35. Evaluation Board Layout, Top Layer

VPOS

LOIP

LOIN

COM2

COM3

CLON
100pF

COM3

06510-036

GND

CLOP

100pF

COM2

LO

Figure 34. ADL5371 Evaluation Board Schematic

Table 8. Evaluation Board Configuration Options

Component Description Default Condition

VPOS, GND Power Supply and Ground Clip Leads. Not applicable
RFPI, RFNI, RFPQ, RFNQ, CFPI,

CFNI, CFPQ, CFNQ, RTQ, RTI

Baseband Input Filters. These components can be used
to implement a low-pass filter for the baseband signals.
See the

Filtering section.

RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = Open (0402)
RTQ, RTI = Open (0402)

Rev. 0 | Page 16 of 20

ADL5371

CHARACTERIZATION SETUP

AEROFLEX IFR 3416

250kHz TO 6GHz SIGNAL G ENERATOR

RF

OUT

R AND S SPECTRUM ANALYZER

FSU 20Hz TO 8GHz

LO

CONNECT TO BACK OF UNIT

I OUT Q OUT

I/AM Q/FM

VPOS +5V

AGILENT 34401A

MULTIMETER

AGILENT E3631A
POWER SUPPLY

6V

+

±25V

–

+

COM

90°

–

IQ

Figure 36. Characterization Bench Setup

The primary setup used to characterize the ADL5371 is shown
in

Figure 36. This setup was used to evaluate the product as a
single-sideband modulator. The Aeroflex signal generator supplied
the LO and differential I/Q baseband signals to the device
under test, DUT. The typical LO drive was 0 dBm. The I channel
is driven by a sine wave, and the Q channel is driven by a cosine
wave. The lower sideband is the single sideband (SSB) output.

RF

IN

06510-038

IP

IN

QP

QN

0°

FMOD

OUT

GNDVPOS

+6dBm

FMOD TEST SETUP

LO

OUTPUT

The majority of characterization for the ADL5371 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the V

IOS

and V
offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT. See the
Carrier Feedthrough Nulling section for the definitions of
V

and V

IOS

QOS

.

QOS

Rev. 0 | Page 17 of 20

ADL5371

TEKTRONI X AFG3252

DUAL FUNCTIO N

ARBITRARY FUNCTI ON GENERATOR

R AND S SMT 06

SIGNAL GE NERATOR

RF

OUT

CH1 OUTP UT

CH2 OUTP UT

LO

OUTPUT

AGILENT E3631A

POWER SUPPLY

6V

–

VPOS +5V

+

VPOS +5V

AGILENT E3631A

POWER SUPPLY

0°

±25V

–

+

COM

–5V

+5V

90°

IQ

SINGLE TO DIFFERENTIAL

CIRCUIT BOARD

FMOD TEST RACK

Q IN AC

Q IN DCCM

TSEN GND

VPOSB VPOSA

IN1

AGND

VN1 VP1

I IN DCCM

I IN AC

IN1

QP

QN

FMOD

CHAR BD

IP

IN

IP

LO

IN

QP

OUT

QN

GND

VPOS

R AND S FSEA 30

SPECTRUM ANALYZER

6V ±25V

–

+

VCM = 0.5V

AGILENT 34401A

MULTIMETER

–

+

COM

Figure 37. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling

The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5371 is shown in

Figure 37.
The interface board has circuitry that converts the single-ended
I/Q inputs from the arbitrary function generator to differential
I/Q baseband signals with a dc bias of 500 mV. Undesired

RF

IN

100MHz TO 4GHz

+6dBm

06510-039

sideband nulling was achieved through an iterative process of
adjusting amplitude and phase on the Q channel. See the
Sideband Suppression Optimization section for a detailed
discussion on sideband nulling.

Rev. 0 | Page 18 of 20

ADL5371

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50
BSC

0.50

0.40

0.30

0.08

Figure 38. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADL5371ACPZ-R2
ADL5371ACPZ-R7
ADL5371ACPZ-WP
ADL5371-EVALZ

1

Z = Pb-free part.

1

–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 250

1

–40°C to +85°C 24-Lead LFCSP_VQ, 7” Tape and Reel CP-24-2 1,500

1

–40°C to +85°C 24-Lead LFCSP_VQ, Waffle Pack CP-24-2 64

1

Evaluation Board

Rev. 0 | Page 19 of 20

ADL5371

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06510-0-1/07(0)

T

Rev. 0 | Page 20 of 20

TTT