Datasheet ADL5367 Datasheet (ANALOG DEVICES)

500 MHz to 1700 MHz Balanced Mixer,

V

FEATURES

RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 8.3 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 34 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance

APPLICATIONS

Cellular base station receivers
Transmit observation receivers
Radio link downconverters

GENERAL DESCRIPTION

The ADL5367 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5367 incorporates
an RF balun, allowing optimal performance over a 500 MHz to
1700 MHz RF input frequency range. Performance is optimized for
RF frequencies from 500 MHz to 1200 MHz using a high-side LO
and for RF frequencies from 900 MHz to 1700 MHz using a
low-side LO. The balanced passive mixer arrangement provides
good LO-to-RF leakage, typically better than −35 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where in­band blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
loss of 7.7 dB and can be used with a wide range of output
impedances.

LO Buffer and RF Balun

ADL5367

FUNCTIONAL BLOCK DIAGRAM

CMI IFOP IFON PWDN COMM

20 19 18 17 16

1

VPMX

2

RFIN

3

RFCT

BIAS

GENERATOR

4

COMM

5

COMM

6 7 8 9 10

VLO3 LGM3 VLO2 LOSW NC

NC = NO CONNECT

Figure 1.

The ADL5367 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5367 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.

The ADL5367 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.

Table 1. Passive Mixers

RF Frequency
(MHz)

Single
Mixer

Single Mixer +
IF Amp

500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356

ADL5367

15

LOI2

14

VPSW

13

VGS1

12

VGS0

11

LOI1

Dual Mixer +
IF Amp

8083-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADL5367

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Performance ........................................................................... 4

3.3 V Performance ........................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

5 V Performance ........................................................................... 7

3.3 V Performance ...................................................................... 14

Upconversion .............................................................................. 15

Spur Tables .................................................................................. 16

Circuit Description......................................................................... 17

RF Subsystem .............................................................................. 17

LO Subsystem ............................................................................. 17

Applications Information .............................................................. 19

Basic Connections ...................................................................... 19

IF Port .......................................................................................... 19

Bias Resistor Selection ............................................................... 19

Mixer VGS Control DAC .......................................................... 19

Evaluation Board ............................................................................ 20

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5367

SPECIFICATIONS

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 14 dB
Input Impedance 50 Ω
RF Frequency Range 500 1700 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 34||1.9 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V

LO INTERFACE

LO Power −6 0 +10 dBm
Return Loss 12.6 dB
Input Impedance 50 Ω
LO Frequency Range 730 1670 MHz

POWER-DOWN (PWDN) INTERFACE

PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 220 ns
PWDN Input Bias Current Device enabled 0.0 μA

Device disabled 70 μA

1

Apply the supply voltage from the external circuit through the choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

2

Rev. 0 | Page 3 of 24

ADL5367

5 V PERFORMANCE

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Loss Including 1:1 IF port transformer and PCB loss 6.5 7.7 8.5 dB
Voltage Conversion Loss Z
SSB Noise Figure 8.3 dB
SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device 25 dBm
LO-to-IF Leakage Unfiltered IF output −15 dBm
LO-to-RF Leakage −40 dBm
RF-to-IF Isolation −47 dBc
IF/2 Spurious 0 dBm input power −75 dBc
IF/3 Spurious 0 dBm input power −72 dBc

POWER SUPPLY

Positive Supply Voltage 4.5 5 5.5 V
Total Quiescent Current VS = 5 V 97 mA

1

Exceeding 20 dBm RF power results in damage to the device.

= 50 Ω, differential Z

SOURCE

= 50 Ω differential 1.4 dB

LOAD

5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered

= 899.5 MHz, f

f

RF1

= 900.5 MHz, fLO = 1103 MHz,

RF2

each RF tone at 0 dBm

= 950 MHz, f

f

RF1

= 900 MHz, fLO = 1103 MHz,

RF2

each RF tone at 0 dBm

21 dB

28 34 dBm

80 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Loss Including 4:1 IF port transformer and PCB loss 7.3 dB
Voltage Conversion Loss Z
SSB Noise Figure 8.1 dB
Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 56 mA
Power-Down Current Device disabled 150 μA

= 50 Ω, differential Z

SOURCE

= 1949.5 MHz, f

f

RF1

= 1950.5 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 1 dB

LOAD

28.5 dBm

75 dBm

Rev. 0 | Page 4 of 24

ADL5367

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
IFOP, IFON Bias Voltage 6.0 V
VGS0, VGS1, LOSW, PWDN 5.5 V
Internal Power Dissipation 1.2 W
θJA 25°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5367

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DN

IFON

IFOP

VCMI

PW

COMM

17

16

18

19

20

PIN 1
INDICATOR

1VPMX
2RFIN

ADL5367

3RFCT

TOP VIEW

4COMM

(Not to S cale)

5COMM

8

6

7

VLO3

VLO2

LGM3

NOTES

1.2 NC = NO CONNECT.
. EXPOSED PAD. MUST BE SOLDERED

TO GROUND.

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 VPMX Positive Supply Voltage for IF Amplifier.
2 RFIN RF Input. This pin must be ac-coupled.
3 RFCT RF Balun Center Tap (AC Ground).
4, 5, 16 COMM Device Common (DC Ground).
6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
7 LGM3 LO Amplifier Bias Control.
9 LOSW LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V.
10 NC No Connect.
11, 15 LOI1, LOI2 LO Inputs. This pin must be ac-coupled.
12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
14 VPSW Positive Supply Voltage for LO Switch.
17 PWDN Power Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
18, 19 IFON, IFOP Differential IF Outputs.
20 VCMI No Connect. This pin can be grounded.
EPAD (EP) Exposed pad must be soldered to ground.

15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1

9

10
NC

LOSW

08083-002

Rev. 0 | Page 6 of 24

ADL5367

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

110

100

105

100

95

90

SUPPLY CURRENT (mA)

85

80

700 750 800 850 900 950 1000 1050 1100 1150 1200

= +25°C

T

A

RF FREQUENCY ( M H z)

TA =–40°C

TA = +85°C

Figure 3. Supply Current vs. RF Frequency

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION LOSS (dB)

6.0

5.5

5.0

700 750 800 850 900 950 1000 1050 1100 1150 1200

T

= +25°C

A

TA =–40°C

RF FREQUENC Y ( MHz)

TA = +85°C

Figure 4. Power Conversion Loss vs. RF Frequency

40

90

80

70

INPUT IP2 (dBm)

60

50

40

700 750 800 850 900 950 1000 1050 1 100 1150 1200

08083-017

TA = –40°C

TA = +85°C

RF FREQUENCY ( MHz )

= +25°C

T

A

08083-023

Figure 6. Input IP2 vs. RF Frequency

12

11

10

9

8

7

SSB NOISE FIGURE (dB)

6

5

700 750 800 850 900 950 1000 1050 1100 1150 1200

08083-035

TA = +85ºC

TA = +25ºC

TA = –40ºC

RF FREQUENCY ( MHz)

08083-011

Figure 7. SSB Noise Figure vs. RF Frequency

38

36

34

32

INPUT IP3 (dBm)

30

28

26

T

= +25°C

A

TA = –40°C

TA = +85°C

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY ( M H z)

08083-028

Figure 5. Input IP3 vs. RF Frequency

Rev. 0 | Page 7 of 24

ADL5367

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

110

86

105

V

= 5.25V

V

POS

POS

= 5V

= 4.75V

TEMPERATURE (°C)

100

95

V

POS

90

SUPPLY CURRENT (mA)

85

80

–40 –20 0 20 40 60 80

Figure 8. Supply Current vs. Temperature

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION L O S S (d B)

6.0

5.5

5.0

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

V
V
V

Figure 9. Power Conversion Loss vs. Temperature

40

POS
POS
POS

= 4.75V
= 5V
= 5.25V

84

82

80

78

76

INPUT IP2 (dBm)

74

72

70

–40 –20 0 20 40 60 80

08083-019

V

= 5V

POS

TEMPERATURE (°C)

V

= 5.25V

POS

V

= 4.75V

POS

8083-025

Figure 11. Input IP2 vs. Temperature

12

11

10

9

8

V

7

SSB NOISE FIGURE (dB)

6

5

–40 –20 0 20 40 60 80

08083-038

POS

TEMPERATURE (ºC)

= 4.75V

V

= 5.25V

POS

V

= 5V

POS

08083-012

Figure 12. SSB Noise Figure vs. Temperature

38

V

= 5.25V

V

POS

POS

= 4.75V

8083-030

36

34

32

INPUT IP3 (dBm)

30

28

26

–40 –20 0 20 40 60 80

V

= 5V

POS

TEMPERATURE (°C)

Figure 10. Input IP3 vs. Temperature

Rev. 0 | Page 8 of 24

ADL5367

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

110

105

100

T

= +25°C

A

95

90

SUPPLY CURRENT (mA)

85

TA = –40°C

TA = +85°C

85

80

75

70

65

INPUT IP2 (dBm)

TA =–40°C

60

55

TA = +25°C

TA = +85°C

80

30 80 130 180 230 280 330 380 430

IF FREQ UENCY (MHz )

Figure 13. Supply Current vs. IF Frequency

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION LOSS (dB)

6.0

5.5

5.0
30 80 130 180 230 280 330 380 430

= +25°C

T

A

IF FREQ UE NCY (M Hz )

TA = +85°C

TA =–40°C

Figure 14. Power Conversion Loss vs. IF Frequency

40

38

TA = –40°C

36

50

30 80 130 180 230 280 330 380 430

8083-016

IF FREQ UENCY (MHz )

8083-021

Figure 16. Input IP2 vs. IF Frequency

12

11

10

9

8

7

SSB NOISE FIGURE (dB)

6

5

30 80 130 180 230 280 330 380 430

08083-033

IF FREQ UENCY ( M Hz )

08083-010

Figure 17. SSB Noise Figure vs. IF Frequency

34

32

INPUT IP3 (dBm)

30

28

26

30 80 130 180 230 280 330 380 430

IF FREQ UENCY (MHz )

Figure 15. Input IP3 vs. IF Frequency

T

= +25°C

A

TA = +85°C

08083-026

Rev. 0 | Page 9 of 24

ADL5367

–

–

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

10.0

40

9.5

9.0

8.5
TA = +25°C

8.0

7.5

CONVERSION LOSS (dB)

7.0

6.5

6.0

–6 –4 –2 0 2 4 6 8 10

TA = +85°C

TA = –40°C

LO POW E R ( dBm)

Figure 18. Power Conversion Loss vs. LO Power

40

38

TA = –40°C

36

34

32

INPUT IP3 (dBm)

30

28

26

–6 –4 –2 0 2 4 6 8 10

T

TA = +85°C

= +25°C

A

LO POW E R ( dBm)

Figure 19. Input IP3 vs. LO Power

90

85

80

TA = +25°C

TA =–40°C

–50

–60

–70

–80

IF/2 SPURIOUS (dBc)

–90

–100

700 750 800

08083-034

TA = +85°C

900 950 1000 1050 1100 1150 1200

850

RF FREQUENC Y ( MHz )

TA = +25°C

TA =–40°C

8083-020

Figure 21. IF/2 Spurious vs. RF Frequency

40

–45

–50

–55

–60

–65

TA =–40°C

–70

IF/3 SPURIOUS (dBc)

–75

–80

–85

700 750 800 850 900 950 1000 1050 1 100 1150 1200

8083-027

TA = +25°C

RF FREQUENCY ( MHz )

TA = +85°C

08083-040

Figure 22. IF/3 Spurious vs. RF Frequency

75

70

65

INPUT IP2 (dBm)

60

55

50

–6 –4 –2 0 2 4 6 8 10

TA = +85°C

LO POW E R ( dBm)

Figure 20. Input IP2 vs. LO Power

08083-022

Rev. 0 | Page 10 of 24

ADL5367

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

100

80

60

40

PERCENT (%)

20

0

7.2 7.8 8.07.6

7.4 8.2

Figure 23. Conversion Loss Distribution

100

STANDARD DEVIATI ON: 0.18

CONVERSION LOSS (dB)

MEAN: 7.7

36.5

36.0

35.5

35.0

34.5

34.0

33.5

33.0

RESISTANCE (Ω)

32.5

32.0

31.5

31.0

30.5

8083-068

30 80 130 180 230 280 330 380 430

IF FREQUENCY (MHz)

Figure 26. IF Port Return Loss

0

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

CAPACITANCE (pF)

08083-069

80

60

40

PERCENT (%)

20

0

31 37 393533

Figure 24. Input IP3 Distribution

100

90

80

70

60

50

40

PERCENTAGE (%)

30

20

10

0

7.8 8.0 8.2 8.4

Figure 25. SSB Noise Figure Distribution

STANDARD DEVIATION: 0.19

INPUT IP3 (dBm)

STANDARD DEVIATION: 0.05

NOISE FI GURE (dB)

8.6

MEAN: 34.67

MEAN: 8.3

8.8 9.0

08083-067

08083-063

5

10

15

RF RETURN LO S S ( dB)

20

25

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY ( MHz)

Figure 27. RF Port Return Loss, Fixed IF

0

2

4

6

8

10

12

14

LO RETURN L OSS (dB)

16

18

20

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

SELECTED

UNSELECTED

LO FREQUENCY (MHz)

Figure 28. LO Return Loss, Selected and Unselected

08083-013

08083-007

Rev. 0 | Page 11 of 24

ADL5367

A

–

A

–

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

70

20

65

60

TION (dB)

55

50

LO SWITCH ISOL

45

40

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENC Y (M Hz )

TA = +25°C

TA = –40°C

TA = +85°C

Figure 29. LO Switch Isolation vs. RF Frequency

40

–42

–44

–46

–48

TION (dBc)

–50

–52

–54

RF-TO-IF ISOL

–56

–58

–60

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

= +25°C

T

A

RF FREQUENC Y ( MHz )

TA = +85°C

TA =–40°C

Figure 30. RF-to-IF Isolation vs. RF Frequency

0

–25

–30

–35

–40

LO-TO-RF L E AKAGE (dBm)

–45

–50

900 950 1000 1050 1 100 1150 1200 1250 1300 1350 1400

08083-059

TA =–40°C

= +25°C

T

A

LO FREQ UENCY (MHz)

TA = +85°C

8083-032

Figure 32. LO-to-RF Leakage vs. LO Frequency

0

–5

–10

–15

–20

–25

–30

–35

2LO LEAKAGE (dBm)

–40

–45

–50

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

08083-039

LO FREQUE NCY (MHz)

2LO TO RF

2LO TO IF

8083-014

Figure 33. 2LO Leakage vs. LO Frequency

0

–5

–10

–15

–20

LO-TO-IF L EAKAG E (d Bm)

–25

–30

TA = –40°C

= +25°C

T

A

TA = +85°C

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

LO FREQ UE NCY (M Hz )

Figure 31. LO-to-IF Leakage vs. LO Frequency

08083-031

–10

–20

–30

–40

3LO LEAKAG E (dBm)

–50

–60

–70

900 950 1000 1050 1 100 1150 1200 1250 1300 1350 1400

LO FREUQENCY (MHz)

3LO TO IF

3LO TO RF

Figure 34. 3LO Leakage vs. LO Frequency

08083-015

Rev. 0 | Page 12 of 24

ADL5367

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

10

9

8

7

6

5

4

3

CONVERSION LOSS (dB)

2

VGS = 0, 0
VGS = 0, 1

1

VGS = 1, 0
VGS = 1, 1

0

700 750 800 850 900 950 1000 1050 1100 1150 1200

CONVERSION LOSS

NOISE FI GURE

RF FREQUENCY ( M H z)

Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency

40

38

36

34

32

30

28

INPUT IP3 (dBm)

26

24

22

20

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENC Y (M Hz )

Figure 36. Input IP3 vs. RF Frequency

12

11

INPUT IP3

VGS = 0, 0
VGS = 0, 1
VGS = 1, 0
VGS = 1, 1

15

14

13

12

11

10

9

8

SSB NOISE FIGURE (dB)

7

6

5

08083-058

30

25

20

15

10

NOISE FI G URE (dB)

5

0

–30 –25 –20 –15 –10 –5 0 5 10

BLOCKER POW E R ( dBm)

08083-003

Figure 38. SSB Noise Figure vs.10 MHz Offset Blocker Level

140

120

100

80

60

40

SUPPLY CURRENT ( mA)

20

0

600 800 1000 1200 1400 1600 1800

08083-062

BIAS RESISTOR VALUE (Ω)

08083-008

Figure 39. LO Supply Current vs. LO Bias Resistor Value

40

35

10

9

8

7

6

SSB NOISE F IGURE (dBm)

CONVERSION LOSS (dB) AND

5

4

600 800 1000 1200 1400 1600 1800

NOISE FI GURE

CONVERSION LOSS

BIAS RESISTOR VALUE (Ω)

Figure 37. Power Conversion Loss, SSB Noise Figure, and

Input IP3 vs. LO Bias Resistor Value

30

25

20

15

INPUT IP3 (dBm)

10

5

0

08083-009

Rev. 0 | Page 13 of 24

ADL5367

3.3 V PERFORMANCE

VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.

64

62

60

58

56

SUPPLY CURRENT (mA)

54

52

50

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +25°C

RF FREQUENC Y ( MHz)

T

= –40°C

A

TA = +85°C

Figure 40. Supply Current vs. RF Frequency at 3.3 V

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION LOSS (dB)

6.0

5.5

5.0

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +25°C

T

A

RF FREQUENC Y ( M Hz )

TA = +85°C

= –40°C

Figure 41. Power Conversion Loss vs. RF Frequency at 3.3 V

34

32

= –40°C

T

30

A

08083-018

08083-036

85

80

75

70

65

60

INPUT IP2 (dBm)

55

50

45

40

T

= –40°C

A

TA = +25°C

TA = +85°C

700 750 800 850 900 950 1000 1050 1 100 1150 1200

RF FREQUENC Y ( M Hz )

Figure 43. Input IP2 vs. RF Frequency at 3.3 V

10.0

9.5

9.0

8.5

8.0

7.5

7.0

NOISE FI GURE (dB)

6.5

6.0

5.5

5.0
700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

TA = +25°C

TA = –40°C

RF FREQUENC Y ( M Hz )

Figure 44. SSB Noise Figure vs. RF Frequency at 3.3 V

08083-024

8083-064

28

26

INPUT IP3 (dBm)

24

22

20

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

RF FREQUENC Y ( M Hz )

TA = +25°C

08083-029

Figure 42. Input IP3 vs. RF Frequency at 3.3 V

Rev. 0 | Page 14 of 24

ADL5367

UPCONVERSION

TA = 25°C, fIF = 153 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION LOSS (dB)

6.0

5.5

5.0
700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

= –40°C

T

A

TA = +25°C

RF FREQUENC Y (M Hz )

08083-065

Figure 45. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion

34

32

30

T

= –40°C

A

TA = +85°C

TA = +25°C

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION LOSS (dB)

6.0

5.5

5.0
700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

TA = +25°C

T

= –40°C

A

RF FRE QUENCY (MHz)

08083-066

Figure 47. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion

34

32

30

T

= –40°C

A

28

26

INPUT IP3 (dBm)

24

22

20

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENC Y (M Hz )

Figure 46. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion

28

26

INPUT IP3 (dBm)

24

22

20

700 750 800 850 900 950 1000 1050 1100 1150 1200

08083-060

TA = +85°C

RF FREQUENC Y ( M Hz )

TA = +25°C

08083-061

Figure 48. Input IP3 vs. RF Frequency at 3.3 V, Upconversion

Rev. 0 | Page 15 of 24

ADL5367

SPUR TABLES

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.

5 V Performance

VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and
Z

= 50 Ω, unless otherwise noted.

O

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −7.8 −24.6 −35.7 −53.0 −47.4
1 −39.7 0.0 −45.0 −27.5 −53.0 −54.4 −71.8
2 −84.6 −68.8 −77.4 −72.8 −80.2 −80.9 −87.8 −96.8
3 <−100 −78.6 −95.5 −75.9 −97.9 −91.7 <−100 <−100

4

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

9

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

14

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

3.3 V Performance

VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 =
0 V, and Z

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

N

= 50 Ω, unless otherwise noted.

O

0 −12.6 −28.8 −40.6 −43.0 −59.6
1 −40.5 0.0 −42.7 −27.1 −53.2 −50.7 −71.8

2

−78.6 −59.5 −64.8 −68.0 −65.9 −73.0 −75.4 −89.4

3 −93.9 −66.3 −90.1 −63.0 −90.5 −77.8 −96.4 −95.6
4 <−100 <−100 −95.6 −95.5 −97.0 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 −98.9 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

7

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

12

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

Rev. 0 | Page 16 of 24

ADL5367

V

CIRCUIT DESCRIPTION

The ADL5367 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.

The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.

The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.

A block diagram of the device is shown in Figure 49.

VPMX

CMI

20 19 18 17 16

1

IFOP IFON PWDN COMM

ADL5367

15

LOI2

The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.

The IP3 performance can be optimized by adjusting the supply
current with an external resistor. Figure 37 and Figure 39
illustrate how various bias resistors affect the performance with a
5 V supply. Additionally, dc current can be saved by increasing
the resistor. It is permissible to reduce the dc supply voltage to
as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors and excessive dc power
dissipation may result.)

2

RFIN

3

RFCT

4

COMM

5

COMM

VLO3 LGM3 VLO2 LOSW NC

NC = NO CONNECT

BIAS

GENERATOR

6 7 8 9 10

Figure 49. Simplified Schematic

14

13

12

11

VPSW

VGS1

VGS0

LOI1

RF SUBSYSTEM

The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 500 MHz to 1700 MHz.

LO SUBSYSTEM

The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or low-side injection
for RF signals in the 900 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion loss is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.

The ADL5367 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times

08083-051

(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.

The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.

Rev. 0 | Page 17 of 24

ADL5367

The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.

In addition, when operating with supply voltages below 3.6 V,
the ADL5367 has a power-down mode that permits the dc
current to drop to <200 μA.

All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.

Rev. 0 | Page 18 of 24

ADL5367

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5367 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 500 MHz to 1700 MHz and
intermediate frequencies (IF) from dc to 450 MHz. Figure 50
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent non-zero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.

For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP),
must be driven differentially or using a 1:1 ratio transformer for
single ended operation. An 8 pF capacitor is recommended for
the RF output, Pin 2 (RFIN).

IF PORT

The real part of the output impedance is approximately 50 Ω,
as seen in Figure 26, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Ta b l e 3 .

BIAS RESISTOR SELECTION

An external resistor, R
integrated amplifiers at the LO terminals. It is necessary to have
a sufficient amount of current to bias the internal LO amplifier
to optimize dc current vs. optimum IIP3 performance. Figure 37
and Figure 39 provide the reference for the bias resistor selection
when lower power consumption is considered at the expense of
conversion gain and IP3 performance.

, is used to adjust the bias current of the

BIAS LO

MIXER VGS CONTROL DAC

The ADL5367 features two logic control pins, Pin 12 (VGS0)
and Pin 13 (VGS1), that allow programmability for internal
gate-to-source voltages for optimizing mixer performance over
desired frequency bands. The evaluation board defaults both
VGS0 and VGS1 to ground. Power conversion loss, NF, and
IIP3 can be optimized, as shown in Figure 35 and Figure 36.

IF1_OUT

R1

C24

0Ω

10kΩ

ADL5367

10kΩ

10pF10pF

22pF

15

14

13

12

11

22pF

10pF

LO2_IN

+5V

LO1_IN

08082-052

+5V

4.7µF

0.01µF

+5V

RF-IN

10pF

8pF

10pF

+5V

T1

C25

560pF

20

1

2

3

4

5

6 7 8 9 10

560pF

19 18 17 16

BIAS

GENERATOR

R

BIAS LO

Figure 50. Typical Application Circuit

Rev. 0 | Page 19 of 24

ADL5367

EVALUATION BOARD

An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 51. The evaluation board is fabricated using Rogers®
RO3003 material. Tab le 7 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 52 to Figure 55.

IF1_OUT

R1

T1

0Ω

CMI
V

VLO3

R9

C24

560pF

IFOP

IFON

ADL5367

LO2

LGM3

V

C8
10pF

DN
W

P

LOSW

VPOS

COMM

NC

L3
0Ω

LOI2

VPSW

VGS1

VGS0

LOI1

R4
10kΩ

R21
10kΩ

VGS0

C12

22pF

LOSEL

PWR_UP

VGS1

C10

22pF

LO2_IN

C20
10pF

C22
1nF

VPOS

LO1_IN

R22
10kΩ

R23
15kΩ

8082-053

RF-IN

VPOS

C1

8pF

C2
10µF

C5

0.01µFC410pF

C21
10pF

VPOS

10pF

R14
0Ω

VPMX

RFIN

RFCT

COMM

COMM

C6

C25

560pF

1.1kΩ

Figure 51. Evaluation Board Schematic

Rev. 0 | Page 20 of 24

ADL5367

Table 7. Evaluation Board Configuration

Components Description Default Conditions

C2, C6, C8,
C20, C21

C1, C4, C5

T1, R1, C24, C25

C10, C12, R4

R21

C22, L3, R9, R14,
R22, R23, VGS0,
VGS1

Power Supply Decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.

RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.

IF Output Interface. T1 is a 1:1 impedance transformer used to provide
a single-ended IF output interface. Remove R1 for balanced output
operation. C24 and C25 are used to block the dc bias at the IF ports.

LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled
when LOSEL is pulled to logic high.

PWDN Interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised
using the an external logic generator. Grounding the PWDN pin for
nominal operation is allowed. Using the PWDN pin when supply
voltages exceed 3.3 V is not allowed.

Bias Control. R22 and R23 form a voltage divider to provide 3 V for
logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal operation.
R9 sets the bias point for the internal LO buffers. R14 sets the bias point
for the internal IF amplifier.

Rev. 0 | Page 21 of 24

C2 = 10 μF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)

C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 μF (Size 0402)

T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
C24, C25 = 560 pF (Size 0402)

C10, C12 = 22 pF (Size 0402),
R4 = 10 kΩ (Size 0402)

R21 = 10 kΩ (Size 0402)

C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.1 kΩ (Size 0402), R14 = 0 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt

ADL5367

Figure 52. Evaluation Board Top Layer

Figure 53. Evaluation Board Ground Plane, Internal Layer 1

08083-054

08083-056

Figure 54. Evaluation Board Power Plane, Internal Layer 2

08083-055

08083-057

Figure 55. Evaluation Board Bottom Layer

Rev. 0 | Page 22 of 24

ADL5367

C

OUTLINE DIMENSIONS

0.05

0.65

BSC

0.75

0.60

0.50

0.60 MAX

15

16

10

11

20

EXPOSED

PAD

(BOTTOM VIEW)

6

2.60 BSC

FOR PROPE R CONNECTION O F
THE EXPOSE D PAD, REF ER T O
THE PIN CONFIGURATION AND
FUNCTION DE SCRIPTIO NS
SECTION OF THIS DATA SHEET.

N

I

1

P

R

O

T

N

D

C

I

A

I

1

3.20

3.10 SQ

3.00

5

042209-B

5.00

INDI

ATOR

0.90

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP VIEW

0.70

0.65

0.60

0.35

0.28

0.23

COMPLIANTTOJEDEC STANDARDS MO-220- VHHC

4.75

BSC SQ

0.20 REF

0.60 MAX

0.05 MAX

0.01 NOM
COPLANARITY

Figure 56. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-20-5)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Model Temperature Range Package Description

Option

ADL5367ACPZ-R71 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-20-5 1,500
ADL5367-EVALZ1 Evaluation Board 1

1

Z = RoHS Compliant Part.

Ordering
Quantity

Rev. 0 | Page 23 of 24

ADL5367

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08083-0-10/09(0)

Rev. 0 | Page 24 of 24