Datasheet ADL5358 Datasheet (ANALOG DEVICES)

500 MHz to 1700 MHz, Dual-Balanced

Mixer, LO Buffer, IF Amplifier, and RF Balun

FEATURES

RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.3 dB
SSB noise figure of 9.9 dB
SSB noise figure with 5 dBm blocker of 23 dB
Input IP3 of 25.2 dBm
Input P1dB of 10.6 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP

APPLICATIONS

Cellular base station receivers
Transmit observation receivers
Radio link downconverters

GENERAL DESCRIPTION

The ADL5358 uses a highly linear, doubly balanced, passive
mixer core along with integrated RF and local oscillator (LO)
balancing circuitry to allow single-ended operation. The
ADL5358 incorporates the RF baluns, allowing for optimal
performance over a 500 MHz to 1700 MHz RF input frequency
range. Performance is optimized for RF frequencies from 500 MHz
to 1200 MHz using a high-side LO and RF frequencies from
1200 MHz to 1700 MHz using a low-side LO. The balanced
passive mixer arrangement provides good LO-to-RF leakage,
typically better than −20 dBm, and excellent intermodulation
performance. The balanced mixer core also provides extremely
high input linearity, allowing the device to be used in demanding
cellular applications where in-band blocking signals may otherwise
result in the degradation of dynamic performance. A high linearity
IF buffer amplifier follows the passive mixer core to yield a
typical power conversion gain of 8.3 dB and can be used with
a wide range of output impedances.

The ADL5358 provides two switched LO paths that can be used
in TDD applications where it is desirable to ping-pong between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5358 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. Under low voltage operation, an additional logic
pin is provided to power down (<300 µA) the circuit when desired.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ADL5358

FUNCTIONAL BLOCK DIAGRAM

N

M

M

S

G

M

N

O
C

M

M

M

G

M

V

O

D

C

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

O
P
V

S
O
P
V

The ADL5358 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.

Table 1. Passive Mixers

RF Frequency
(MHz)

Single
Mixer

500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

O
N
M

P
O
V
D

Figure 1.

P
O
N
M

N
O
V
D

E

S

L

O

N

P

M

V

ADL5358

S

E
L

O

V

P

D

V

Single Mixer
and IF Amp

G
L
N

C

M

N

C

G
L

N
V
D

Dual Mixer
and IF Amp

LOI2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

LOI1

07885-001

ADL5358

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Performance ........................................................................... 4

3.3 V Performance ........................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

5 V Performance ........................................................................... 7

REVISION HISTORY

11/09—Revision 0: Initial Version

3.3 V Performance ...................................................................... 15

Spurious Performance ............................................................... 16

Circuit Description......................................................................... 17

RF Subsystem .............................................................................. 17

LO Subsystem ............................................................................. 18

Applications Information .............................................................. 19

Basic Connections ...................................................................... 19

IF Port .......................................................................................... 19

Bias Resistor Selection ............................................................... 19

Mixer VGS Control DAC .......................................................... 19

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

Rev. 0 | Page 2 of 24

ADL5358

SPECIFICATIONS

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

Table 2.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 20 dB
Input Impedance 50 Ω
RF Frequency Range 500 1700 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V

LO INTERFACE

LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50 Ω
LO Frequency Range 530 1670 MHz

POWER-DOWN (PWDN) INTERFACE2

PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 μA

Device disabled 70 μA

1

Apply supply voltage from external circuit through choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

Rev. 0 | Page 3 of 24

ADL5358

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7.6 8.3 8.6 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.9 dB
SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 10.6 dBm
LO-to-IF Leakage Unfiltered IF output −33 dBm
LO-to-RF Leakage −31 dBm
RF-to-IF Isolation −43 dBc
IF/2 Spurious −10 dBm input power −72 dBc
IF/3 Spurious −10 dBm input power −79 dBc
IF Channel-to-Channel Isolation 54 dB

POWER SUPPLY

Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current LO supply 170 mA
IF supply 180 mA
Total Quiescent Current 350 mA

= 50 Ω, unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered

= 899.5 MHz, f

f

RF1

= 900.5 MHz, fLO = 1103 MHz,

RF2

each RF tone at −10 dBm

= 900 MHz, f

f

RF1

= 950 MHz, fLO = 1103 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.6 dB

LOAD

23 dB

22 25.2 dBm

57 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 k,
R2 = R5 = 400 , VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.3 dB
Voltage Conversion Gain Z
SSB Noise Figure 8.9 dB
Input Third-Order Intercept (IIP3)

f
each RF tone at −10 dBm

Input Second-Order Intercept (IIP2)

f
each RF tone at −10 dBm

Input 1 dB Compression Point (IP1dB) 6.75 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 200 mA
Total Quiescent Current Device disabled 300 μA

= 50 , unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

= 899.5 MHz, f

RF1

= 950 MHz, f

RF1

= 900.5 MHz, fLO = 1103 MHz,

RF2

= 900 MHz, fLO = 1103 MHz,

RF2

= 200 Ω differential 14.6 dB

LOAD

19.3 dBm

47.2 dBm

Rev. 0 | Page 4 of 24

ADL5358

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
MNOP, MNON, DVOP, DVON Bias 6.0 V
VGS2, VGS1, VGS0, LOSW, PWDN 5.5 V
Internal Power Dissipation 2.2 W
θJA 22°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5358

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

N

M

M

P

E

S

O

G

M

O

N

N

O

P

M

C

M

V

6

5

4

3

3

3

3

3

1

MNIN

2

MNCT

3

COMM

4

VPOS

5

COMM

6

VPOS

7

COMM

DVCT

8
9

DVIN

NOTES

1. NC = NO CONNECT .

2. EXPOSED PAD MUST BE CONNECT E D TO GROUND.

ADL5358

TOP VIEW

(Not to S cal e)

0

1

2

1

1

1

S

M

M

O

G

M

P

V

O

V

D

C

3

1

P
O
V
D

Figure 2. Pin Configuration

G

S

O

L

L

O

N

N

N

C

P

M

M

V

M

2

3

4

1

N
O
V
D

N

1

0

9

8

3

3

2

2

27

LOI2
VGS2

26

VGS1

25

VGS0

24

LOSW

23
22

PWDN

21

VPOS

20

COMM
LOI1

19

5

6

7

8

1

1

1

1

S

E

C

G

L

L

N

O

V

V

P

D

V

D

07885-002

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. This pin must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass this pin to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16,

VPOS Positive Supply Voltage.

21, 30, 36
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. This pin must be ac-coupled.
11 DVGM Diverstiy Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to

VCC using external inductors.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diverstiy Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. This pin must be ac-coupled.
22 PWDN

Connect to Ground for Normal Operation. Connect this pin to 3 V for disable mode when using

VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26 VGS0, VGS1, VGS2 Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. This pin must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON

Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to

VCC using external inductors.
35 MNGM Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
Paddle EPAD Exposed pad must be connected to ground.

Rev. 0 | Page 6 of 24

ADL5358

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

400

= 50 Ω, unless otherwise noted.

O

70

380

360

340

SUPPLY CURRENT (mA)

320

300

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA =–40°C

TA = +25°C

TA = +85°C

RF FREQUENCY (M Hz )

Figure 3. Supply Current vs. RF Frequency

12

11

10

9

8

7

CONVERSION GAIN (dB)

6

TA = +25°C

TA = –40°C

TA = +85°C

65

60

55

TA = +25°C

INPUT IP2 (dBm)

50

45

40

700 750 800 850 900 950 1000 1050 1100 1150 1200

07885-003

RF FREQUENCY ( M Hz )

TA =–40°C

TA = +85°C

07885-006

Figure 6. Input IP2 vs. RF Frequency

14

13

12

11

10

INPUT P1dB (dBm)

9

TA = +85°C

TA = –40°C

TA = +25°C

5

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY (MHz )

Figure 4. Power Conversion Gain vs. RF Frequency

31

29

27

TA = –40°C

25

INPUT IP3 (dBm)

23

21

19

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

RF FREQUENCY ( M Hz )

TA = +25°C

Figure 5. Input IP3 vs. RF Frequency

07885-004

07885-005

Rev. 0 | Page 7 of 24

8

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY ( M Hz )

Figure 7. Input P1dB vs. RF Frequency

14

13

12

11

10

9

SSB NOISE F IGURE (dB)

8

7

6

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +25°C

TA = –40°C

RF FREQUENCY (M Hz )

TA = +85°C

Figure 8. SSB Noise Figure vs. RF Frequency

07885-007

07885-008

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

400

380

360

340

SUPPLY CURRENT (mA)

320

300

–40 –20 –10–30 0 10 20 30 40 50 60 70 80

Figure 9. Supply Current vs. Temperature

10.0

9.5

9.0

8.5

8.0

CONVERSION GAIN (dB)

7.5

4.75V

5.0V

5.25V

= 50 Ω, unless otherwise noted.

O

V

= 5.25V

POS

V

= 5.0V

POS

V

= 4.75V

POS

TEMPERATURE ( °C)

62

61

60

59

V

V

58

57

56

INPUT IP2 (dBm)

55

54

53

52

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

07885-009

= 5.0V

POS

TEMPERATURE (°C)

POS

= 5.25V

V

POS

= 4.75V

07885-012

Figure 12. Input IP2 vs. Temperature

13

12

11

10

INPUT P1dB (dBm)

9

V

POS

= 5.25V

V

= 5.0V

POS

V

= 4.75V

POS

7.0
–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE ( °C)

Figure 10. Power Conversion Gain vs. Temperature

29

28

27

26

25

24

INPUT IP3 (dBm)

23

22

21

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

V

= 5.0V

POS

V

= 5.25V

POS

V

= 4.75V

POS

TEMPERATURE (°C)

Figure 11. Input IP3 vs. Temperature

07885-010

07885-011

8

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE ( °C)

Figure 13. Input P1dB vs. Temperature

12.0

11.5

11.0

= 5.25V

10.5

10.0

9.5

SSB NOISE FIGURE (dB)

9.0

8.5

8.0
–40 –20 0

V

POS

V

V

POS

TEMPERATURE (°C)

POS

= 5.0V

20

= 4.75V

30

40 60–30 –10 10

50 70 80

Figure 14. SSB Noise Figure vs. Temperature

07885-013

07885-014

Rev. 0 | Page 8 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

400

= 50 Ω, unless otherwise noted.

O

70

380

360

340

SUPPLY CURRENT ( mA)

320

300

30 80 130 180 230 280 330 430380

TA = –40°C

TA = +85°C

IF FREQ UENCY (MHz)

Figure 15. Supply Current vs. IF Frequency

11

10

9

8

7

6

CONVERSION G AI N (d B)

5

TA = +25°C

TA = –40°C

TA = +85°C

TA = +25°C

65

60

55

INPUT IP2 (dBm)

50

45

40

30

80

07885-015

TA = +85°C

130 180 230 280 330 380 430

IF FREQ UENCY (MHz)

TA = +25°C

TA = –40°C

07885-018

Figure 18. Input IP2 vs. IF Frequency

13

12

11

10

9

INPUT P1dB (dBm)

8

TA = +25°C

TA = +85°C

TA = –40°C

4

30

130 180 230 280 330 380 430

80

IF FREQUENCY (MHz )

Figure 16. Power Conversion Gain vs. IF Frequency

30

29

28

27

26

25

24

INPUT IP3 (dBm)

23

22

21

20

30

80

TA = +25°C

TA = +85°C

130 180 230 280 330 380 430

IF FREQ UE NCY (MHz)

Figure 17. Input IP3 vs. IF Frequency

07885-016

TA = –40°C

07885-017

7

30

130 180 230 280 330 380 430

80

IF FREQUE NCY (MHz)

07885-019

Figure 19. Input P1dB vs. IF Frequency

14

13

12

11

10

9

SSB NOISE F IGURE (dB)

8

7

6

30

130 180 230 280 330 380 430

80

IF FREQUE NCY ( M Hz )

07885-020

Figure 20. SSB Noise Figure vs. IF Frequency

Rev. 0 | Page 9 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

11.0

10.5

10.0

9.5

9.0

8.5

8.0

7.5

CONVERSION G AI N (d B)

7.0

6.5

6.0
–6 –4 –2 0 2 4 6 8 10

Figure 21. Power Conversion Gain vs. LO Power

30

29

28

27

26

25

24

INPUT IP3 (dBm)

23

22

21

20

–6 –4 –2 0 2 4 6 8 10

TA =–40°C

TA = +25°C

Figure 22. Input IP3 vs. LO Power

64

62

60

58

56

INPUT IP2 (dBm)

54

52

50

–6 –4 –2 0 2 4 6 8 10

TA = –40°C

TA = +25°C

TA = +85°C

Figure 23. Input IP2 vs. LO Power

= 50 Ω, unless otherwise noted.

O

TA =–40°C

TA = +25°C

TA = +85°C

LO POW E R (dBm)

TA = +85°C

LO POW E R (dBm)

LO POWER (dBm)

12.0

11.5

11.0

10.5

10.0

INPUT P1dB (dBm)

9.5

9.0
–6 –4 –2 0 2 4 6 8 10

07885-021

TA = –40°C

TA = +85°C

TA = +25°C

LO POWE R (dBm)

07885-024

Figure 24. Input P1dB vs. LO Power

–60

–65

–70

–75

TA = +25°C

–80

IF/2 SPURIOUS (dBc)

–85

–90

700 750 800 850 900 950 1000 1050 1100 1150 1200

07885-022

TA = +85°C

TA = –40°C

RF FREQUENCY (M Hz )

07885-025

Figure 25. IF/2 Spurious vs. RF Frequency

–65

–67
–69

–71

–73

–75

–77

IF/3 SPURIOUS (dBc)

–79

–81

–83
–85

700 750 800 850 900 950 1000 1050 1100 1150 1200

07885-023

TA = –40°C

RF FREQUENCY (M Hz )

Figure 26. IF/3 Spurious vs. RF Frequency

TA = +25°C

TA = +85°C

07885-026

Rev. 0 | Page 10 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

100

MEAN = 8.47
STANDARD DEVIATION = 0.66%

80

500

400

12

9

60

40

PERCENTAGE (%)

20

0

7.0 7.5 8.0 8.5 9.0 9.5 10.0
CONVERSION G AI N (d B)

Figure 27. Conversion Gain Distribution

100

MEAN = 25.2
STANDARD DEVIATION = 0.71

80

60

40

PERCENTAGE (%)

20

0

1815 21 24 27 3330

INPUT IP3 LO (dBm)

Figure 28. Input IP3 Distribution

100

MEAN = 10.66
STANDARD DEVIATION = 0.96

80

60

40

PERCENTAGE (%)

20

0

7 8 9 10111213

INPUT P1dB (dBm)

Figure 29. Input P1dB Distribution

300

200

RESISTANCE (Ω)

100

0

30 43038033028023018013080

07885-027

IF FREQ UE NCY (MHz)

Figure 30. IF Output Impedance (R Parallel, C Equivalent)

10

12

14

16

18

20

22

24

RF RETURN LO S S (dB)

26

28

30

700 750 800 850 900 950 1000 1050 1100 1150 1200

07885-028

RF FREQUENCY ( M Hz )

Figure 31. RF Return Loss, Fixed IF

8

9

10

11

12

13

14

LO RETURN L OSS (dB)

15

16

17

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

07885-029

SELECTED

UNSELECTED

LO FREQ UENCY ( GHz)

Figure 32. LO Return Loss, Selected and Unselected

6

3

CAPACIT A N CE (pF )

0

–3

07885-030

07885-031

07885-032

Rev. 0 | Page 11 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

65

–24

TA = +25°C

60

55

TA = –40°C

50

LO SWITCH ISOLATION (dB)

45

40

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

RF FREQUENCY (M Hz )

Figure 33. LO Switch Isolation vs. RF Frequency

–20

–25

–30

5

–3

–40

–45

RF-TO-IF ISOLATION (dB)

–50

–55

–60

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

TA = +25°C

TA = –40°C

RF FREQUENCY ( M Hz )

Figure 34. RF-to-IF Isolation vs. RF Frequency

–20

–26

–28

–30

–32

–34

LO-TO - RF LEAKAGE (dBm)

–36

–38

900 95

07885-033

TA = –40°C

TA = +25°C

TA = +85°C

0 1000 1050 1100 1150 1200 1250 1300 1350 1400

LO FREQUE NCY (MHz)

07885-036

Figure 36. LO-to-RF Leakage vs. LO Frequency

0

–5

–10

–15

–20

2XLO LEAKAGE (dBm)

–25

–30

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

07885-034

LO FREQUE NCY (MHz)

2XLO-TO-RF

2XLO-TO-IF

07885-037

Figure 37. 2XLO Leakage vs. LO Frequency

0

–25

–30

–35

–40

LO-TO- IF LEAKAGE ( dBm)

–45

–50

0 1000 1050 1100 1150 1200 1250 1300 1350 1400

90095

TA = +85°C

LO FREQ UE NCY (MHz )

TA = –40°C

TA = +25°C

07885-035

Figure 35. LO-to-IF Leakage vs. LO Frequency

–10

–20

–30

3XLO-TO-RF

–40

–50

3XLO LEAKAGE (dBm)

–60

3XLO-TO-IF

–70

900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400

LO FREQ UENCY ( MHz)

Figure 38. 3XLO Leakage vs. LO Frequency

07885-038

Rev. 0 | Page 12 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

9

= 50 Ω, unless otherwise noted.

O

14

30

8

7

6

5

CONVERSION GAIN (dB)

VGS = 000

4

VGS = 011
VGS = 100
VGS = 110

3

700 120011001000900800750 11501050950850

RF FREQUENCY ( MHz)

13

12

11

10

SSB NOISE F IGURE (dB)

9

8

Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency

for Various VGS Settings

13

12

11

10

9

INPUT P1dB (dB)

8

VGS = 000

7

VGS = 011
VGS = 100
VGS = 110

6

700 120011001000900800750 11501050950850

RF FREQUENCY ( M Hz )

45

40

35

30

25

INPUT IP3 (dB)

20

15

10

Figure 40. Input P1dB and Input IP3 vs. RF Frequency for Various VGS Settings

CONVERSION GAIN AND SSB NOISE FIGURE ( dB)

16

14

12

10

8

6

4

2

600 1600150014001300120011001000900800700

INPUT IP3

NOISE FI G URE

CONVERSION GAIN

LO BIAS RES ISTOR VALUE ( Ω)

32

28

24

20

16

INPUT IP3 (dBm)

12

8

4

Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs.

LO Bias Resistor Value

25

20

15

10

SSB NOISE F IGURE (dB)

5

0

–30 –25 –20 –15 –5–10 501

07885-039

BLOCKER POW E R ( dBm)

0

07885-042

Figure 42. SSB Noise Figure vs. 10 MHz Offset Blocker Level

300

280

260

240

220

200

180

160

SUPPLY CURRENT (mA)

140

120

100

600 1600150014001300120011001000900800700

07885-040

IF RESIS T OR SUPPLY CURRENT

LO RESIS T OR SUPPLY CURRENT

BIAS RESISTOR VALUE (Ω)

07885-043

Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value

18

16

14

12

10

8

6

CONVERSION GAIN AND SSB NOIS E FIGURE (d B)

4

07885-041

600 1600150014001300120011001000900800700

INPUT IP3

NOISE FI GURE

CONVERSION GAIN

IF BIAS RESIS TOR VAL UE ( Ω)

28

24

20

16

12

INPUT IP3 (dBm)

8

4

0

07885-044

Figure 44. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs.

IF Bias Resistor Value

Rev. 0 | Page 13 of 24

ADL5358

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, Z

60

59

= 50 Ω, unless otherwise noted.

O

TA = –40°C

58

57

56

55

54

IF CHANNEL-T O-CHANNEL ISOLATIO N (dB)

53

700 750 800 850 900 950 1000 1050 1100 1150 1200

Figure 45. IF Channel-to-Channel Isolation vs. RF Frequency

TA = +85°C

RF FREQUENCY (M Hz )

TA = +25°C

07885-045

Rev. 0 | Page 14 of 24

ADL5358

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ,
R2 = R5 = 400 Ω, VGS0 = VGS1 = VGS2 = 0 V, Z

220

= 50 Ω, unless otherwise noted.

O

60

215

210

205

200

SUPPLY CURRENT ( mA)

195

190

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = –40°C

TA = +25°C

TA = +85°C

RF FREQUENCY (M Hz )

Figure 46. Supply Current vs. RF Frequency at 3.3 V

11

10

9

TA = +25°C

8

7

CONVERSION GAIN (dB)

6

TA = +85°C

TA = –40°C

55

TA = –40°C

50

45

INPUT IP2 (dBm)

40

35

30

700 750 800 850 900 950 1000 1050 1100 1150 1200

07885-046

TA = +85°C

TA = +25°C

RF FREQUENCY (M Hz )

07885-049

Figure 49. Input IP2 vs. RF Frequency at 3.3 V

10

9

8

7

6

INPUT P1dB (dBm)

5

TA = +25°C

TA = +85°C

TA = –40°C

5

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY (M Hz )

Figure 47. Power Conversion Gain vs. RF Frequency at 3.3 V

26

24

22

20

18

INPUT IP3 (dBm)

TA = +85°C

16

14

12

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA =–40°C

TA = +25°C

RF FREQUENCY (M Hz )

Figure 48. Input IP3 vs. RF Frequency at 3.3 V

07885-047

07885-048

Rev. 0 | Page 15 of 24

4

700 750 800 850 900 950 1000 1050 1100 1150 1200

RF FREQUENCY (MHz )

Figure 50. Input P1dB vs. RF Frequency at 3.3 V

14

13

12

11

TA = +25°C

10

9

8

7

SSB NOISE F IGURE (dB)

6

5

4

700 750 800 850 900 950 1000 1050 1100 1150 1200

TA = +85°C

TA = –40°C

RF FREQUENCY ( M Hz )

Figure 51. SSB Noise Figure vs. RF Frequency at 3.3 V

07885-050

07885-051

ADL5358

SPURIOUS PERFORMANCE

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.

5 V Performance

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ,
R2 = R5 = 1 kΩ, VGS0 = VGS1 = VGS2 = 0 V, and Z

N

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −28.0 −21.5 −59.0 −44.2 −71.2

−52.4 0.0 −70.8 −42.4 −67.8 −65.5 −86.2

1

−74.8 −73.1 −78.2 −90.2 −77.6 <−100 −91.0 <−100

2
3 <−100 <−100 <−100 −91.1 <−100 <−100 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

5

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

6
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

8

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

9
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

12

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

13
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

3.3 V Performance

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 =
R5 = 400 Ω, VGS0 = VGS1 = VG2 = 0 V, and Z

N

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

−33.3 −23.7 −49.1 −41.3 −82.9

0

−46.3 0.0 −64.4 −39.4 −71.2 −73.1 −86.1

1
2 −68.2 −61.5 −78.4 −81.2 −71.8 −94.6 −88.8 <−100

−99.9 −90.6 −95.2 −75.7 <−100 <−100 <−100 <−100

3

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

4
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

7

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

8
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

10

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

11
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

14

= 50 Ω, unless otherwise noted.

O

M

= 50 Ω, unless otherwise noted.

O

M

Rev. 0 | Page 16 of 24

ADL5358

CIRCUIT DESCRIPTION

The ADL5358 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated into
a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.

The RF subsystem consists of integrated, low loss RF baluns,
passive MOSFET mixers, sum termination networks, and IF
amplifiers. The LO subsystem consists of an SPDT-terminated FET
switch and two multistage limiting LO amplifiers. The purpose of
the LO subsystem is to provide a large, fixed amplitude balanced
signal to drive the mixer independent of the level of the LO input.

A simplified schematic of the device is shown in Figure 52.

N

M

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

M

S

G

O
P
V

S
O
P
V

M

N

O
C

M

M

M

G

M

V

O

D

C

P
O
N
M

P
O
V
D

E

O

L

N

N

M

M

E

N

L

O

V

V

D

D

S
O
P
V

ADL5358

S
O
P
V

G
L
N

C

M

N

LOI2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

LOI1

C

G
L

N
V
D

Figure 52. Simplified Schematic

RF SUBSYSTEM

The single-ended, 50  RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can be
dc connected, it is recommended that a blocking capacitor be used
to avoid running excessive dc current through the part. The RF
balun can easily support an RF input frequency range of 500 MHz
to 1700 MHz.

Rev. 0 | Page 17 of 24

07885-001

The resulting balanced RF signal is applied to a passive mixer that
commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss of
the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum network
between the IF amplifier and the mixer and in the feedback
elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that
is required to achieve the overall performance. The balanced open­collector output of the IF amplifier, with impedance modified
by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or an analog-to-digital input while providing optimum second­order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 . If
operation in a 50  system is desired, the output can be
transformed to 50  by using a 4:1 transformer.

The intermodulation performance of the design is generally limited
by the IF amplifier. The IP3 performance can be optimized by
adjusting the IF current with an external resistor.

Figure 41,
Figure 43, and Figure 44 illustrate how various IF and LO bias
resistors affect the performance with a 5 V supply. Additionally,
dc current can be saved by increasing either or both resistors. It
is permissible to reduce the dc supply voltage to as low as 3.3 V,
further reducing the dissipated power of the part. No performance
enhancement is obtained by reducing the value of these resistors,
and excessive dc power dissipation may result.

ADL5358

LO SUBSYSTEM

The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or low-side injection
for RF signals in the 1200 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion gain is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.

The ADL5358 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.

The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier. This
results in consistent performance over a range of LO input power.
Optimum performance is achieved from −6 dBm to +10 dBm,
but the circuit continues to function at considerably lower levels
of LO input power.

The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the LO
amplifier by raising the value of the external bias control resistor.
For dc current critical applications, the LO chain can operate
with a supply voltage as low as 3.3 V, resulting in substantial
dc power savings.

In addition, when operating with supply voltages below 3.6 V, the
ADL5358 has a power-down mode that permits the dc current
to drop to <300 µA.

The logic inputs are designed to work with any logic family that
provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.

Rev. 0 | Page 18 of 24

ADL5358

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5358 mixer is designed to downconvert radio
frequencies (RF) primarily between 500 MHz and 1700 MHz to
lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 53 depicts the basic connections of the mixer.
It is recommended to ac-couple the RF and LO input ports to
prevent non-zero dc voltages from damaging the RF balun or
LO input circuit. The RFIN matching network consists of a
series 8 pF capacitor to provide the optimized RF input return
loss for the desired frequency band.

IF PORT

The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.

The real part of the output impedance is approximately 200 Ω,
as seen in Figure 30, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the power
conversion gain, as shown in Ta ble 3 . When a 50 Ω output
impedance is needed, use a 4:1 impedance transformer, as shown
in Figure 53.

BIAS RESISTOR SELECTION

The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5)
are used to adjust the bias current of the integrated amplifiers at the
IF and LO terminals. It is necessary to have a sufficient amount
of current to bias both the internal IF and LO amplifiers to optimize
dc current vs. optimum IIP3 performance. Figure 41, Figure 43,
and Figure 44 provide the reference for the bias resistor selection
when lower power consumption is preferred at the expense of
conversion gain and IP3 performance.

MIXER VGS CONTROL DAC

The ADL5358 features three logic control pins, VGS0 (Pin 24),
VGS1 (Pin 25), and VGS2 (Pin 26), that allow programmability for
internal gate-to-source voltages for optimizing mixer performance
over desired frequency bands. The evaluation board defaults
VGS0, VGS1, and VGS2 to ground. Power conversion gain, NF,
IIP3, and input P1dB can be optimized, as shown in Figure 39
and Figure 40.

Rev. 0 | Page 19 of 24

ADL5358

MAIN_IN

C9

Z1 Z2

C3

C2

VCC

1

2

3

4

5

MAIN_OUTN

C19 C17

C22

R1

36 35 34 33 32 31 30 29 28

C33

C8 C21

L1

C27

R10

VCC

C32

T1

L2

R3

MAIN_OUTP

C25 C18

VCC

R2

R12

R7

R14
R11

C16

R16

C34

R17

LO2

VCC

27

26

R13

25

R8

24

R15

23

DIV_IN

VCC

C6 C7

C11

Z3 Z4

GND

VCC

+

C10

6

7

8

9

10 11 12 13 14 15 16 17 18

VCC

C23

R4

C20

DIV_OUTP DIV_OUTN

C30 C31

VCC

R6

L5

C1 C12

C28

R9

L4

C29

T2

ADL5358

VCC

C24 C13

22

21

C26

20

19

C14

R5

C15

LO1

VCC

R19

07885-153

Figure 53. Typical Application Circuit

Rev. 0 | Page 20 of 24

ADL5358

EVALUATION BOARD

An evaluation board is available for the family of double
balanced mixers. The standard evaluation board schematic is
shown in Figure 54. The evaluation board is fabricated using
Rogers® RO3003 material.

Tabl e 7 describes the various configuration options of the
evaluation board. Evaluation board layout is shown in Figure 55
and Figure 56.

MAIN_IN

DIV_IN

C9

Z1 Z2

VCC

C11

Z3 Z4

C3 C2

C6 C7

VCC

+

GND

C10

MAIN_OUTN

C22

VCC

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

VCC

C23

R10

C33

C19 C17

S
O
P
V

C8 C21

L1

R1

M

M

G

M

N

O
C

M

C27

VCC

N
O
N
M

T1

L2

R3

P
O
N
M

ADL5358

TOP VIEW

(Not to Scale)

S
O
P
V

M

G

O

V

C

D

R4

L5

M

M

N

P

O

O

V

V

D

D

VCC

R6

L4

S
O
P
V

S
O
P
V

MAIN_OUTP

C18

G
L
N

M

G
L
V
D

C32

C25

E
L
N

M

E
L
V
D

C24 C13

VCC

C
N

C
N

VCC

R2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

R5

LOI2

LOI1

C14

C26

R13

C16

R12

R16

R7

C34

R8

R17

R14
R11

R15

R19

VCC

C15

LO1

LO2

VCC

C1 C12

C28

C20

DIV_OUTP DIV_OUTN

C30 C31

R9

Figure 54. Evaluation Board Schematic

C29

T2

07885-154

Rev. 0 | Page 21 of 24

ADL5358

Table 7. Evaluation Board Configuration

Components Description Default Conditions

C1, C8, C10, C12,
C13, C15, C18,
C21, C22, C23,
C24, C25, C26

Z1 to Z4, C2, C3,
C6, C7, C9, C11

T1, T2, C17, C19,
C20, C27 to C33,
L1, L2, L4, L5,
R3, R6, R9, R10

C14, C16,
R15, LOSW

R19, PWDN

R1, R2, R4, R5, R7,
R8, R11 to
R14, R16, R17, C34

Power Supply Decoupling. Nominal supply decoupling consists of a

0.01 μF capacitor to ground in parallel with 10 pF capacitors to
ground positioned as close to the device as possible.

RF Main and Diversity Input Interface. Main and diversity input
channels are ac-coupled through C9 and C11. Z1 to Z4 provide
additional component placement for external matching/filter
networks. C2, C3, C6, and C7 provide bypassing for the center taps
of the main and diversity on-chip input baluns.

IF Main and Diversity Output Interface. The open collector IF output
interfaces are biased through pull-up choke inductors L1, L2, L4, and
L5, with R3 and R6 available for additional supply bypassing. T1 and
T2 are 4:1 impedance transformers used to provide a single-ended IF
output interface with C27 and C28 providing center-tap bypassing.
C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled
output interface. Remove R9 and R10 for balanced output operation.

LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2
local oscillator inputs. LOSW selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled
when the LOSW jumper is removed. Jumper can be removed to
allow LOSW interface to be exercised using an external logic generator.

PWDN Interface. When the PWDN 2-pin shunt is inserted, the
ADL5358 is powered down. When R19 is open, it pulls the PWDN
logic low and enables the device. Jumper can be removed to allow
PWDN interface to be exercised using an external logic generator.
Grounding the PWDN pin is allowed during nominal operation but
is not permitted when supply voltages exceed 3.3 V.

Bias Control. R16 and R17 form a voltage divider to provide a 3 V for
logic control, bypassed to ground through C34. R7, R8, R11, R12, R13,
and R14 provide resistor programmability of VGS0, VGS1, and VGS2.
Typically, these nodes can be hardwired for nominal operation.
Grounding these pins is allowed for nominal operation. R2 and R5 set
the bias point for the internal LO buffers. R1 and R4 set the bias point
for the internal IF amplifiers.

C1, C8, C12, C21 = 150 pF (Size 0402),
C10 = 4.7 μF (Size 3216),
C13, C15, C18 = 0.1 μF (Size 0402)
C22, C23, C24, C25, C26 = 10 pF (Size 0402)

Z1, Z3 = open (Size 0402),
Z2, Z4 = open (Size 0402),
C2, C7 = 10 pF (Size 0402),
C3, C6 = 0.01 μF (Size 0402),
C9, C11 = 8 pF (Size 0402)

T1, T2 = TC4-1T+ (Mini-Circuits),
C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402),
C27, C28 = 150 pF (Size 0402),
L1, L2, L4, L5 = 330 nH (Size 0805),
R3, R6, R9, R10 = 0 Ω (Size 0402)

C14, C16 = 10 pF (Size 0402),
R15 = 10 kΩ (Size 0402),
LOSW = 2-pin shunt

R19 = 10 kΩ (Size 0402),
PWDN = 2-pin shunt

R1, R4 = 1.3 kΩ (Size 0402),
R2, R5 = 1 kΩ (Size 0402),
R7, R8, R11 = 0 Ω (Size 0402),
R12, R13, R14 = open (Size 0402),
R16 = 10 kΩ (Size 0402),
R17 = 15 kΩ (Size 0402),
C34 = 1 nF (Size 0402)

Figure 55. Evaluation Board Top Layer

07885-056

Figure 56. Evaluation Board Bottom Layer

07885-057

Rev. 0 | Page 22 of 24

ADL5358

OUTLINE DIMENSIONS

6.00

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.28

0.23

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM
COPLANARITY

0.60 MAX

0.50
BSC

0.75

0.60

0.50

0.08

Figure 57. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6mm × 6 mm Body, Very Thin Quad (CP-36-1)

Dimensions shown in millimeters

0.60 MAX

28

27

EXPOSED

(BOTTOM VIEW)

19

18

36

1

PAD

9

10

4.00
REF

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

PIN 1
INDICATOR

3.85

3.70 SQ

3.55

0.20 MIN

050808-D

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADL5358ACPZ-R21 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1
ADL5358ACPZ-R71 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1
ADL5358-EVALZ1 Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

ADL5358

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07885-0-11/09(0)

Rev. 0 | Page 24 of 24