Datasheet ADL5356 Datasheet (ANALOG DEVICES)

1200 MHz to 2500 MHz, Dual-Balanced

Mixer, LO Buffer, IF Amplifier, and RF Balun

FEATURES

RF frequency range of 1200 MHz to 2500 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.2 dB
SSB noise figure of 9.9 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 31 dBm
Input P1dB of 11 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP

APPLICATIONS

Cellular base station receivers
Transmit observation receivers
Radio link downconverters

GENERAL DESCRIPTION

The ADL5356 uses a highly linear, doubly balanced, passive mixer
core along with integrated RF and local oscillator (LO) balancing
circuitry to allow single-ended operation. The ADL5356
incorporates the RF baluns, allowing for optimal performance over
a 1200 MHz to 2500 MHz RF input frequency range. Performance
is optimized for RF frequencies from 1700 MHz to 2500 MHz
using a low-side LO and RF frequencies from 1200 MHz to
1700 MHz using a high-side LO. The balanced passive mixer
arrangement provides good LO-to-RF leakage, typically better
than −35 dBm, and excellent intermodulation performance. The
balanced mixer core also provides extremely high input linearity,
allowing the device to be used in demanding cellular applications
where in-band blocking signals may otherwise result in the
degradation of dynamic performance. A high linearity IF buffer
amplifier follows the passive mixer core to yield a typical power
conversion gain of 8.2 dB and can be used with a wide range of
output impedances.

The ADL5356 provides two switched LO paths that can be used
in TDD applications where it is desirable to ping-pong between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5356 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. Under low voltage operation, an additional logic
pin is provided to power down (<300 µA) the circuit when desired.

ADL5356

FUNCTIONAL BLOCK DIAGRAM

N

M

M

S

G

M

N

O
C

M

M

M

G

M

V

O

D

C

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

O
P
V

36 35 34 33 32 31 30 29 28

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

S
O
P
V

The ADL5356 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.

Table 1. Passive Mixers

RF Frequency
(MHz)

Single
Mixer

500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356

P

O

O

N

N
M

M

P

N

O

O

V

V

D

D

Figure 1.

Single Mixer
and IF Amp

E
L
N

M

ADL5356

E
L
V
D

G

S

L

O

N

P
V

S
O
P
V

C

M

N

27

LOI2

26

VGS2

25

VGS1

24

VGS0

23

LOSW

22

PWDN

21

VPOS

20

COMM

19

LOI1

C

G
L

N
V
D

Dual Mixer
and IF Amp

07883-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADL5356

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Performance ........................................................................... 4

3.3 V Performance ........................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

5 V Performance ........................................................................... 7

3.3 V Performance ...................................................................... 15

Spur Tables .................................................................................. 16

Circuit Description......................................................................... 17

RF Subsystem .............................................................................. 17

LO Subsystem ............................................................................. 18

Applications Information .............................................................. 19

Basic Connections ...................................................................... 19

IF Port .......................................................................................... 19

Bias Resistor Selection ............................................................... 19

Mixer VGS Control DAC .......................................................... 19

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5356

SPECIFICATIONS

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 =
R5 = 1 k, Z

Table 2.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 15 dB
Input Impedance 50 Ω
RF Frequency Range 1200 2500 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V

LO INTERFACE

LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50 Ω
LO Frequency Range 1230 2470 MHz

POWER-DOWN (PWDN) INTERFACE2

PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 μA

Device disabled 70 μA

1

Apply supply voltage from external circuit through choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

Rev. 0 | Page 3 of 24

ADL5356

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7.5 8.2 8.5 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.9 dB
SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 11 dBm
LO-to-IF Leakage Unfiltered IF output −24 dBm
LO-to-RF Leakage −35 dBm
RF-to-IF Isolation −33 dBc
IF/2 Spurious −10 dBm input power −75 dBc
IF/3 Spurious −10 dBm input power −73 dBc
IF Channel-to-Channel Isolation 50 dB

POWER SUPPLY

Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current LO supply 170 mA
IF supply 180 mA
Total Quiescent Current VS = 5 V 350 mA

= 50 Ω, unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered

= 1899.5 MHz, f

f

RF1

RF2

each RF tone at −10 dBm

= 1900 MHz, f

f

RF1

= 1950 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.5 dB

LOAD

= 1900.5 MHz, fLO = 1697 MHz,

21 dB

25 31 dBm

50 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 k, R2 =
R5 = 400 , VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.3 dB
Voltage Conversion Gain Z
SSB Noise Figure 8.9 dB
Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 7 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 200 mA
Total Quiescent Current Device disabled 300 μA

= 50 , unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

= 1899.5 MHz, f

f

RF1

RF2

LOAD

= 1900.5 MHz, fLO = 1697 MHz,

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.6 dB

21.2 dBm

48 dBm

Rev. 0 | Page 4 of 24

ADL5356

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
MNOP, MNON, DVOP, DVON Bias 6.0 V
VGS2,VGS1,VGS0, LOSW, PWDN 5.5 V
Internal Power Dissipation 2.2 W
θJA 22°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5356

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

N

M

M

P

E

S

O

G

M

O

N

N

O

P

M

C

M

V

6

5

4

3

3

3

3

3

1

MNIN

2

MNCT

3

COMM

4

VPOS

5

COMM

6

VPOS

7

COMM

DVCT

8
9

DVIN

NOTES

12. NC = NO CONNECT .
. EXPOSED P AD M US T BE CONNECTED T O GROUND.

ADL5356

TOP VIEW

(Not to S cale)

0

1

2

1

1

1

S

M

M

O

G

M

P

V

O

V

D

C

3

1

P
O
V
D

Figure 2. Pin Configuration

G

S

O

L

L

O

N

N

N

C

P

M

M

V

M

2

3

4

1

N
O
V
D

N

1

0

9

8

3

3

2

2

27

LOI2
VGS2

26

VGS1

25

VGS0

24

LOSW

23
22

PWDN

21

VPOS

20

COMM
LOI1

19

5

6

7

8

1

1

1

1

S

E

C

G

L

L

N

O

V

V

P

D

V

D

7883-002

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16,

VPOS Positive Supply Voltage.

21, 30, 36
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
11 DVGM Diverstiy Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to

VCC using external inductors.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diverstiy Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22 PWDN

Connect to Ground for Normal Operation. Connect pin to 3 V for disable mode when using

VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26 VGS0, VGS1, VGS2 Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON

Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to

VCC using external inductors.
35 MNGM Main Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
Paddle EPAD Exposed pad must be connected to ground.

Rev. 0 | Page 6 of 24

ADL5356

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

61

380

TA = –40°C

360

TA = +25°C

340

SUPPLY CURRENT (mA)

320

300

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

RF FREQUENCY (M Hz )

Figure 3. Supply Current vs. RF Frequency

11

10

TA = –40°C

9

TA = +25°C

8

7

CONVERSION GAIN (dB)

6

TA = +85°C

59

57

55

INPUT IP2 (dBm)

53

51

49

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

7883-003

TA = +25°C

TA = +85°C

RF FREQUENCY ( MHz)

TA = –40°C

7883-006

Figure 6. Input IP2 vs. RF Frequency

13.0

12.5

12.0

TA = +85°C

11.5

11.0

10.5

INPUT P1dB (dBm)

10.0

9.5

TA = –40°C

TA = +25°C

5
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY (MHz )

Figure 4. Power Conversion Gain vs. RF Frequency

45

40

TA = –40°C

35

30

INPUT IP3 (dBm)

25

20

15

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

RF FREQUENCY ( M Hz )

Figure 5 .Input IP3 vs. RF Frequency

TA = +25°C

7883-004

7883-005

Rev. 0 | Page 7 of 24

9.0
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY ( M Hz )

Figure 7. Input P1dB vs. RF Frequency

14

13

12

11

10

9

8

SSB NOISE F IGURE (dB)

7

6

5

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +25°C

TA = –40°C

RF FREQUENCY (M Hz )

TA = +85°C

Figure 8. SSB Noise Figure vs. RF Frequency

7883-007

7883-008

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

V

= 5.25V

380

360

340

SUPPLY CURRENT (mA)

320

300

–40 –20 –10–30 0 10 20 30 40 50 60 70 80

POS

V

= 5.00V

POS

V

= 4.75V

POS

TEMPERATURE ( °C)

Figure 9. Supply Current vs. Temperature

10.0

9.5

9.0

4.75V

5.00V

5.25V

07883-009

58

57

56

55

54

53

INPUT IP2 (dBm)

52

51

50

49

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE ( °C)

V

= 5.25V

POS

V

= 5.0V

POS

V

= 4.75V

POS

Figure 12. Input IP2 vs. Temperature

14

13

V

= 5.25V

12

POS

V

= 5.0V

POS

07883-012

9.5

8.0

CONVERSION GAIN (dB)

7.5

7.0
–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE (°C)

Figure 10. Power Conversion Gain vs. Temperature

40

38

36

V

= 5.25V

34

32

30

INPUT IP3 (dBm)

28

26

24

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

= 5.0V

V

POS

POS

V

= 4.75V

POS

TEMPERATURE (°C)

Figure 11. Input IP3 vs. Temperature

11

10

INPUT P1dB (dBm)

9

8

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

07883-010

V

= 4.75V

POS

TEMPERATURE ( °C)

07883-013

Figure 13. Input P1dB vs. Temperature

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

SSB NOISE FIGURE (dB)

8.0

7.5

7.0
–40 –20 0

07883-011

= 5.25V

V

POS

V

POS

V

= 4.75V

= 5.0V

TEMPERATURE (°C)

POS

20

30

40 60–30 –10 10

50 70 80

07883-014

Figure 14. SSB Noise Figure vs. Temperature

Rev. 0 | Page 8 of 24

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

70

380

360

340

SUPPLY CURRENT ( mA)

320

300

30 80 130 180 230 280 330 430380

TA =–40°C

TA = +85°C

IF FREQUENCY (MHz)

Figure 15. Supply Current vs. IF Frequency

10

9

8

7

6

5

4

3

CONVERSION G AI N (d B)

2

1

0

30

TA = +25°C

TA = +85°C

130 180 230 280 330 380 430

80

IF FREQUE NCY ( M Hz )

Figure 16. Power Conversion Gain vs. IF Frequency

40

35

30

25

20

15

INPUT IP3 (dBm)

10

5

0

30

TA = +25°C

TA = +85°C

130 180 230 280 330 380 4 30

80

IF FREQUENCY (MHz)

Figure 17. Input IP3 vs. IF Frequency

TA = +25°C

TA = –40°C

TA = –40°C

65

60

55

INPUT IP2 (dBm)

50

45

40

30

80

7883-015

TA = +85°C

130 180 230 280 330 380 430

IF FREQ UE NCY (MHz )

TA = +25°C

TA = –40°C

07883-018

Figure 18. Input IP2 vs. IF Frequency

14

13

TA = +85°C

12

11

TA = +25°C

10

INPUT P1dB (dBm)

9

8

30

07883-016

130 180 230 280 330 380 430

80

TA = –40°C

IF FREQUENCY (MHz)

07883-019

Figure 19. Input P1dB vs. IF Frequency

14

13

12

11

10

9

SSB NOISE F IGURE (dB)

8

7

6

30

07883-017

130 180 230 280 330 380 430

80

IF FREQUENCY (MHz )

07883-020

Figure 20. SSB Noise Figure vs. IF Frequency

Rev. 0 | Page 9 of 24

ADL5356

–

–

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

11

10

TA = –40°C

9

8

7

CONVERSION GAIN (dB)

6

5

–6 –4 –2 0 2 4 6 8 10

TA = +25°C

TA = +85°C

LO POW E R (dBm)

7883-021

Figure 21. Power Conversion Gain vs. LO Power

40

38

TA = –40°C

36

34

32

30

28

INPUT IP3 (dBm)

26

24

22

20

–6 –4 –2 0 2 4 6 8 10

TA = +25°C

TA = +85°C

LO POW E R (dBm)

7883-022

Figure 22. Input IP3 vs. LO Power

65

63

61

59

57

55

53

INPUT IP2 (dBm)

51

49

47

45

–6 –4 –2 0 2 4 6 8 10

TA = +25°C

LO POWER (dBm)

TA = –40°C

TA = +85°C

07883-023

Figure 23. Input IP2 vs. LO Power

11.8

11.6

11.4

11.2

11.0

10.8

INPUT P1dB (dB)

10.6

10.4

10.2

10.0

TA = +85°C

TA = +25°C

TA = –40°C

–6 –4 –2 0 2 4 6 8 10

LO POWE R (dBm)

Figure 24. Input P1dB vs. LO Power

55

–60

–65

–70

–75

IF/2 SPURIOUS (dBc)

TA = +85°C

–80

–85

1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200

TA = –40°C

TA = +25°C

RF FREQUENCY (M Hz )

Figure 25. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm

65

–66
–67

–68

–69

–70

–71

IF/3 SPURIOUS (dBc)

–72

–73

–74
–75

1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200

TA = –40°C

RF FREQUENCY (M Hz )

TA = +85°C

TA = +25°C

Figure 26. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm

7883-024

7883-025

7883-026

Rev. 0 | Page 10 of 24

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

100

80

MEAN = 8.26
SD = 0.31%

500 10

400

8

60

40

PERCENTAGE (%)

20

0

7.6 7.8 8.0 8.2 8.4 8.6 8.8
CONVERSION GAIN (dB)

Figure 27. Conversion Gain Distribution

100

MEAN = 31.67
SD = 0.35%

80

60

40

PERCENTAGE (%)

20

0

2520 30 35 40 45

INPUT IP3 LO (dBm)

Figure 28. Input IP3 Distribution

100

MEAN = 11.37
SD = 0.49%

80

300

200

RESISTANCE (Ω)

100

0

30 80 130 180 230

07883-027

IF FREQUENCY (MHz)

280 330 380 430

6

4

CAPACITANCE (pF)

2

0

07883-055

Figure 30. IF Output Impedance (R Parallel C Equivalent)

0

5

10

15

20

RF PORT RETURN LOSS (dB)

25

30

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

07883-028

RF FRE QUENCY (MHz)

07883-031

Figure 31. RF Port Return Loss, Fixed IF

0

5

60

40

PERCENTAGE (%)

20

0

10 11 12 13

INPUT P1dB (dBm)

Figure 29. Input P1dB Distribution

07883-029

10

SELECTED

15

LO RETURN L OSS (dB)

20

25

1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00

UNSELECTED

LO FREQ UENCY ( GHz)

Figure 32. LO Return Loss, Selected and Unselected

7883-032

Rev. 0 | Page 11 of 24

ADL5356

–

–

–

–

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

LO-TO - RF LEAKAGE (dBm)

–20

–25

–30

–35

–40

–45

15

TA = –40°C

TA = +25°C

TA = +85°C

60

TA =–40°C

50

40

30

20

LO SWITCH ISOLATION (dB)

10

TA = +25°C

TA = +85°C

0
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY (M Hz )

Figure 33. LO Switch Isolation vs. RF Frequency

26

28

30

32

34

36

RF-TO-IF ISOLATION (dB)

38

40

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

TA = +25°C

TA = –40°C

RF FREQUENCY ( M Hz )

Figure 34. RF-to-IF Isolation vs. RF Frequency

10

–15

–50

1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000

7883-033

LO FREQUE NCY (MHz)

07883-036

Figure 36. LO-to-RF Leakage vs. LO Frequency

16

–18

–20

–22

–24

–26

2XLO LEAKAGE (dBm)

–28

–30

7883-034

1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000

2XLO-TO-IF

2XLO-TO-RF

LO FREQUE NCY (MHz)

07883-037

Figure 37. 2XLO Leakage vs. LO Frequency

35

–40

–20

–25

–30

LO-TO- IF LEAKAGE ( dBm)

–35

–40

1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000

TA = +25°C

LO FREQUENCY (MHz)

TA = –40°C

TA = +85°C

Figure 35. LO-to-IF Leakage vs. LO Frequency

07883-035

–45

–50

–55

–60

3XLO LEAKAGE (dBm)

–65

–70

1500 1550 16501600 1750 18001700 2000195019001850

3XLO-TO-RF

3XLO-TO-IF

LO FREQUE NCY ( M Hz )

Figure 38. 3XLO Leakage vs. LO Frequency

07883-038

Rev. 0 | Page 12 of 24

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

10

18

30

9

8

7

6

CONVERSION GAIN (dB)

VGS = 000

5

VGS = 011
VGS = 100
VGS = 110

4

1700 220021002000190018001750 2150205019501850

RF FREQUENCY ( MHz)

16

14

12

10

SSB NOISE F IGURE (dB)

8

6

07883-039

Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency

for Various VGS Settings

20

18

16

14

12

INPUT P1dB (dB)

10

VGS = 000

8

VGS = 011
VGS = 100
VGS = 110

6
1700 220021002000190018001750 2150205019501850

RF FREQUENCY ( M Hz )

32

30

28

26

24

INPUT IP3 (dB)

22

20

18

7883-040

Figure 40. Input IP3 and Input P1dB vs. RF Frequency for Various VGS Settings

13

12

INPUT IP3

35

30

25

20

15

10

SSB NOISE F IGURE (dB)

5

0

–30 –25 –20 –15 –5–10 501

BLOCKER POW E R ( dBm)

0

Figure 42. SSB Noise Figure vs. 10 MHz Offset Blocker Level

350

300

IF RESIS T OR SUPPLY CURRENT

LO RESIS T OR SUPPLY CURRENT

BIAS RESISTOR VALUE (Ω)

SUPPLY CURRENT (mA)

250

200

150

100

50

0

600 1600150014001300120011001000900800700

Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value

13

INPUT IP3

12

35

30

7883-042

7883-043

11

NOISE FI GURE

CONVERSION GAIN

LO BIAS RESIS T OR VALUE ( Ω)

CONVERSION GAIN AND SSB NOIS E FIGURE (d B)

10

9

8

7

6

600 1600150014001300120011001000900800700

Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs.

LO Bias Resistor Value

25

20

15

INPUT IP3 (dBm)

10

5

0

7883-041

Rev. 0 | Page 13 of 24

11

NOISE FI G URE

CONVERSION GAIN

IF BIAS RES ISTOR VALUE ( Ω)

CONVERSION GAIN AND SSB NOIS E FIGURE (d B)

10

9

8

7

6

600 1600150014001300120011001000900800700

Figure 44. Power Conversion Gain, Noise Figure, and Input IP3 vs.

IF Bias Resistor Value

25

20

15

INPUT IP3 (dBm)

10

5

0

7883-044

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

54

53

52

51

50

49

48

47

IF CHANNEL-T O-CHANNEL ISOLATIO N (dB)

46

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

Figure 45. IF Channel-to-Channel Isolation vs. RF Frequency

TA =–40°C

RF FREQUENCY (M Hz )

TA = +85°C

TA = +25°C

7883-051

Rev. 0 | Page 14 of 24

ADL5356

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ,
R2 = R5 = 400 Ω, Z

215

210

205

200

SUPPLY CURRENT (mA)

195

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

TA =–40°C

TA = +25°C

TA = +85°C

INPUT IP2 (dBm)

70

65

60

55

50

45

40

35

TA = –40°C

TA = +85°C

TA = +25°C

190

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY (M Hz )

Figure 46. Supply Current vs. RF Frequency at 3.3 V

11

10

9

8

7

6

CONVERSION GAIN (dB)

5

4
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = –40°C

TA = +25°C

TA = +85°C

RF FREQUENCY ( M Hz )

Figure 47. Power Conversion Gain vs. RF Frequency at 3.3 V

30

28

26

24

22

20

18

INPUT IP3 (dBm)

TA = +25°C

16

14

12

10

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

RF FREQUENCY (M Hz )

TA = –40°C

Figure 48. Input IP3 vs. RF Frequency at 3.3 V

30

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

7883-045

RF FREQUENCY (M Hz )

7883-048

Figure 49. Input IP2 vs. RF Frequency at 3.3 V

14

12

10

8

6

INPUT P1dB (dBm)

4

2

0

7883-046

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = –40°C

RF FREQUENCY (M Hz )

TA = +25°C

TA = +85°C

7883-049

Figure 50. Input P1dB vs. RF Frequency at 3.3 V

14

12

10

8

TA = +25°C

6

SSB NOISE F IGURE (dB)

4

2

7883-047

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY (M Hz )

TA = +85°C

TA = –40°C

7883-050

Figure 51. SSB Noise Figure vs. RF Frequency at 3.3 V

Rev. 0 | Page 15 of 24

ADL5356

SPUR TABLES

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.

5 V Performance

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, VGS0 = VGS1 = VGS2 = 0 V,
and Z

= 50 Ω, unless otherwise noted.

O

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −21.6 −20.2 −64.4
1 −40.7 0.00 −72.7 −45.9 −69.6
2 −70.5 −91.0 −74.4 −82.9 −86.4 <−100
3 <−100 <−100 <−100 −79.3 −96.5 <−100

4

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

5 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100

9

<−100 <−100 <−100 <−100 <−100 <−100

10 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100

14

<−100 <−100

15 <−100

3.3 V Performance

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 =
R5 = 400 Ω, VGS0 = VGS1 = VG2 = 0 V, and Z

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −9.84 −20.31 −43.05 −40.75 −64.36
1 −49.63 0.00 −47.95 −37.36 −53.08 −57.08 −74.07

2

−74.64 −56.52 −57.35 −64.17 −80.85 −91.01 −85.58 <−100

3 <−100 −88.31 −98.10 −62.72 <−100 −91.46 <−100 <−100
4 <−100 <−100 <−100 <−100 −99.73 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

7

N

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

12

<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

= 50 Ω, unless otherwise noted.

O

Rev. 0 | Page 16 of 24

ADL5356

CIRCUIT DESCRIPTION

The ADL5356 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated into
a single die using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.

The RF subsystem consists of integrated, low loss RF baluns,
passive MOSFET mixers, sum termination networks, and IF
amplifiers. The LO subsystem consists of an SPDT-terminated FET
switch and two multistage limiting LO amplifiers. The purpose of
the LO subsystem is to provide a large, fixed amplitude, balanced
signal to drive the mixer independent of the level of the LO input.

A block diagram of the device is shown in Figure 52.

N

M

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

M

S

G

O
P
V

36 35 34 33 32 31 30 29 28

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

S
O
P
V

M

N

O
C

M

M

M

G

M

V

O

D

C

P
O
N
M

P
O
V
D

E

O

L

N

N

M

M

E

N

L

O

V

V

D

D

S
O
P
V

ADL5356

S
O
P
V

G
L
N

C

M

N

27

LOI2

26

VGS2

25

VGS1

24

VGS0

23

LOSW

22

PWDN

21

VPOS

20

COMM

19

LOI1

C

G
L

N
V
D

Figure 52. Simplified Schematic

RF SUBSYSTEM

The single-ended, 50  RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can be
dc connected, it is recommended that a blocking capacitor be used
to avoid running excessive dc current through the part. The RF
balun can easily support an RF input frequency range of 1200 MHz
to 2500 MHz.

07883-001

The resulting balanced RF signal is applied to a passive mixer that
commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss of
the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum network
between the IF amplifier and the mixer and in the feedback
elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that
is required to achieve the overall performance. The balanced open­collector output of the IF amplifier, with impedance modified
by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or an analog-to-digital input while providing optimum second­order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 . If
operation in a 50  system is desired, the output can be
transformed to 50  by using a 4:1 transformer.

The intermodulation performance of the design is generally limited
by the IF amplifier. The IP3 performance can be optimized by
adjusting the IF current with an external resistor.

Figure 41,
Figure 43, and Figure 44 illustrate how various IF and LO bias
resistors affect the performance with a 5 V supply. Additionally,
dc current can be saved by increasing either or both resistors. It
is permissible to reduce the dc supply voltage to as low as 3.3 V,
further reducing the dissipated power of the part. (No performance
enhancement is obtained by reducing the value of these resistors,
and excessive dc power dissipation may result.)

Rev. 0 | Page 17 of 24

ADL5356

LO SUBSYSTEM

The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1700 MHz. The best
operation is achieved with either low-side LO injection for RF
signals in the 1700 MHz to 2500 MHz range or high-side injection
for RF signals in the 1200 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion gain is
extremely wideband, easily spanning 1200 MHz to 2500 MHz,
but intermodulation is optimal over the aforementioned ranges.

The ADL5356 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.

The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier. This
results in consistent performance over a range of LO input power.
Optimum performance is achieved from −6 dBm to +10 dBm,
but the circuit continues to function at considerably lower levels
of LO input power.

The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the LO
amplifier by raising the value of the external bias control resistor.
For dc current critical applications, the LO chain can operate
with a supply voltage as low as 3.3 V, resulting in substantial
dc power savings.

In addition, when operating with supply voltages below 3.6 V, the
ADL5356 has a power-down mode that permits the dc current
to drop to <300 µA.

The logic inputs are designed to work with any logic family that
provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.

Rev. 0 | Page 18 of 24

ADL5356

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5356 mixer is designed to downconvert radio
frequencies (RF) primarily between 1200 MHz and 2500 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 53 depicts the basic connections of the mixer.
It is recommended to ac-couple the RF and LO input ports to
prevent non-zero dc voltages from damaging the RF balun or
LO input circuit. The RFIN matching network consists of a
series 1.8 pF capacitor and a shunt 15 nH inductor to provide
the optimized RF input return loss for the desired frequency band.

IF PORT

The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.

The real part of the output impedance is approximately 200 Ω,
as seen in Figure 30, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the power
conversion gain, as shown in Ta ble 3 . When a 50 Ω output
impedance is needed, use a 4:1 impedance transformer, as shown
in Figure 53.

BIAS RESISTOR SELECTION

The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5)
are used to adjust the bias current of the integrated amplifiers at the
IF and LO terminals. It is necessary to have a sufficient amount
of current to bias both the internal IF and LO amplifiers to optimize
dc current vs. optimum IIP3 performance. Figure 41, Figure 43,
and Figure 44 provide the reference for the bias resistor selection
when lower power consumption is considered at the expense of
conversion gain and IP3 performance.

MIXER VGS CONTROL DAC

The ADL5356 features three logic control pins, VGS0 (Pin 24),
VGS1 (Pin 25), and VGS2 (Pin26), that allow programmability for
internal gate-to-source voltages for optimizing mixer performance
over desired frequency bands. The evaluation board defaults
VGS0, VGS1, and VGS2 to ground. Power conversion gain, NF,
IIP3, and input P1dB can be optimized, as shown in Figure 39
and Figure 40.

Rev. 0 | Page 19 of 24

ADL5356

MAIN_IN

C9

Z1 Z2

C3

C2

MAIN_OUTN

C19 C17

C22

VCC

36 35 34 33 32 31 30 29 28

1

2

3

4

5

R1

C33

C8 C21

L1

C27

R10

VCC

C32

T1

L2

R3

L6

MAIN_OUTP

C25 C18

VCC

R2

R12

R7

R14
R11

C16

R16

C34

R17

LO2

VCC

27

26

R13

25

R8

24

R15

23

DIV_IN

VCC

C6 C7

C11

Z3 Z4

GND

VCC

+

C10

6

7

8

9

10 11 12 13 14 15 16 17 18

VCC

C23

R4

C20

DIV_OUTP DIV_OUTN

C30 C31

VCC

R6

L5

C1 C12

C28

R9

L3

C24 C13

L4

C29

T2

ADL5356

VCC

22

21

C26

20

19

C14

R5

C15

LO1

VCC

R19

07883-153

Figure 53. Typical Application Circuit

Rev. 0 | Page 20 of 24

ADL5356

EVALUATION BOARD

An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 54. The evaluation board is fabricated using Rogers®

RO3003 material. Tab le 7 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 55 and Figure 56.

MAIN_IN

DIV_IN

C9

Z1 Z2

VCC

C11

Z3 Z4

C3 C2

C6 C7

VCC

+

GND

C10

MAIN_OUTN

C22

VCC

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

VCC

C23

R10

C33

C19 C17

S
O
P
V

C8 C21

L1

R1

M

M
G

M

N

O
C

M

C27

VCC

N
O
N
M

T1

L2

R3

L6

P
O
N
M

ADL5356

TOP VIEW

(Not to Scale)

M

M

S

G

O

V

P
V

D

R4

P
M
O
C

L5

N

O

O

V

V

D

D

VCC

R6

L4

S
O
P
V

S
O
P
V

MAIN_OUTP

C18

G
L
N

M

G
L
V
D

C32

C25

E
L
N

M

E
L
V
D

L3

C24 C13

VCC

C
N

C
N

VCC

R2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

R5

LOI2

LOI1

C14

C26

R13

R8

R15

LO1

R12

R7

R14

R11

C16

C15

C34

VCC

R16

R17

LO2

VCC

R19

C1 C12

C28

C20

DIV_OUTP DIV_OUTN

C30 C31

R9

C29

T2

07883-154

Figure 54. Evaluation Board Schematic

Rev. 0 | Page 21 of 24

ADL5356

Table 7. Evaluation Board Configuration

Components Description Default Conditions

C1, C8, C10, C12,
C13, C15, C18,
C21, C22, C23,
C24, C25, C26

Z1 to Z4, C2, C3,
C6, C7, C9, C11

T1, T2, C17, C19,
C20, C27 - C33,
L1, L2, L4, L5,
R3, R6, R9, R10

C14, C16,
R15, LOSEL

R19, PWDN

R1, R2, R4, R5, L3,
L6, R7, R8, R11 to
R14, R16, R17, C34

Power Supply Decoupling. Nominal supply decoupling consists of a

0.01 μF capacitor to ground in parallel with 10 pF capacitors to
ground positioned as close to the device as possible.

RF Main and Diversity Input Interface. Main and diversity
input channels are ac-coupled through C9 and C11. Z1 to
Z4 provide additional component placement for external
matching/filter networks. C2, C3, C6, and C7 provide bypassing
for the center taps of the main and diversity on-chip input baluns.

IF Main and Diversity Output Interface. The open collector IF
output interfaces are biased through pull-up choke inductors
L1, L2, L4, and L5, with R3 and R6 available for additional
supply bypassing. T1 and T2 are 4:1 impedance transformers
used to provide a single-ended IF output interface with C27
and C28 providing center-tap bypassing. C17, C19, C20, C29,
C30, C31, C32, and C33 ensure an ac-coupled output interface.
Remove R9 and R10 for balanced output operation.

LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2
local oscillator inputs. LOSEL selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled
when the LOSEL jumper is removed. Jumper can be removed to
allow LOSEL interface to be exercised using external logic generator.

PWDN Interface. When the PWDN 2-pin shunt is inserted, the
ADL5356 is powered down. When R19 is open, it pulls the PWDN
logic low and enables the device. Jumper can be removed to allow
PWDN interface to be excercised using an external logic generator.
Grounding the PWDN pin is allowed during nominal operation but
is not permitted when supply voltages exceed 3.3 V.

Bias Control. R16 and R17 form a voltage divider to provide a 3 V for
logic control, bypassed to ground through C34. R7, R8, R11, R12, R13,
and R14 provide resistor programmability of VGS0, VGS1, and VGS2.
Typically, these nodes can be hardwired for nominal operation.
Grounding these pins is allowed for nominal operation. R2 and R5 set
the bias point for the internal LO buffers. R1 and R4 set the bias point
for the internal IF amplifiers. L3 and L6 are external inductors used to
improve isolation and common-mode rejection.

C10 = 4.7 μF (Size 3216),
C1, C8, C12, C21 = 150 pF (Size 0402),
C22, C23, C24, C25, C26 = 10 pF (Size 0402),
C13, C15, C18 = 0.1 μF (Size 0402)

C2, C7 = 10 pF (Size 0402),
C3, C6 = 0.01 μF (Size 0402),
C9, C11 = 1.8 pF (Size 0402),
Z2, Z4 = 15 nH,
Z1, Z3 = open (Size 0402)

C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402),
C27, C28 = 150 pF (Size 0402),
T1, T2 = TC4-1T+ (Mini-Circuits),
L1, L2, L4, L5 = 330 nH (Size 0805),
R3, R6, R9, R10 = 0 Ω (Size 0402)

C14, C16 = 10 pF (Size 0402),
R15 = 10 kΩ (Size 0402),
LOSEL = 2-pin shunt

R19 = 10 kΩ (Size 0402),
PWDN = 2-pin shunt

R1, R4 = 1.3 kΩ (Size 0402),
R2, R5 = 1 kΩ (Size 0402),
L3, L6 = 0 Ω (Size 0603),
R12, R13, R14 = open (Size 0402),
R7, R8, R11 = 0 Ω (Size 0402),
R16 = 10 kΩ (Size 0402),
R17 = 15 kΩ (Size 0402),
C34 = 1 nF (Size 0402)

Figure 55. Evaluation Board Top Layer

7883-056

Figure 56. Evaluation Board Bottom Layer

7883-057

Rev. 0 | Page 22 of 24

ADL5356

OUTLINE DIMENSIONS

6.00

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.28

0.23

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM
COPLANARITY

0.60 MAX

0.50

BSC

0.75

0.60

0.50

0.08

Figure 57. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6mm × 6 mm Body, Very Thin Quad (CP-36-1)

Dimensions shown in millimeters

0.60 MAX

28

27

EXPOSED

(BOTTOM VIEW)

19

18

36

1

PAD

9

10

4.00
REF

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

PIN 1
INDICATOR

3.85

3.70 SQ

3.55

0.20 MIN

050808-D

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADL5356ACPZ-R21 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1
ADL5356ACPZ-R71 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1
ADL5356-EVALZ1 Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

ADL5356

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07883-0-10/09(0)

Rev. 0 | Page 24 of 24