Datasheet ADL5355 Datasheet (ANALOG DEVICES)

1200 MHz to 2500 MHz Balanced Mixer,

LO Buffer, IF Amplifier, and RF Balun

FEATURES

RF frequency range of 1200 MHz to 2500 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.4 dB
SSB noise figure of 9.2 dB
SSB noise figure with 5 dBm blocker of 20 dB
Input IP3 of 27 dBm
Input P1dB of 10.4 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance

APPLICATIONS

Cellular base station receivers
Transmit observation receivers
Radio link downconverters

GENERAL DESCRIPTION

The ADL5355 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5355 incorporates
an RF balun, allowing for optimal performance over a 1200 MHz
to 2500 MHz RF input frequency range using low-side LO
injection for RF frequencies from 1700 MHz to 2500 MHz and
high-side LO injection for RF frequencies from 1200 MHz to
1700 MHz. The balanced passive mixer arrangement provides
good LO-to-RF leakage, typically better than −39 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where in­band blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
gain of 8.4 dB and can be used with a wide range of output
impedances.

ADL5355

FUNCTIONAL BLOCK DIAGRAM

IFGM

20 19 18 17 16

1

VPIF

2

RFIN

3

RFCT

4

COMM

5

COMM

6 7 8 9 10

VLO3 LGM3 VLO2 LOSW NC

NC = NO CONNECT

The ADL5355 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5355 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.

The ADL5355 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.

IFOP IFON PWDN LEXT

ADL5355

BIAS

GENERATOR

Figure 1.

15

LOI2

14

VPSW

13

VGS1

12

VGS0

11

LOI1

8080-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADL5355

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Performance ........................................................................... 4

3.3 V Performance ........................................................................ 4

Spur Tables .................................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

5 V Performance ........................................................................... 8

3.3 V Performance ...................................................................... 15

Circuit Description......................................................................... 16

RF Subsystem .............................................................................. 16

LO Subsystem ............................................................................. 17

Applications Information .............................................................. 18

Basic Connections ...................................................................... 18

IF Port .......................................................................................... 18

Bias Resistor Selection ............................................................... 18

Mixer VGS Control DAC .......................................................... 18

Evaluation Board ............................................................................ 20

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5355

SPECIFICATIONS

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 20 dB
Input Impedance 50 Ω
RF Frequency Range 1200 2500 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage

LO INTERFACE

LO Power −6 0 +10 dBm
Return Loss 15 dB
Input Impedance 50 Ω
LO Frequency Range 1230 2470 MHz

POWER-DOWN (PWDN) INTERFACE

PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 220 ns
PWDN Input Bias Current Device enabled 0.0 μA

Device disabled 70 μA

1

Apply the supply voltage from the external circuit through the choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

1

2

Externally generated 3.3 5.0 5.5 V

Rev. 0 | Page 3 of 24

ADL5355

5 V PERFORMANCE

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7 8.4 9.5 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.2 dB
SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 10.4 dBm
LO-to-IF Leakage Unfiltered IF output −12.6 dBm
LO-to-RF Leakage −39 dBm
RF-to-IF Isolation −33 dBc
IF/2 Spurious −10 dBm input power −69 dBc
IF/3 Spurious −10 dBm input power −73 dBc

POWER SUPPLY

Positive Supply Voltage 4.5 5 5.5 V
Quiescent Current LO supply, resistor programmable 100 mA
IF supply, resistor programmable 90 mA
Total Quiescent Current VS = 5 V 190 mA

= 50 Ω, differential Z

SOURCE

= 200 Ω differential 14.7 dB

LOAD

5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered

= 1949.5 MHz, f

f

RF1

= 1950.5 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

20 dB

22 27 dBm

50 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and Z

= 50 Ω, unless otherwise noted.

O

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 9 dB
Voltage Conversion Gain Z
SSB Noise Figure 8.75 dB
Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 7 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 125 mA
Power-Down Current Device disabled 150 μA

= 50 Ω, differential Z

SOURCE

= 1949.5 MHz, f

f

RF1

= 1950.5 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 15.3 dB

LOAD

22 dBm

52 dBm

Rev. 0 | Page 4 of 24

ADL5355

SPUR TABLES

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.

5 V Performance

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.

Table 4.

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −10.0 −21.1 −53.8
1 −42.3 0.0 −57.1 −51.4 −75.9
2 −66.7 −65.3 −57.0 −67.0 −88.4 <−100
3 <−100 <−100 −97.6 −61.6 <−100 <−100 <−100
4 <−100 <−100 <−100 −97.9 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100
14 <−100 <−100
15 <−100

3.3 V Performance

VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and Z

= 50 Ω, unless otherwise noted.

O

Table 5.

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −15.3 −27.3 −65.5
1 −42.9 0.0 −58.3 −52.2 −78.0
2 −64.4 −67.3 −56.6 −73.6 −75.7 <−100
3 <−100 <−100 −95.5 −60.4 <−100 <−100 <−100
4 <−100 <−100 <−100 −97.0 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100
14 <−100 <−100
15 <−100

Rev. 0 | Page 5 of 24

ADL5355

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
IFOP, IFON Bias Voltage 6.0 V
VGS0, VGS1, LOSW, PWDN 5.5 V
Internal Power Dissipation 1.2 W
θJA 25°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 24

ADL5355

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DN

IFON

IFOP

IFGM

20

1VPIF
2RFIN

ADL5355

3RFCT

TOP VIEW

4COMM

(Not to Scale)

5COMM

6

VLO3

NOTES

1.2 NC = NO CONNECT.
. EXPOSED PAD. MUST BE SOLDERED

TO GROUND.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VPIF Positive Supply Voltage for IF Amplifier.
2 RFIN RF Input. Must be ac-coupled.
3 RFCT RF Balun Center Tap (AC Ground).
4, 5 COMM Device Common (DC Ground).
6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
7 LGM3 LO Amplifier Bias Control.
9 LOSW LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V.
10 NC No Connect.
11, 15 LOI1, LOI2 LO Inputs. Must be ac-coupled.
12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
14 VPSW Positive Supply Voltage for LO Switch.
16 LEXT IF Return. This pin must be grounded.
17 PWDN Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode.
18, 19 IFON, IFOP Differential IF Outputs (Open Collectors). Each requires an external dc bias.
20 IFGM IF Amplifier Bias Control.
EPAD (EP) Exposed pad. Must be soldered to ground.

PW

17

18

19

PIN 1
INDICATOR

9

8

7

VLO2

LGM3

LOSW

LEXT

16

10

NC

15 LO I2
14 VPSW
13 VGS1
12 VGS0
11 LO I1

08080-002

Rev. 0 | Page 7 of 24

ADL5355

m

A

3

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and Z

= 50 Ω, unless otherwise noted.

O

240

220

)

200

180

160

SUPPLY CURRENT (

140

TA = –40°C

T

= +85°C

A

= +25°C

T

A

70

TA = –40°C

T

= +85°C

A

= +25°C

A

60

50

T

40

30

INPUT IP2 (dBm)

20

120

100

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20
RF FREQUENCY (GHz)

Figure 3. Supply Current vs. RF Frequency

20

18

16

14

12

10

8

6

CONVERSION G AIN (dB)

4

2

0

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

TA = –40°C

= +85°C

T

A

RF FREQUENCY ( GHz)

T

= +25°C

A

Figure 4. Power Conversion Gain vs. RF Frequency

35

TA = –40°C

30

25

20

(dBm)

15

INPUT IP

10

5

0

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

T

= +25°C

A

T

= +85°C

A

RF FREQUENCY (GHz)

Figure 5. Input IP3 vs. RF Frequency

10

0

08080-007

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20
RF FREQUENCY (GHz)

08080-015

Figure 6. Input IP2 vs. RF Frequency

15

14

13

12

11

10

9

INPUT P1dB (dBm)

8

7

6

5

08080-011

T

= +85°C

A

TA = –40°C

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

TA = +25°C

RF FREQUENCY (GHz)

08080-023

Figure 7. Input P1dB vs. RF Frequency

20

18

16

14

= +85°C

T

12

10

8

6

SSB NOISE F IGURE (dB)

4

2

0

1.70 1.75 1.80 1.85 1. 90 1.95 2. 00 2.05 2.10 2.15 2.20

08080-019

A

TA = –40°C

RF FREQUENCY (GHz)

T

= +25°C

A

08080-033

Figure 8. SSB Noise Figure vs. RF Frequency

Rev. 0 | Page 8 of 24

ADL5355

250

= 5.25V

V

200

150

100

SUPPLY CURRENT (mA)

50

0

–40 –20 0 20 40 60 80

POS

V

= 4.75V

POS

TEMPERATURE (° C)

V

= 5.0V

POS

Figure 9. Supply Current vs. Temperature

12

V

= 4.75V

POS

= 5.0V

V

POS

11

10

9

8

7

CONVERSION G AIN (dB)

6

= 5.25V

V

POS

08080-008

60

V

= 5.25V

55

50

V

= 4.75V

POS

45

40

35

30

INPUT IP2 (dBm)

25

20

15

10

–40 –20 0 20 40 60 80

V

POS

TEMPERATURE (° C)

POS

= 5.0V

Figure 12. Input IP2 vs. Temperature

12

10

8

6

INPUT P1dB (dBm)

4

2

V

= 5.25V

POS

V

= 4.75V

POS

V

= 5.0V

POS

08080-016

5

–40 –20 0 20 40 60 80

TEMPERATURE ( °C)

Figure 10. Power Conversion Gain vs. Temperature

35

V

= 5.25V

30

V

= 4.75V

25

20

15

INPUT IP3 (dBm)

10

5

0
–40 –20 0 20 40 60 80

POS

TEMPERATURE (°C)

POS

V

= 5.0V

POS

Figure 11. Input IP3 vs. Temperature

0

–40 –20 0 20 40 60 80

08080-012

TEMPERATURE (° C)

08080-024

Figure 13. Input P1dB vs. Temperature

12

11

10

= 5.25V

V

POS

9

8

SSB NOISE F IGURE (dB)

7

6
–40 806040200–20

08080-020

= 5.0V

V

POS

TEMPERATURE (° C)

V

POS

= 4.75V

08080-034

Figure 14. SSB Noise Figure vs. Temperature

Rev. 0 | Page 9 of 24

ADL5355

m

m

230

220

210

200

190

180

SUPPLY CURRENT (mA)

170

160

150

30 80 130 180 230 280 330 380 430

TA = –40°C

T

= +85°C

A

IF FREQUENCY (MHz)

= +25°C

T

A

Figure 15. Supply Current vs. IF Frequency

12

10

8

6

T

= –40°C

A

= +85°C

T

A

TA = +25°C

08080-006

70

TA = –40°C

T

60

50

)

40

30

INPUT IP2 (dB

20

10

0

30 80 130180230280330380430

IF FREQUENCY (MHz)

= +25°C

A

= +85°C

T

A

Figure 18. Input IP2 vs. IF Frequency

12

10

)

8

6

T

= +85°C

A

TA = –40°C

= +25°C

T

A

08080-013

4

CONVERSION G AIN (dB)

2

0

30 80 130 180 230 280 330 380 430

IF FREQUENCY (MHz)

Figure 16. Power Conversion Gain vs. IF Frequency

40

35

30

25

20

15

INPUT IP3 (dBm)

10

5

0

30 80 130 180 230 280 330 380 430

TA = –40°C

T

= +85°C

A

= +25°C

T

A

IF FREQUENCY (MHz)

Figure 17. Input IP3 vs. IF Frequency

4

INPUT P1dB (dB

2

0

30 80 130180230280330380430

08080-009

IF FREQUENCY (MHz)

08080-021

Figure 19. Input P1dB vs. IF Frequency

15

14

13

12

11

10

9

8

SSB NOISE F IGURE (dB)

7

6

5

30 43038033028023018013080

08080-017

IF FREQUENCY (MHz)

08080-035

Figure 20. SSB Noise Figure vs. IF Frequency

Rev. 0 | Page 10 of 24

ADL5355

–

–

10

9

8

7

6

5

4

3

CONVERSION G AIN (dB)

2

1

0

–6 –4 –2 0 2 4 6

TA = –40°C

TA = +85°C

LO POWER (dBm)

Figure 21. Power Conversion Gain vs. LO Power

35

30

25

20

TA = –40°C

TA = +25°C

TA = +85°C

TA = +25°C

810

08080-010

14

12

10

8

6

INPUT P1dB (dBm)

4

2

0

–6 –4 –2 0 2 4 6 8 10

TA = +85°C

TA = –40°C

TA = +25°C

LO POW ER (dBm)

Figure 24. Input P1dB vs. LO Power

50

–55

–60

8080-022

15

INPUT IP3 (dBm)

10

5

0

–6–4–20246810

LO POW ER (dBm)

Figure 22. Input IP3 vs. LO Power

65

60

TA = +85°C

TA = –40°C

TA = +25°C

810

LO POWER (dBm)

55

50

45

INPUT IP2 (dBm)

40

35

30

–6 –4 –2 0 2 4 6

Figure 23. Input IP2 vs. LO Power

–65

IF/2 SPURIOUS (dBc)

–70

–75

8080-018

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

TA = –40°C

= +85°C

T

A

RF FREQUENCY ( GHz)

T

= +25°C

A

8080-025

Figure 25. IF/2 Spurious vs. RF Frequency

50

–55

–60

–65

–70

IF/3 SPURIOUS (dBc)

–75

–80

08080-014

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

TA = –40°C

TA = +25°C

= +85°C

T

A

RF FREQUENCY ( GHz)

8080-027

Figure 26. IF/3 Spurious vs. RF Frequency

Rev. 0 | Page 11 of 24

ADL5355

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAGE (%)

10

0

7.0 7.5 8. 0 8. 5 9. 0 9. 5 10.0

100

90

80

70

60

50

40

30

20

DISTRIBUTI ON PERCENTAGE (%)

10

0

22 24 26 28 30 32 34

100

90

80

70

60

50

40

30

20

DISTRI BUTION PERCE NTAGE (%)

10

0

8 9 10 11 12 13 14

CONVERSION GAIN (dB)

Figure 27. Conversion Gain Distribution

INPUT IP3 (dBm)

Figure 28. Input IP3 Distribution

INPUT P1dB (dBm)

Figure 29. Input P1dB Distribution

500

400

300

200

RESISTANCE (Ω)

100

0

80 130 180 230 280 330 38030 430

08080-046

IF FREQUENCY ( MHz)

10

8

6

4

CAPACITANCE (pF)

2

0

08080-043

Figure 30. IF Port Return Loss

0

5

10

15

20

RF RETURN LOSS (dB)

25

30

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

08080-047

RF FREQUENCY (GHz)

08080-036

Figure 31. RF Port Return Loss, Fixed IF

0

5

10

15

20

LO RETURN LOSS (dB)

25

30

1.50 1.55 1. 60 1.65 1. 70 1.75 1.80 1.85 1.90 1.95 2.00

08080-048

SELECTED

UNSELECTED

LO FREQUENCY (GHz)

Figure 32. LO Return Loss, Selected and Unselected

08080-037

Rev. 0 | Page 12 of 24

ADL5355

A

L

70

65

60

TION (dB)

55

50

LO SWITCH ISOL

45

40

1.50 2.001.55 1.60 1.65 1. 70 1.75 1.80 1. 85 1.90 1.95

= –40°C

T

A

TA = +85°C

LO FREQ UENCY (GHz)

Figure 33. LO Switch Isolation vs. LO Frequency

0

= +25°C

T

A

08080-041

0

–5

–10

–15

–20

–25

–30

T

= +25°C

LO-TO -RF LEAKAGE ( dBm)

–35

–40

–45

A

1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00

T

= +85°C

A

TA = –40°C

LO FREQUENCY (GHz)

Figure 36. LO-to-RF Leakage vs. LO Frequency

0

08080-030

–10

–20

TA = +25°C

–30

–40

RF-TO-IF ISOLATION (dBc)

–50

–60

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

T

= +85°C

A

TA = –40°C

RF FREQUENCY ( GHz)

Figure 34. RF-to-IF Isolation vs. RF Frequency

0

–5

TA = –40°C

–10

T

= +25°C

A

–15

LO-TO-IF LEAKAGE (dBm)

–20

= +85°C

T

A

–5

–10

–15

–20

–25

O LEAKAGE (dBm)
2

–30

–35

–40

1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00

8080-032

LO FREQUENCY (GHz)

2LO TO IF

2LO TO RF

08080-026

Figure 37. 2LO Leakage vs. LO Frequency

0

–10

–20

–30

–40

3LO LEAKAGE (dBm)

–50

–60

3LO TO RF

3LO TO IF

–25

1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1. 95 2.00
LO FREQUENCY (GHz)

Figure 35. LO-to-IF Leakage vs. LO Frequency

08080-029

–70

1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00

LO FREQUENCY (GHz)

Figure 38. 3LO Leakage vs. LO Frequency

08080-028

Rev. 0 | Page 13 of 24

ADL5355

10

9

8

CONVERSION

7

6

5

4

3

CONVERS ION GAIN (dB)

2

1

0

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency

20

18

16

INPUT IP3

14

12

INPUT P1dB (dBm)

10

VGS = 00

8

VGS = 01
VGS = 10
VGS = 11

6

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

Figure 40. Input IP3 and Input P1dB vs. RF Frequency

12

11

GAIN

SSB NOISE FIGURE

RF FREQUEN CY (GHz)

INPUT

P1dB

RF FREQUENCY (GHz)

INPUT IP3

VGS = 00
VGS = 01
VGS = 10
VGS = 11

30

28

26

24

22

20

18

16

30

25

15

14

13

12

11

10

9

8

SSB NOISE F IGURE (dB)

7

6

5

08080-039

30

25

20

15

10

SSB NOISE FIGURE (dB)

5

0

–30 –25 –20 –15 –10 –5 0 5 10

BLOCKER POWER (dBm)

08080-031

Figure 42. SSB Noise Figure vs.10 MHz Offset Blocker Level

160

150

140

130

120

110

INPUT IP3 (dBm)

08080-038

100

90

SUPPLY CURRENT (mA)

R14 IF SET RESISTOR

80

70

60

600 80 0 1000 1200 1400 1600 1800

R9 LO SET RESISTOR

BIAS RESISTOR VALUE (Ω)

08080-040

Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value

12

INPUT IP3

11

30

25

10

9

8

7

CONVERSION G AIN AND SSB NOISE FI GURE (dB)

6

0.6 0. 8 1. 0 1. 2 1.4 1.6 1. 8

LO BIAS RESI STOR VALUE (kΩ)

Figure 41. Power Conversion Gain, SSB Noise Figure, and

Input IP3 vs. LO Bias Resistor Value

SSB NOISE FIGURE

CONVERSION GAIN

20

15

INPUT IP3 (dBm)

10

5

0

08080-044

Rev. 0 | Page 14 of 24

10

9

8

7

CONVERSION G AIN AND SSB NOIS E FIGURE ( dB)

6

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

IF BIAS RESI STOR VALUE (kΩ)

SSB NOISE F IGURE

CONVERSION G AIN

Figure 44. Power Conversion Gain, SSB Noise Figure, and

Input IP3 vs. IF Bias Resistor Value

20

15

INPUT IP3 (dBm)

10

5

0

08080-045

ADL5355

3.3 V PERFORMANCE

VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and Z

= 50 Ω, unless otherwise noted.

O

150

145

140

135

130

125

120

115

SUPPLY CURRENT (mA)

110

105

100

1.70 1.75 1. 80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

RF FREQUENCY (GHz)

TA = –40°C

T

= +85°C

T

A

= +25°C

A

Figure 45. Supply Current vs. RF Frequency at 3.3 V

12

T

= +25°C

10

A

TA = –40°C

08080-053

70

= +25°C

T

A

60

50

T

40

30

INPUT IP2 (dBm)

20

10

0

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

TA = –40°C

= +85°C

A

RF FREQUENCY (GHz)

Figure 48. Input IP2 vs. RF Frequency at 3.3 V

14

12

08080-050

8

T

= +85°C

6

4

CONVERSION G AIN (dB)

2

0

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

RF FREQUENCY (GHz)

A

Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V

30

TA = –40°C

25

= +25°C

T

A

20

15

INPUT IP3 (dBm)

10

5

= +85°C

T

A

10

= +85°C

T

= +25°C

T

8

6

INPUT P1dB (dBm)

4

2

0

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2. 20

08080-049

A

RF FREQUENCY (GHz)

A

TA = –40°C

08080-052

Figure 49. Input P1dB vs. RF Frequency at 3.3 V

14

12

TA = +85°C

10

8

6

SSB NOISE F IGURE (dB)

4

TA = +25°C

TA = –40°C

0

1.70 1.75 1. 80 1.85 1.90 1.95 2.00 2.05 2.10 2. 15 2.20

RF FREQUENCY (G Hz)

08080-051

Figure 47. Input IP3 vs. RF Frequency at 3.3 V

2

1.70 1.75 1. 80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2. 20

RF FREQUENCY (GHz)

Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V

08080-054

Rev. 0 | Page 15 of 24

ADL5355

CIRCUIT DESCRIPTION

The ADL5355 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.

The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.

The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.

A block diagram of the device is shown in Figure 51.

IFGM

20 19 18 17 16

1

VPIF

2

RFIN

3

RFCT

4

COMM

5

COMM

VLO3 LGM3 VLO2 LOSW NC

NC = NO CONNECT

6 7 8 9 10

IFOP IFON PWDN LEXT

ADL5355

BIAS

GENERATOR

Figure 51. Simplified Schematic

15

14

13

12

11

LOI2

VPSW

VGS1

VGS0

LOI1

RF SUBSYSTEM

The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 1200 MHz to 2500 MHz.

The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.

As the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum
network between the IF amplifier and the mixer and also in
the feedback elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that is
required to achieve the overall performance. The balanced open­collector output of the IF amplifier, with impedance modified
by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or an analog-to-digital input while providing optimum second­order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 Ω. If operation

8080-001

in a 50 Ω system is desired, the output can be transformed to
50 Ω by using a 4:1 transformer.

The intermodulation performance of the design is generally
limited by the IF amplifier. The IP3 performance can be optimized
by adjusting the IF current with an external resistor.
Figure 43, and Figure 44 illustrate how various IF and LO bias
resistors affect the performance with a 5 V supply. Additionally,
dc current can be saved by increasing either or both resistors. It
is permissible to reduce the dc supply voltage to as low as 3.3 V,
further reducing the dissipated power of the part. (Note that no
performance enhancement is obtained by reducing the value of
these resistors and excessive dc power dissipation may result.)

Figure 41,

Rev. 0 | Page 16 of 24

ADL5355

LO SUBSYSTEM

The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1700 MHz. The best
operation is achieved with either low-side LO injection for RF
signals in the 1700 MHz to 2500 MHz range or high-side injection
for RF signals in the 1200 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion gain is
extremely wideband, easily spanning 1200 MHz to 2500 MHz,
but intermodulation is optimal over the aforementioned ranges.

The ADL5355 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.

The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.

The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.

In addition, when operating with supply voltages below 3.6 V,
the ADL5355 has a power-down mode that permits the dc
current to drop to <200 μA.

All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.

All pins, including the RF pins, are ESD protected and have
been tested up to a level of 1500 V HBM and 500 V CDM.

Rev. 0 | Page 17 of 24

ADL5355

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5355 mixer is designed to downconvert radio
frequencies (RF) primarily between 1200 MHz and 2500 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 52 depicts the basic connections of the mixer.
It is recommended to ac-couple RF and LO input ports to
prevent non-zero dc voltages from damaging the RF balun or LO
input circuit. The RFIN capacitor value of 3 pF is recommended
to provide the optimized RF input return loss for the desired
frequency band.

IF PORT

The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.

The real part of the output impedance is approximately
200 Ω, as seen in Figure 30, which matches many commonly
used SAW filters without the need for a transformer. This results in
a voltage conversion gain that is approximately 6 dB higher than
the power conversion gain, as shown in Tabl e 2. When a 50 Ω
output impedance is needed, use a 4:1 impedance transformer,
as shown in Figure 52.

BIAS RESISTOR SELECTION

Two external resistors, R
bias current of the integrated amplifiers at the IF and LO terminals.
It is necessary to have a sufficient amount of current to bias both
the internal IF and LO amplifiers to optimize dc current vs.
optimum IIP3 performance. Figure 41, Figure 43, and Figure 44
provide the reference for the bias resistor selection when lower
power consumption is considered at the expense of conversion
gain and IP3 performance.

BIAS IF

and R

, are used to adjust the

BIAS LO

MIXER VGS CONTROL DAC

The ADL5355 features two logic control pins, VGS0 (Pin 12) and
VGS1 (Pin 13), that allow programmability for internal gate-to­source voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground. Power conversion gain, IIP3, NF, and IP1dB
can be optimized, as is shown in Figure 39 and Figure 40.

Rev. 0 | Page 18 of 24

ADL5355

V

+5

100pF

150pF

470nH 470n H

+5V

4.7µF

+5V

10pF

4:1

R

BIAS IF

20

19 18 17 16

10kΩ

ADL5355

1

15

IF OUT

22pF

LO2 IN

3pF

RF IN

2

14

+5V

10pF

10pF

0.1µF

3

BIAS

GENERATOR

4

13

12

22pF

LO1 IN

+5V

5

6 7 8 9 10

R

BIAS LO

11

10kΩ

10pF10pF

08080-005

Figure 52. Typical Application Circuit

Rev. 0 | Page 19 of 24

ADL5355

EVALUATION BOARD

An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 53. The evaluation board is fabricated using Rogers®
RO3003 material. Tab le 8 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 54 to Figure 57.

L5

VPOS

C18

100pF

470nH

T1

IF1-OUT

RF-IN

VPOS

C1

3pF

100pF

C2
10µF

C5

0.01µFC410pF

C19

C21
10pF

VPOS

10pF

L4

470nH

R14
910Ω

VPIF

RFIN

RFCT

COMM

COMM

C6

R25

0Ω

GM
IF

VLO3

R9

1.1kΩ

R24
0Ω

IFOP

IFON

ADL5355

LO2

LGM3

V

C8
10pF

DN
W

P

LOSW

C17
150pF

VPOS

LEXT

NC

L3
0Ω

LOI2

VPSW

VGS1

VGS0

LOI1

R4
10kΩ

R1
0Ω

R21
10kΩ

VGS0

C12

22pF

LOSEL

PWR_UP

VGS1

C10

22nF

LO2_IN

C20
10pF

C22
1nF

VPOS

LO1_IN

R22
10kΩ

R23
15kΩ

8080-042

Figure 53. Evaluation Board Schematic

Rev. 0 | Page 20 of 24

ADL5355

Table 8. Evaluation Board Configuration

Components Description Default Conditions

C2, C6, C8, C18, C19,
C20, C21

C1, C4, C5

T1, C17, L4, L5,
R1, R24, R25

C10, C12, R4

R21

C22, L3, R9, R14, R22,
R23, VGS0, VGS1

Power Supply Decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.

RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.

IF Output Interface. The open-collector IF output interfaces are
biased through pull-up choke inductors L4 and L5. T1is a 4:1
impedance transformer used to provide a single-ended IF output
interface, with C17 providing center-tap bypassing. Remove R1 for
balanced output operation.

LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO
input for both mixer cores. R4 provides a pull-down to ensure that
LO1_IN is enabled when the LOSEL test point is logic low.
LO2_IN is enabled when LOSEL is pulled to logic high.

PWDN Interface. R21 pulls the PWDN logic low and enables the
device. The PWR_UP test point allows the PWDN interface to be
exercised using the external logic generator. Grounding the
PWDN pin for nominal operation is allowed. Using the PWDN pin
when supply voltages exceed 3.3 V is not allowed.

Bias Control. R22 and R23 form a voltage divider to provide 3 V
for logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal
operation. R9 sets the bias point for the internal LO buffers.
R14 sets the bias point for the internal IF amplifier.

C2 = 10 μF (size 0603),
C6, C8, C20, C21 = 10 pF (size 0402),
C18, C19 = 100 pF (size 0402)

C1 = 3 pF (size 0402), C4 = 10 pF (size 0402),
C5 = 0.01 μF (size 0402)

T1 = TC4-1W+ (Mini-Circuits),
C17 = 150 pF (size 0402),
L4, L5 = 470 nH (size 1008),
R1, R24, R25 = 0 Ω (size 0402)

C10, C12 = 22 pF (size 0402),
R4 = 10 kΩ (size 0402)

R21 = 10 kΩ (size 0402)

C22 = 1 nF (size 0402), L3 = 0 Ω (size 0603),
R9 = 1.1 kΩ (size 0402), R14 = 910 Ω (size 0402),
R22 = 10 kΩ (size 0402), R23 = 15 kΩ (size 0402),
VGS0 = VGS1 = 3-pin shunt

Rev. 0 | Page 21 of 24

ADL5355

Figure 54. Evaluation Board Top Layer

Figure 55. Evaluation Board Ground Plane, Internal Layer 1

08080-055

08080-057

Figure 56. Evaluation Board Power Plane, Internal Layer 2

08080-056

08080-058

Figure 57. Evaluation Board Bottom Layer

Rev. 0 | Page 22 of 24

ADL5355

C

OUTLINE DIMENSIONS

0.05

0.65

BSC

0.75

0.60

0.50

0.60 MAX

15

16

10

11

20

EXPOSED

PAD

(BOTTOM VIEW)

6

2.60 BSC

FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION OF THIS DATA SHEET.

N

I

1

P

R

O

T

N

D

C

I

A

I

1

3.20

3.10 SQ

3.00

5

042209-B

5.00

INDI

ATO R

0.90

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP VIEW

0.70

0.65

0.60

0.35

0.28

0.23

COMPLIANTTOJEDEC STANDARDS MO-220-VHHC

4.75

BSC SQ

0.20 REF

0.60 MAX

0.05 MAX

0.01 NOM
COPLANARITY

Figure 58. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-20-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADL5355ACPZ-R7
ADL5355ACPZ-WP
ADL5355-EVALZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-5 1,500, 7” Tape and Reel

1

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-5 36, Waffle Pack

1

Evaluation Board 1

Te mp e ra tu r e
Range Package Description

Package
Option

Ordering
Quantity

Rev. 0 | Page 23 of 24

ADL5355

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08080-0-7/09(0)

Rev. 0 | Page 24 of 24