Datasheet ADL5354 Datasheet (ANALOG DEVICES)

2200 MHz to 2700 MHz, Dual-Balanced

Mixer, LO Buffer, IF Amplifier, and RF

Balun

FEATURES

RF frequency range of 2200 MHz to 2700 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.6 dB SSB noise figure of 10.6 dB Input IP3 of 26.1 dBm Input P1dB of 10.6 dBm Typical LO power of 0 dBm Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP 1500 V HBM/500 V FICDM ESD performance

APPLICATIONS

Cellular base station receivers Transmit observation receivers Radio link downconverters

GENERAL DESCRIPTION

The ADL5354 uses a highly linear, doubly balanced, passive mixer core along with integrated RF and local oscillator (LO) balancing circuitry to allow single-ended operation. The ADL5354 incorporates the RF baluns, allowing for optimal performance over a 2200 MHz to 2700 MHz RF input frequency range. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −37 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8 dB and can be used with a wide range of output impedances.

The ADL5354 provides two switched LO paths that can be used in time division duplex (TDD) applications where it is desirable to ping-pong between two local oscillators. LO current can be externally set using a resistor to minimize dc current

ADL5354

FUNCTIONAL BLOCK DIAGRAM

N

M

S

G

M

N

O C

M

35

34

11

12

M

G

M

V

O

D

C

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

O P V

36

1

2

3

4

5

6

7

8

9

10

S O P V

commensurate with the desired level of performance. For low voltage applications, the ADL5354 is capable of operation at voltages as low as 3.3 V with substantially reduced current. For low voltage operation, an additional logic pin is provided to power down (~300 µA) the circuit when desired.

The ADL5354 is fabricated using a BiCMOS high performance IC process. The device is available in a 6 mm × 6 mm, 36-lead LFCSP and operates over a −40°C to +85°C temperature range. An evaluation board is also available.

Table 1. Passive Mixers

RF Frequency (MHz)

Single Mixer

500 to 1700 ADL5367 ADL5357 ADL5358 1200 to 2500 ADL5365 ADL5355 ADL5356 2200 to 2700 ADL5353 ADL5354

P

O

N

M

33

32

13

14

P

N

O

V

D

Figure 1.

Single Mixer and IF Amp

E L N

M

31

ADL5354

15

E L V D

S O P V

30

16

S O P V

G L N

C

M

N

29

28

17

18

C

G L

N V D

Dual Mixer and IF Amp

27

26

25

24

23

22

21

20

19

LOI2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

LOI1

09118-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADL5354

REVISION HISTORY

2/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5354

SPECIFICATIONS

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, Z

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 20 dB Input Impedance 50 Ω RF Frequency Range 2200 2700 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF IF Frequency Range 30 450 MHz DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V

LO INTERFACE

LO Power −6 0 +10 dBm Return Loss 13 dB Input Impedance 50 Ω LO Frequency Range 1750 2670 MHz

POWER-DOWN (PWDN) INTERFACE2

PWDN Threshold 1.0 V Logic 0 Level 0.4 V Logic 1 Level 1.4 V PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns Device disabled, supply current < 5 mA 230 ns PWDN Input Bias Current Device enabled 0 µA

Device disabled 70 µA

1

Apply supply voltage from external circuit through choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

Rev. 0 | Page 3 of 24

ADL5354

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.6 dB Voltage Conversion Gain Z SSB Noise Figure 10.6 dB Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 10.6 dBm LO-to-IF Leakage Unfiltered IF output −20.7 dBm LO-to-RF Leakage −37 dBm RF-to-IF Isolation −34 dBc IF/2 Spurious −10 dBm input power −73 dBc IF/3 Spurious −10 dBm input power −71 dBc IF Channel-to-Channel Isolation 52 dB

POWER SUPPLY

Positive Supply Voltage 4.75 5 5.25 V Quiescent Current LO supply 170 mA IF supply 180 mA Total Quiescent Current VS = 5 V 350 mA

= 50 Ω, unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

= 2534.5 MHz, f

f

RF1

each RF tone at −10 dBm

= 2535 MHz, f

f

RF1

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.6 dB

LOAD

= 2535.5 MHz, fLO = 2332 MHz,

RF2

= 2585 MHz, fLO = 2332 MHz,

26.1 dBm

50 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V, and Z

= 50 , unless otherwise noted.

O

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8 dB Voltage Conversion Gain Z SSB Noise Figure 9.9 dB Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 7 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V Quiescent Current Resistor programmable 200 mA Power-Down Current Device disabled 300 A

= 50 Ω, differential Z

SOURCE

= 2534.5 MHz, f

f

RF1

RF tone at −10 dBm

= 2535 MHz, f

f

RF1

RF2

tone at −10 dBm

= 200 Ω differential 14 dB

LOAD

= 2535.5 MHz, fLO = 2332 MHz, each

RF2

= 2585 MHz, fLO = 2332 MHz, each RF

17.5 dBm

49 dBm

Rev. 0 | Page 4 of 24

ADL5354

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage, VS 5.5 V RF Input Level 20 dBm LO Input Level 13 dBm MNOP, MNON, DVOP, DVON Bias 6.0 V VGS2,VGS1,VGS0, LOSW, PWDN 5.5 V Internal Power Dissipation 2.2 W Thermal Characteristic θJA 22°C/W Maximum Junction Temperature 150°C Temperature Range

Operating −40°C to +85°C Storage −65°C to +150°C

Lead Temperature (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5354

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

N

M

P

E

S

O

G

M

O

N

O

P

M

C

M

V

6

5

4

3

1

MNIN

2

MNCT

3

COMM

4

VPOS

5

COMM

6

VPOS

7

COMM

DVCT

8 9

DVIN

NOTES

12. NC = NO CONNECT. . EXPOSED P AD MUST BE CONNECTED TO GRO UND.

ADL5354

TOP VIEW

(Not to Scale)

0

1

2

1

S

M

O

G

M

P

V

O

V

D

C

3 1

P O V D

Figure 2. Pin Configuration

G

S

O

L

O

N

C

P

M

V

M

2 3

4 1

N O V D

N

1

0

9

8

3

2

5

6

7

8

1

S

E

C

G

L

N

O

V

P

D

V

D

27

LOI2 VGS2

26

VGS1

25

VGS0

24

LOSW

23 22

PWDN

21

VPOS

20

COMM LOI1

19

09118-002

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled. 2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor. 3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground). 4, 6, 10, 16, 21, 30, 36 VPOS Positive Supply Voltage. 8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor. 9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled. 11 DVGM Diversity Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation. 13, 14 DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled up to

VCC using external inductors, see Figure 53 for details. 15 DVLE Diversity Channel IF Return. This pin must be grounded. 17 DVLG Diversity Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation. 18, 28 NC No Connect. Do not connect to this pin. 19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled. 22 PWDN

Power Down. Connect this pin to ground for normal operation. Connect pin to 3 V for disable

mode when using VPOS ≤ 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V. 23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2. 24, 25, 26

VGS0, VGS1, VGS2

Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to a low logic

level. 27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled. 29 MNLG Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation. 31 MNLE Main Channel IF Return. This pin must be grounded. 32, 33 MNOP, MNON

Main Channel Differential Open-Collector Outputs. Pull up MNOP and MNON to VCC by using

external inductors, see Figure 53 for details. 35 MNGM Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation. EPAD Exposed Paddle. Exposed pad must be connected to ground.

Rev. 0 | Page 6 of 24

ADL5354

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

390

380

370

360

350

340

330

SUPPLY CURRENT (mA)

320

310

300

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = –40°C

T

= +25°C

A

T

= +85°C

A

RF FREQUENCY ( GHz)

Figure 3. Supply Current vs. RF Frequency

12

09118-003

60

58

56

54

52

50

48

INPUT IP2 (dBm)

46

44

42

40

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

T

= +25°C

A

RF FREQUENCY ( GHz)

TA = –40°C

= +85°C

T

A

Figure 6. Input IP2 vs. RF Frequency

18

09118-006

11

10

9

8

7

CONVERSION GAIN (dB)

6

5

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = –40°C

T

= +25°C

A

T

= +85°C

A

RF FREQUENCY ( GHz)

Figure 4. Power Conversion Gain vs. RF Frequency

35

30

25

T

= +25°C

20

INPUT IP3 (dBm)

15

10

A

TA = –40°C

T

= +85°C

A

16

14

12

10

INPUT P1dB (dBm)

8

6

4

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

09118-004

T

TA = –40°C

= +85°C

A

T

= +25°C

A

RF FREQUENCY ( GHz)

09118-007

Figure 7. Input P1dB vs. RF Frequency

14

13

12

11

10

9

SSB NOISE FIGURE (dB)

8

7

= +85°C

T

A

= +25°C

T

A

TA = –40°C

5

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

RF FREQUENCY ( GHz)

Figure 5. Input IP3 vs. RF Frequency

09118-005

6

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

RF FREQUENCY ( GHz)

Figure 8. SSB Noise Figure vs. RF Frequency

09118-008

Rev. 0 | Page 7 of 24

ADL5354

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

390

380

370

360

350

340

330

SUPPLY CURRENT (mA)

320

310

300

–40 806040200–20 70503010–10–30

TEMPERATURE (°C)

VS = 5.25V

= 5.00V

V

S

= 4.75V

V

S

09118-009

Figure 9. Supply Current vs. Temperature

9.4

9.2

9.0

8.8

8.6

8.4

CONVERSION GAIN (dB)

8.2

8.0

7.8 –40 806040200–20 70503010–10–30

TEMPERATURE (°C)

V

S

= 4.75V

VS = 5.25V

V

= 5.00V

S

09118-010

Figure 10. Power Conversion Gain vs. Temperature

29

28

= 5.00V

VS = 5.25V

09118-011

27

26

25

24

INPUT IP3 (dBm)

23

22

21

–40 806040200–20 70503010–10–30

V

S

= 4.75V

V

S

TEMPERATURE (°C)

Figure 11. Input IP3 vs. Temperature

53

52

51

50

49

INPUT IP2 (dBm)

48

47

46

–40 806040200–20 70503010–10–30

VS = 5.25V

= 5.00V

V

S

= 4.75V

V

S

TEMPERATURE (°C)

Figure 12. Input IP2 vs. Temperature

15

14

13

12

11

10

9

INPUT P1dB (dBm)

8

7

6

5

–40 806040200–20 70503010–10–30

VS = 5.25V

V

= 4.75V

S

TEMPERATURE (°C)

V

S

= 5.00V

Figure 13. Input P1dB vs. Temperature

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

SSB NOISE FIGURE (dB)

8.0

7.5

7.0 –40 806040200–20 70503010–10–30

VS = 5.25V

V

= 4.75V

S

TEMPERATURE (°C)

V

S

= 5.00V

Figure 14. SSB Noise Figure vs. Temperature

09118-012

09118-013

09118-014

Rev. 0 | Page 8 of 24

ADL5354

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

400

390

380

370

360

350

340

330

SUPPLY CURRENT (mA)

320

310

300

30 43038033028023018013080

12

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

TA = –40°C

TA = +25°C

TA = +85°C

IF FREQUENCY (MHz)

09118-015

Figure 15. Supply Current vs. IF Frequency

INPUT IP2 (dBm)

60

58

56

54

52

50

48

46

44

42

40

30 43038033028023018013080

12

TA = +25°C

IF FREQUENCY (MHz)

TA = –40°C

TA = +85°C

Figure 18. Input IP2 vs. IF Frequency

09118-018

11

CONVERSION GAIN (dB)

10

9

8

7

6

5

4

30 43038033028023018013080

TA = +25°C

TA = –40°C

TA = +85°C

IF FREQUENCY (MHz)

Figure 16. Power Conversion Gain vs. IF Frequency

40

35

30

TA = –40°C

25

TA = +85°C

INPUT IP3 (dBm)

20

15

TA = +25°C

11

10

9

8

INPUT P1dB (dBm)

7

6

30 43038033028023018013080

09118-016

TA = +85°C

TA = +25°C

IF FREQUENCY (MHz)

TA = –40°C

09118-019

Figure 19. Input P1dB vs. IF Frequency

14

13

12

11

10

9

SSB NOISE FIGURE (dB)

8

10

30 43038033028023018013080

IF FREQUENCY (MHz)

Figure 17. Input IP3 vs. IF Frequency

09118-017

7

30 43038033028023018013080

IF FREQUENCY (MHz)

Figure 20. SSB Noise Figure vs. IF Frequency

09118-020

Rev. 0 | Page 9 of 24

ADL5354

–

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

CONVERSION GAIN (dB)

12

11

10

TA = –40°C

9

8

7

6

5

–6 1086420–2–4

TA = +25°C

TA = +85°C

LO POW ER (dBm)

Figure 21. Power Conversion Gain vs. LO Power

32

09118-021

INPUT P1dB (dB)

12.0

11.6

11.2

10.8

10.4

10.0

9.6

9.2

8.8

8.4

8.0

66

TA = +85°C

TA = +25°C

TA = –40°C

–6 1086420–2–4

LO POW ER (dBm)

Figure 24. Input P1dB vs. LO Power

09118-024

INPUT IP3 (dBm)

INPUT IP2 (dBm)

30

28

26

24

22

20

18

16

–6 1086420–2–4

58

56

54

52

50

48

46

44

42

40

–6 1086420–2–4

TA = –40°C

TA = +25°C

TA = +85°C

LO POW ER (dBm)

Figure 22. Input IP3 vs. LO Power

TA = –40°C

TA = +85°C

LO POW ER (dBm)

Figure 23. Input IP2 vs. LO Power

TA = +25°C

IF/2 SPURIOUS (dBc)

09118-022

IF/3 SPURIOUS (dBc)

09118-023

TA = –40°C

–68

–70

–72

–74

–76

–78

–80

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

T

= +25°C

A

T

= +85°C

A

RF FREQUENCY ( GHz)

Figure 25. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm

60

–62

–64

–66

–68

–70

= +25°C

–72

–74

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

T

A

RF FREQUENCY ( GHz)

T

= +85°C

A

TA = –40°C

Figure 26. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm

09118-025

09118-026

Rev. 0 | Page 10 of 24

ADL5354

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

100

MEAN = 8.6 SD = 0.28%

500

10

80

60

40

20

DISTRIBUTI ON PERCENTAG E (%)

0

8.3 8.78.5 8.68.4

CONVERSION G AIN (dB)

Figure 27. Conversion Gain Distribution

100

MEAN = 26.1 SD = 0.5%

80

60

40

20

DISTRIBUTI ON PERCENTAG E (%)

0

23 24 25 26 2827

INPUT IP3 (dBm)

Figure 28. Input IP3 Distribution

100

MEAN = 10.6 SD = 0.36%

80

60

40

20

DISTRIBUTI ON PERCENTAG E (%)

400

300

RESISTANCE

200

RESISTANCE (Ω)

100

CAPACITANCE

0

30 43038033028023018013080

09118-027

IF FREQUENCY (MHz)

8

6

4

CAPACITANCE (pF )

2

0

09118-030

Figure 30. IF Output Impedance (R Parallel, C Equivalent)

0

–3

–6

–9

–12

–15

–18

RF RETURN LOSS (dB)

–21

–24

–27

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

09118-028

RF FREQUENCY ( GHz)

09118-031

Figure 31. RF Return Loss, Fixed IF

0

–5

–10

–15

–20

–25

LO RETURN LOSS (dB)

–30

SELECTED

UNSELECTED

0

10.0 10.3 10.6 10. 9 11.2

INPUT P1dB (dBm)

Figure 29. Input P1dB Distribution

09118-029

Rev. 0 | Page 11 of 24

–35

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50

LO FREQUENCY (GHz)

Figure 32. LO Return Loss, Selected and Unselected

09118-132

ADL5354

–

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

60

55

50

45

40

LO SWITCH ISOLATION (dB)

35

30

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

30

–31

–32

–33

–34

–35

–36

–37

RF-TO-IF ISOLATION (dB)

–38

–39

–40

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

0

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

TA = –40°C

= +85°C

T

A

= +25°C

T

A

RF FREQUENCY ( GHz)

09118-133

Figure 33. LO Switch Isolation vs. RF Frequency

= +85°C

T

A

= +25°C

T

A

TA = –40°C

RF FREQUENCY ( GHz)

09118-034

Figure 34 RF-to-IF Isolation vs. RF Frequency

30

–32

–34

–36

–38

–40

–42

LO-TO- RF LEAKAGE (dBm)

–44

–46

–48

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50

TA = –40°C

T

= +25°C

A

T

= +85°C

A

LO FREQUENCY (GHz)

Figure 36. LO-to-RF Leakages vs. LO Frequency

0

–5

–10

–15

–20

–25

–30

–35

2 × LO LEAKAGE (dBm)

–40

–45

–50

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50

LO FREQUENCY (GHz)

2 × LO-TO -RF

2 × LO-TO-IF

Figure 37. 2 × LO Leakage vs. LO Frequency

30

09118-036

09118-037

–5

–10

–15

–20

–25

–30

LO-TO -IF LEAKAG E (dBm)

–35

–40

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50

TA = –40°C

T

= +85°C

A

LO FREQUENCY (GHz)

T

A

Figure 35. LO-to-IF Leakage vs. LO Frequency

= +25°C

09118-035

–35

–40

–45

–50

–55

3 × LO LEAKAGE (dBm)

–60

–65

–70

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50

LO FREQUENCY (GHz)

3 × LO-T O-RF

3 × LO-TO-IF

Figure 38. 3 × LO Leakage vs. LO Frequency

09118-038

Rev. 0 | Page 12 of 24

ADL5354

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ, Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

10

18

0.30

9

8

7

6

CONVERSION GAIN (dB)

5

4

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65

RF FREQUENCY (G Hz)

VGS = 000 VGS = 011 VGS = 100 VGS = 110

16

14

12

10

SSB NOISE FIGURE (dB)

8

6

Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for

Various VGS Settings

20

18

16

14

12

INPUT P1dB (dBm)

10

8

6

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.702.65

RF FREQUENCY (G Hz)

VGS = 000 VGS = 011 VGS = 100 VGS = 110

32

29

26

23

20

INPUT IP3 (dBm)

17

14

11

Figure 40. Input P1dB and Input IP3 vs. RF Frequency for Various VGS Settings

14

32

0.25

0.20

0.15

0.10

SUPPLY CURRENT (mA)

0.05

09118-039

IF BIAS SUPPLY CURRENT

LO BIAS SUPP LY CURRENT

0

0.6 0.7 0.8 0.9 1.0 1.1 1. 2 1.3 1.5 1. 71.4 1.6 1.8

BIAS RESIST OR VALUE (kΩ)

09118-142

Figure 42. LO and IF Supply Current vs. IF and LO Bias Resistor Value

16

15

14

13

12

11

10

9

8

7

CONVERSION G AIN AND SSB NOIS E FIGURE (dB)

6

0.6 0.7 0.9 1.1 1.3 1.60.8 1. 0 1.2 1.4 1.81.5 1. 7

09118-040

INPUT IP3

SSB NOISE FIGURE

CONVERSION G AIN

IF BIAS RESISTOR VALUE (kΩ)

30

27

24

21

18

15

12

INPUT IP3 (dBm)

9

6

3

0

09118-042

Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias

Resistor Value

62

13

12

11

10

9

8

7

CONVERSION G AIN AND SSB NOIS E FIGURE (dB)

6

0.6 0.7 0.9 1.1 1.3 1.60.8 1. 0 1.2 1.4 1.81.5 1. 7

LO BIAS RESISTOR VALUE (kΩ)

INPUT IP3

SSB NOISE FIGURE

CONVERSION G AIN

29

26

23

20

17

INPUT IP3 (dBm)

14

11

8

09118-041

Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias

Resistor Value

Rev. 0 | Page 13 of 24

TA = –40°C

60

58

56

54

52

IF CHANNEL-T O-CHANNEL ISOLATIO N (dB)

50

TA = +25°C

TA = +85°C

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

RF FREQUENCY ( GHz)

09118-043

Figure 44. IF Channel-to-Channel Isolation vs. RF Frequency

ADL5354

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V, and Z

= 50 , unless otherwise noted.

O

208

206

204

202

200

198

196

194

SUPPLY CURRENT (mA)

192

190

188

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = –40°C

TA = +25°C

TA = +85°C

RF FREQUENCY ( GHz)

Figure 45. Supply Current vs. RF Frequency at 3.3 V

15

13

11

9

7

5

3

1

CONVERSION GAIN (dB)

–1

–3

–5

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = +25°C

RF FREQUENCY ( GHz)

TA = –40°C

TA = +85°C

Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V

25

09118-044

09118-045

60

TA = +25°C

50

40

TA = +85°C

30

TA = –40°C

INPUT IP2 (dBm)

20

10

0

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

RF FREQUENCY ( GHz)

Figure 48. Input IP2 vs. RF Frequency at 3.3 V

8

6

4

2

0

–2

–4

INPUT P1dB (dBm)

–6

TA = –40°C

–8

–10

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = +85°C

RF FREQUENCY ( GHz)

TA = +25°C

Figure 49. Input P1dB vs. RF Frequency at 3.3 V

22

09118-047

09118-048

20

15

10

INPUT IP3 (dBm)

5

0

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

TA = +25°C

RF FREQUENCY ( GHz)

Figure 47. Input IP3 vs. RF Frequency at 3.3 V

TA = –40°C

TA = +85°C

18

16

14

12

SSB NOISE FIGURE (dB)

10

8

6

2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70

09118-046

TA = –40°C

RF FREQUENCY ( GHz)

TA = +85°C

TA = +25°C

09118-049

Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V

Rev. 0 | Page 14 of 24

ADL5354

SPUR TABLES

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm.

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2500 MHz, fLO = 2297 MHz, LO power = 0 dBm, RF power = −10 dBm, VGS0 = VGS1 = VGS2 = 0 V, and Z

= 50 Ω, unless otherwise noted.

O

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −19.7 −28.9 1 −41.5 0.00 −65.2 −51.9 2 −92.6 −95.3 −73.6 −90.2 −84.3 3 <−100 <−100 −77.6 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100

11

<−100 <−100 <−100 <−100 <−100

12 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 14 <−100 <−100 15 <−100

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2500 MHz, fLO = 2297 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kΩ, R2 = R5 = 400 Ω, VGS0 = VGS1 = VG2 = 0 V, and Z

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −26.5 −36.3 1 −40.6 0.00 −58.8 −55.5 2 −87.8 −77.7 −64.2 −79.1 −84.3 3 <−100 <−100 −70.2 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 14 <−100 <−100 15 <−100

= 50 Ω, unless otherwise noted.

O

Rev. 0 | Page 15 of 24

ADL5354

C

CIRCUIT DESCRIPTION

The ADL5354 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size.

The RF subsystem consists of integrated, low loss RF baluns, passive MOSFET mixers, sum termination networks, and IF amplifiers. The LO subsystem consists of an SPDT-terminated FET switch and two multistage limiting LO amplifiers. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 51.

N

M

S

G

M

N

O C

M

35

34

11

12

M

G

M

V

O

D

C

MNIN

MNCT

OMM

VPOS

OMM

VPOS

OMM

DVCT

DVIN

O P V

36

1

2

3

4

5

6

7

8

9

10

S O P V

Figure 51. Simplified Schematic

RF SUBSYSTEM

The single-ended, 50  RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 2200 MHz to 2700 MHz.

The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimal noise to the frequency translation. The only noise

P O N M

33

13

P O V D

E

O

L

N

M

32

31

14

15

E

N

L

O

V

D

S O P V

30

ADL5354

16

S O P V

G L N

C

M

N

29

28

27

LOI2

26

VGS2

25

VGS1

24

VGS0

23

LOSW

22

PWDN

21

VPOS

20

COMM

19

LOI1

17

18

C

G L

N V D

contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 . If operation in a 50  system is desired, the output can be transformed to 50  by using a 4:1 transformer.

The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (No performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.)

LO SUBSYSTEM

The ADL5354 has two LO inputs permitting multiple synthesizers

9118-052

to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses.

The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from −6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power.

The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the

Rev. 0 | Page 16 of 24

ADL5354

system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings.

In addition, when operating with supply voltages below 3.6 V, the ADL5354 has a power-down mode that permits the dc current to drop to ~300 µA.

The logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn.

All pins, including the RF pins, are ESD protected and have been tested to a level of 1500 V HBM and 500 V FICDM.

Rev. 0 | Page 17 of 24

ADL5354

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5354 mixer is designed to downconvert radio frequencies (RF) primarily between 2200 MHz and 2700 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 52 depicts the basic connections of the mixer. It is recommended to ac couple the RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. The RFIN matching network consists of a series 1.5 pF capacitor and a shunt 4.3 nH inductor to provide the optimized RF input return loss for the desired frequency band.

IF PORT

The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss.

The real part of the output impedance is approximately 200 Ω, which matches many commonly used SAW filters without the

need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Tab l e 3 . When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 52.

BIAS RESISTOR SELECTION

The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5) are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance.

MIXER VGS CONTROL DAC

The ADL5354 features three logic control pins, VGS0 (Pin 24), VGS1 (Pin 25), and VGS2 (Pin26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults VGS0, VGS1, and VGS2 to ground.

Rev. 0 | Page 18 of 24

ADL5354

MAIN_IN

C9

Z1 Z2

C3

C2

MAIN_OUTN

C19 C17

C22

VCC

1

2

3

4

5

R1

36 35 34 33 32 31 30 29 28

C33

C8 C21

L1

C27

R10

VCC

C32

T1

L2

R3

L6

MAIN_OUTP

C25 C18

VCC

R2

R12

R7

R14

R11

C16

R16

C34

R17

LO2

VCC

27

26

R13

25

R8

24

R15

23

DIV_IN

VCC

C6 C7

C11

Z3 Z4

GND

VCC

+

C10

6

7

8

9

10 11 12 13 14 15 16 17 18

VCC

C23

R4

C20

DIV_OUTP DIV_OUTN

C30 C31

VCC

R6

L5

C1 C12

C28

R9

L3

C24 C13

L4

C29

T2

ADL5354

VCC

22

21

C26

20

19

C14

R5

C15

LO1

VCC

R19

09118-153

Figure 52. Typical Application Circuit

Rev. 0 | Page 19 of 24

ADL5354

EVALUATION BOARD

An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 53. The evaluation board is fabricated using Rogers®

RO3003 material. Tab le 7 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 54 and Figure 55.

MAIN_IN

DIV_IN

C9

Z1 Z2

VCC

C11

Z3 Z4

C3 C2

C6 C7

VCC

+

GND

C10

MAIN_OUTN

C22

VCC

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

VCC

C23

R10

C33

C19 C17

S O P V

C8 C21

L1

R1

M

M G

M

N

O C

M

C27

VCC

N O N M

T1

L2

R3

L6

P O N M

ADL5354

TOP VIEW

(Not to Scal e)

M

S

G

O

V

P V

D

R4

P M O C

L5

N

O

V

D

VCC

R6

L4

S O P V

MAIN_OUTP

C18

G L N

M

G L V D

C32

C25

E L N

M

E L V D

L3

C24 C13

VCC

R2

C N

LOI2

VGS2

VGS1

VGS0

LOSW

PWDN

VPOS

COMM

LOI1

C N

R5

R13

C26

C14

C16

R12

R16

R7

C34

R8

R14

R17

R11

R15

R19

VCC

C15

LO1

LO2

VCC

C1 C12

C28

C20

DIV_OUTP DIV_OUTN

C30 C31

R9

C29

T2

Figure 53. Evaluation Board Schematic

Rev. 0 | Page 20 of 24

09118-154

ADL5354

Table 7. Evaluation Board Configuration

Components Description Default Conditions

C1, C8, C10, C12, C13, C15, C18, C21, C22, C23, C24, C25, C26

Z1 to Z4, C2, C3, C6, C7, C9, C11

T1, T2, C17, C19, C20, C27 to C33, L1, L2, L4, L5, R3, R6, R9, R10

C14, C16, R15, LOSEL

R19, PWDN

R1, R2, R4, R5, L3, L6, R7, R8, R11 to R14, R16, R17, C34

Power supply decoupling. Nominal supply decoupling consists of a 0.01 µF capacitor to ground in parallel with 10 pF capacitors to ground positioned as close to the device as possible.

RF main and diversity input interface. Main and diversity input channels are ac-coupled through C9 and C11. Z1 to Z4 provide additional component placement for external matching/filter networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns.

IF main and diversity output interface. The open-collector IF output interfaces are biased through the pull-up choke inductors (L1, L2, L4, and L5), leaving R3 and R6 available for additional supply bypassing. T1 and T2 are 4:1 impedance transformers that are used to provide a single-ended IF output interface, and C27 and C28 provide the center tap bypassing. C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled output interface. Remove R9 and R10 for balanced output operation.

LO interface. C14 and C16 provide ac coupling for the LOI1 and LOI2 local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled when the LOSEL jumper is removed. The jumper can be removed to allow the LOSEL interface to be exercised by using an external logic generator.

PWDN interface. When the PWDN 2-pin shunt is inserted, the ADL5354 is powered down. When R19 is open, it pulls the PWDN logic low and enables the device. The jumper can be removed to allow PWDN interface to be exercised using an external logic generator. Grounding the PWDN pin is allowed during nominal operation but is not permitted when supply voltages exceed 3.3 V.

Bias control. R16 and R17 form a voltage divider to provide a 3 V for logic control, bypassed to ground through C34. Resistors R7, R8, R11, R12, R13, and R14 provide resistor programmability of VGS0, VGS1, and VGS2. Typically, these nodes can be hardwired for nominal operation. Grounding these pins is allowed for nominal operation. R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set the bias point for the internal IF amplifiers. L3 and L6 are external inductors used to improve isolation and common-mode rejection.

C10 = 4.7 µF (Size 3216), C1, C8, C12, C21 = 150 pF (Size 0402), C22, C23, C24, C25, C26 = 10 pF (Size 0402), C13, C15, C18 = 0.1 µF (Size 0402)

C2, C7 = 10 pF (Size 0402), C3, C6 = 0.01 µF (Size 0402), C9, C11 = 1.5 pF (Size 0402), Z2, Z4 = 4.3 nH (Size 0402), Z1, Z3 = open (Size 0402)

C17, C19, C20, C29 to C33 = 0.001 µF (Size 0402), C27, C28 = 150 pF (Size 0402), T1, T2 = TC4-1T+ (Mini-Circuits), L1, L2, L4, L5 = 330 nH (Size 0805), R3, R6, R9, R10 = 0 Ω (Size 0402)

C14, C16 = 10 pF (Size 0402), R15 = 10 kΩ (Size 0402), LOSEL = 2-pin shunt

R19 = 10 kΩ (Size 0402), PWDN = 2-pin shunt

R1, R4 = 1.3 kΩ (Size 0402), R2, R5 = 1 kΩ (Size 0402), L3, L6 = 0 Ω (Size 0603), R12, R13, R14 = open (Size 0402), R7, R8, R11 = 0 Ω (Size 0402), R16 = 10 kΩ (Size 0402), R17 = 15 kΩ (Size 0402), C34 = 1 nF (Size 0402)

Figure 54. Evaluation Board Top Layer

09118-056

Rev. 0 | Page 21 of 24

Figure 55. Evaluation Board Bottom Layer

09118-057

ADL5354

OUTLINE DIMENSIONS

PIN 1

INDICATOR

12° MAX

1.00

0.85

0.80

SEATING

PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.28

0.23

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1

5.75

BSC SQ

0.20 REF

0.60 MAX

0.05 MAX

0.02 NOM COPLANARITY

0.08

0.50

BSC

0.75

0.60

0.50

0.60 MAX

28

27

EXPOSED

(BOTTOM V IEW)

19

18

36

PAD

10

4.00 REF

FORPROPERCONNECTIONOF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

Figure 56. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad (CP-36-1)

Dimensions shown in millimeters

PIN 1 INDICATOR

1

3.85

3.70 SQ

3.55

9

0.20 MIN

050808-D

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADL5354ACPZ-R2 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1 ADL5354ACPZ-R7 −40°C to +85°C 36-Lead LFCSP_VQ CP-36-1 ADL5354-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

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ADL5354

NOTES

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ADL5354

NOTES

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Datasheet ADL5354 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

5 V PERFORMANCE

3.3 V PERFORMANCE

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

3.3 V PERFORMANCE

SPUR TABLES

5 V PERFORMANCE

3.3 V PERFORMANCE

CIRCUIT DESCRIPTION

RF SUBSYSTEM

LO SUBSYSTEM

APPLICATIONS INFORMATION

BASIC CONNECTIONS

IF PORT

BIAS RESISTOR SELECTION

MIXER VGS CONTROL DAC

EVALUATION BOARD

OUTLINE DIMENSIONS

ORDERING GUIDE