Datasheet ADL5317 Datasheet (ANALOG DEVICES)

Avalanche Photodiode Bias Controller and

Wide Range (5 nA to 5 mA) Current Monitor

FEATURES

Accurately sets avalanche photodiode (APD) bias voltage

Wide bias range from 6 V to 75 V
3 V-compatible control interface
Monitors photodiode current (5:1 ratio) over six decades
Linearity 0.25% from 10 nA to 1 mA, 0.5% from 5 nA to 5 mA
Overcurrent protection and overtemperature shutdown
Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)

APPLICATIONS

Optical power monitoring and biasing in APD systems
Wide dynamic range voltage sourcing and current

monitoring in high voltage systems

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

COMM16COMM15COMM14COMM

FALT

1

2

3

4

OVERCURRENT

PROTECTION

VSET

VPLV

VPHV

VPHV VCLH

5

PROTECTION

THERMAL

6

30 × V

SET

29 × R

R

GARD VAPD

Figure 1.

7

ADL5317

1313

ADL5317

CURRENT

MIRROR

5:1

I

APD

8

NC

IPDM

I

APD

5

NC

GARD

12

11

10

9

05456-001

The ADL5317 is a high voltage, wide dynamic range, biasing
and current monitoring device optimized for use with
avalanche photodiodes. When used with a stable high voltage
supply (up to 80 V), the bias voltage at the VAPD pin can be
varied from 6 V to 75 V using the 3 V-compatible VSET pin.
The current sourced from the VAPD pin over a range of 5 nA to
5 mA is accurately mirrored with an attenuation of 5 and
sourced from the IPDM monitor output. In a typical
application, the monitor output drives a current input
logarithmic amplifier to produce an output representing the
optical power incident upon the photodiode. The photodiode
anode can be connected to a high speed transimpedance
amplifier for the extraction of the data stream.

A signal of 0.2 V to 2.5 V with respect to ground applied at the
VSET pin is amplified by a fixed gain of 30 to produce the 6 V
to 75 V bias at Pin VAPD. The accuracy of the bias control
interface of the ADL5317 allows for straightforward calibration,
thereby maintaining a constant avalanche multiplication factor
of the photodiode over temperature. The current monitor

output, IPDM, maintains its high linearity vs. photodiode
current over the full range of APD bias voltage. The current
ratio of 5:1 remains constant as V

SET

and V

are varied.

PHV

The ADL5317 also offers a supply tracking mode compatible
with adjustable high voltage supplies. The VAPD pin accurately
follows 2.0 V below the VPHV supply pin when VSET is tied to
a voltage from 3.0 V to 5.5 V (or higher with a current limiting
resistor), and the VCLH pin is open.

Protection from excessive input current at VAPD as well as
excessive die temperature is provided. The voltage at VAPD falls
rapidly from its setpoint when the input current exceeds 18 mA
nominally. A die temperature in excess of 140°C will cause the
bias controller and monitor to shut down until the temperature
falls below 120°C. Either overstress condition will trigger a logic
low at the FALT pin, an open collector output loaded by an
external pull-up to an appropriate logic supply (1 mA max).

The ADL5317 is available in a 16-lead LFCSP package and is
specified for operation from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADL5317

TABLE OF CONTENTS

Features .............................................................................................. 1

VCLH Interface .......................................................................... 10

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ........................................................................ 9

Bias Control Interface.................................................................. 9

GARD Interface............................................................................ 9

REVISION HISTORY

7/05—Revision 0: Initial Version

Noise Performance ..................................................................... 10

Response Time............................................................................ 10

Device Protection ....................................................................... 10

Applications..................................................................................... 11

Supply Tracking Mode............................................................... 11

Translinear Log Amp Interfacing............................................. 11

Characterization Methods ........................................................ 12

Evaluation Board ............................................................................ 14

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

ADL5317

SPECIFICATIONS

V

= 78 V, V

PHV

Table 1.

Parameter Min Typ Max Unit Conditions

CURRENT MONITOR OUTPUT

Current Gain from VAPD to IPDM

0.193 0.207

Wideband Noise at IPDM

Output Voltage Range

APD BIAS CONTROL VSET (Pin 2), VAPD (Pin 8)

Specified V

VAPD to GARD Offset 3 mV
Specified Input Current Range, I
VSET to VAPD Incremental Gain 29.7 30 30.3 V/V 0.2 V < V
VSET Input Referred Offset, 1σ 0.5 mV
VSET Voltage Range 0.2 5.5 V
Incremental Input Resistance at VSET 100 MΩ V
Input Bias Current at VSET 0.3 µA V
V

Settling Time, 5%

APD

V

Supply Tracking Offset (Below V

APD

OVERSTRESS PROTECTION FALT (Pin 1)

VAPD Current Compliance Limit 14 18 21 mA V
Thermal Shutdown Trip Point 140

Thermal Hysteresis 20
FALT Output Low Voltage 0.8 V Fault condition, load current < 1 mA

POWER SUPPLIES

Low Voltage Supply 4 6 V VPLV
Quiescent Current 0.7 0.84 mA Independent of I
High Voltage Supply 10 80 V VPHV
Quiescent Current 2.3 2.9 mA I

3.6 4.5 mA I

1

Tested 1.5 V < V

= 5 V, V

PLV

Voltage Operating Range

APD

< 2.5 V, guaranteed operation 0.2 V < V

SET

APD

= 60 V, I

APD

= 5 A, TA = 25°C, unless otherwise noted.

APD

)

PHV

IPDM (Pin 11)

0.198 0.200 0.202 A/A

0.25 1.6 % 10 nA < I

0.5 3.0 % 5 nA < I
2 kHz I
2 MHz I
10 nA

0 V
0 V

6 V
V

− 35 V

PHV

V

− 35 75 V 76.5 V < V

PHV

PLV

/ 3 V

APD

− 1.5 V 10 V < V

PHV

− 1.5 V 41 V < V

PHV

V

= 25°C

T

A

−40°C < T

APD

= 5 nA, V

APD

= 5 µA, V

APD

= 5 µA, C

I

APD

= 40 V, V

V

PHV

V

> 3 × V

APD

V

< 3 × V

APD

< +85°C

A

< 1 mA Nonlinearity

APD

< 5 mA

= 60 V, V

PHV

= 60 V, V

PHV

= 2 nF, BW = 10 MHz,

GRD

= 30 V

APD

PLV

PLV

< 41 V

PHV

< 76.5 V

PHV

< 80 V

PHV

= 30 V Small-Signal Bandwidth

APD

= 30 V

APD

5n 5m A Flows from VAPD pin

1

< 2.5 V

SET

= 2.0 V

SET

= 2.0 V, flows from VSET pin

SET

20 sec

100 sec

1.90 2.0 2.15 V V

°C
°C

< 2.5 V.

SET

= 1.6 V to 2.4 V, C

V

SET

= 30 V

V

APD

= 2.4 V to 1.6 V, C

V

SET

= 30 V

V

APD

= 5.0 V, 10 V < V

SET

= 2.0 V, V

SET

APD

= 2 nF, V

GRD

= 2 nF, V

GRD

< 77 V

PHV

deviation of 500 mV

Die temperature rising

VPHV (Pin 4, Pin 5), VPLV (Pin 3)

APD

= 5 A, V

APD

= 1 mA, V

APD

= 60 V

APD

APD

= 60 V

= 60 V,

PHV

= 60 V,

PHV

Rev. 0 | Page 3 of 16

ADL5317

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 80 V
Input Current at VAPD 25 mA
Internal Power Dissipation 615 mW

θJA (Soldered Exposed Paddle)

Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C

65°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 4 of 16

ADL5317

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

COMM

COMM

COMM

COMM
14

13

15

16

PIN 1
INDICATOR

1FALT
2VSET

ADL5317

3VPLV

TOP VIEW

(Not to Scale)

4VPHV

5

6

VPHV

VCLH

NC = NO CONNECT

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 FALT Open Collector (Active Low) Logic Output. Indicates an overcurrent or overtemperature condition.
2 VSET APD Bias Voltage Setting Input. Short to VPLV for supply tracking mode.
3 VPLV Low Voltage Supply, 4 V to 6 V.
4, 5 VPHV High Voltage Supply, 10 V to 80 V.
6 VCLH Can be shorted to VPHV for extended linear operating range. No connect for supply tracking mode.
7, 9 GARD

Guard pin tracks VAPD pin and filters setpoint buffer noise (with External Capacitor C

shielding of VAPD trace. Capacitive load only.
8 VAPD APD Bias Voltage Output and Current Input. Sources current only.
10, 12 NC Optional shielding of IPDM trace. No connection to die.
11 IPDM Photodiode Monitor Current Output. Sources current only. Current at this node is equal to I
13 to 16 COMM Analog Ground.

12 NC
11 IPDM
10 NC
9 GARD

8

7

VAPD

GARD

05456-002

to COMM). Optional

GRD

/5.

APD

Rev. 0 | Page 5 of 16

ADL5317

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 78 V, V

PHV

10m 2.0

1m 1.5

100μ 1.0

10μ 0.5

1μ 0

(Amperes)

100n –0.5

PDM

I

10n –1.0

1n –1.5

100p –2.0

1n 10m

(V)

APD

V

2.150

2.125

2.100

2.075

2.050

(V)

2.025

APD

2.000

– V

1.975

PHV

V

1.950

1.925

1.900

1.875

1.850

Figure 5. V

= 5 V, V

PLV

+85°C

+25°C

+85°C

+25°C
–40°C

10n 100n 1μ 10μ 100μ 1m

Figure 3. I

PDM

Normalized to I

80

70

60

V

= 78V, +25°C

PHV

50

V

= 78V, –40°C

PHV

40

30

V

= 45V,

PHV

–40°C

20

10

0

0 3.0

V
V

0.5 1.0 1.5 2.0 2.5

Figure 4. V

V

= 78 V and V

PHV

–40°C

10 20 30 40 50 60 70 80

09

Supply Tracking Offset vs. V

APD

–40°C

= 60 V, I

APD

I

APD

(Amperes)

= 5 A, TA = 25°C, unless otherwise noted.

APD

Linearity for Multiple Temperatures,

= 5 A, 25°C

APD

V

= 78V, +85°C

PHV

= 45V, +85°C

PHV

= 45V, +25°C

PHV

V

(V)

SET

vs. V

APD

for Multiple Temperatures,

SET

= 45 V, I

PHV

+25°C

+85°C

(V)

V

PHV

= 5 A

APD

for Multiple Temperatures

PHV

LINEARITY (%)

PDM

I

05456-003

05456-006

05456-005

0

10m

1m

100μ

V

= 78V, V

PHV

10μ

1μ

(Amperes)

100n

PDM

I

V

PHV

V

APD

10n

1n

100p

1n 10m10n 100n 1μ 10μ 100μ 1m

Figure 6. I

APD

V

= 45V, V

PHV

= 10V,
= 6V

Linearity for Multiple Values of V

PDM

Normalized to I

31.0

30.8

30.6

30.4

30.2

30.0

GAIN (V/V)

29.8

29.6

29.4

29.2

29.0
0 3.0

V
V
V

0.5 1.0 1.5 2.0 2.5

Figure 7. Incremental Gain from V

Multiple Temperatures, I

70 0.030

60 0.020

50 0.010

40 0

(V)

APD

V

30 –0.010

20 –0.020

10 –0.030

0 –0.040

1n 10m

Figure 8. V

78/60 +25°C
45/32 +25
10/6 +25

V

= 78V, V

PHV

V

PHV

V

PHV

10n 100n 1μ 10μ 100μ 1m

vs. I

APD

APD

= 45V, V

APD

= 10V, V

APD

for Multiple Temperatures and Values of V

APD

V

= 78V, V

PHV

V

PHV

V

PHV

= 60V

= 32V

APD

(Amperes)

I

APD

= 5 A, V

APD

= 45V, +85°C

PHV

= 45V, +25°C

PHV

= 45V, –40°C

PHV

V

SET

= 5 A, V

APD

78/60 –40
45/32 –40

°

C

10/6 –40

°

C
= 60V; +85°C, +25°C, –40°C

= 32V; +85°C, +25°C, –40°C

= 6V; +85°C, +25°C, –40°C

I

(Amperes)

APD

= 45V, V
= 10V, V

=78 V, V

PHV

(V)

SET

°

C

°

C

°

C

to V

PHV

APD
APD
APD

= 60V
= 32V
= 6V

and V

APD

= 60 V

APD

V

= 78V, +85°C

PHV

V

= 78V, +25°C

PHV

V

= 78V, –40°C

PHV

vs. V

APD

SET

= 78 V and 45 V

78/60 +85
45/32 +85
10/6 +85

°

for

°

C

°

C

C

PHV

PHV

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

,

and V

LINEARITY (%)

PDM

I

05456-007

VARIATION (V)

APD

V

05456-008

APD

05456-004

Rev. 0 | Page 6 of 16

ADL5317

3

2

+85°C
+25°C
–40°C

3

2

+85°C
+25°C
–40°C

1

0

LINEARITY (%)

–1

PDM

I

–2

–3

1n

10n 100n 1μ 10μ 100μ 1m

Figure 9. I

100pA

10pA

1pA

100fA

(AMPERES rms/√Hz)

10fA

1fA

Linearity for Multiple Temperatures and Devices

PDM

=75 V, V

V

PHV

1k 10M

APD

500μA

I

(Amperes)

APD

= 60 V, Normalized to I

5mA

10k 100k 1M

FREQUENCY (Hz)

5nA

= 5 µA, 25°C

APD

500nA

50nA

Figure 10. Output Current Noise Density vs. Frequency for

, C

Multiple Values of I

30

20

10

DRIFT (mV)

–10

APD

V

–20

–30

–40

AVERAGE

0

–40 90

–30 –20 –10 0 10 20 30 40 50 60 70 80

= 2 nF, V

APD

GARD

+3 SIGMA

–3 SIGMA

TEMPERATURE (°C)

Figure 11. Temperature Drift of V

= 40 V, V

PHV

, 3 σ to Either Side of Mean

APD

50μA

APD

5μA

= 30 V

10m

05456-010

05456-035

05456-042

1

0

LINEARITY (%)

–1

PDM

I

–2

PDM

APD

10m

vs. I

in

100M

05456-011

PDM

05456-036

,

05456-043

–3

1n

10n 100n 1μ 10μ 100μ 1m

Figure 12. I

(%)

V

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Linearity for Multiple Temperatures and Devices

PDM

= 45 V, V

PHV

1n 1m

APD

10n 100n 1μ 10μ 100μ

I

(Amperes)

APD

= 32 V, Normalized to I

(Amperes)

I

PDM

= 5 µA, 25°C

APD

Figure 13. Output Wideband Current Noise as a Percentage of I

= 2 nF, V

C

GARD

10

5

0

–5

–10

–15

–20

NORMALIZED RESPONSE (dB)

–25

–30

10 100 1k 10k 100k 1M 10M

Figure 14. Small Signal AC Response from I

Decades from 5 nA to 50 A, V

= 40 V, V

PHV

5nA

FREQUENCY (Hz)

= 30 V, BW = 10 MHz

APD

500nA

50nA

to I

APD

= 60 V, V

PHV

APD

5μA

, for I

PDM

= 30 V

50μA

Rev. 0 | Page 7 of 16

ADL5317

10m

75

1m

100μ

10μ

1μ

(Amperes)

100n

PDM

I

10n

1n

10n

0 400

Figure 15. Pulse Response from I

30

25

20

(%)

15

10

5

0

29.7 29.8 29.9 30.0 30.1 30.2 30.3

100μA TO 1mA: T-RISE =
<0.5μs, T-FALL = <0.5μs

10μA TO 100μA: T-RISE =
<0.5μs, T-FALL = <0.5μs

1μA TO 10μA: T-RISE =
<0.5μs, T-FALL = <0.5μs

100nA TO 1μA: T-RISE =
<1μs, T-FALL = <1.5μs

10nA TO 100nA: T-RISE =
<10μs, T-FALL = <15μs

1nA TO 10nA: T-RISE =
<100μs, T-FALL = <150μs

50 100 150 200 250 300 350

from 5 nA to 5 mA, V

TIME (μs)

to I

APD

= 60 V, V

PHV

SLOPE (V/V)

PDM

for I

APD

APD

= 30 V

N = 2021
MEAN = 29.959
SD = 0.0316714

Figure 16. Distribution of Incremental Gain from V

from 1.5 V to 2.4 V, I

V

SET

APD

= 5 A

in Decades

to V

for

SET

APD

05456-016

05456-038

70

65

60

, VOLTAGE (V)

APD

55

V

50

45

0

50 100 150 200 250 300 350

Figure 17. Pulse Response from V

in Decades from 5 nA to 5 mA, C

for I

APD

20

15

(%)

10

5

0

0.1980 0.1985 0.1990 0.1995 0.2000 0.2005 0.2010 0.2015 0.2020

Figure 18. Distribution of I

PDM/IAPD

TIME (μs)

SET

I

PDM/IAPD

at V

to V

GARD

PHV

5mA

500μA
50μA

500nA

5μA

(V

Pulsed 1.6 V to 2.4 V)

APD

SET

= 2 nF, V

PHV

N = 2029
MEAN = 0.200035
SD = 0.000454209

(A/A)

= 60 V, V

SET

50nA

= 60 V, V

= 1.0 V, I

5nA

APD

= 50 A

APD

400

= 30 V

05456-017

05456-039

Rev. 0 | Page 8 of 16

ADL5317

THEORY OF OPERATION

The ADL5317 is designed to address the need for high voltage
bias control and precision optical power monitoring in optical
systems using avalanche photodiodes. It is optimized for use
with the Analog Devices, Inc. family of translinear logarithmic
amplifiers that take advantage of the wide input current range
of the ADL5317. This arrangement allows the anode of the
photodiode to connect directly to a transimpedance amplifier
for the extraction of the data stream without need for a separate
optical power monitoring tap.

Figure 19 shows the basic

connections for the ADL5317.

14

15

FALT

LOW VOLTAGE

SUPPLY

0.1μF

10kΩ

V

SET

0Ω

0.01μF

0.01μF

0.1μF

HIGH VOLTAGE

1

2

3

4

SUPPLY

FALT

VSET

VPLV

VPHV

0Ω

COMM16COMM

COMM13COMM

ADL5317

VPHV6VCLH7GARD8VAPD

5

I

APD

APD

NC

IPDM

NC

GARD

1kΩ

12

11

10

9

1nF

MIRROR CURRENT

OUTPUT

0.01μF

Figure 19. Basic Connections

At the heart of the ADL5317 is a precision attenuating current
mirror with a voltage following characteristic that provides
precision biasing at the monitor input. This architecture uses a
JFET-input amplifier to drive the bipolar mirror and maintain
stable V

voltage, while offering very low leakage current at

APD

the VAPD pin. The mirror attenuates the current sourced
through VAPD by a factor of 5 to limit power dissipation under
high voltage operation and delivers the mirrored current to the
IPDM monitor output pin. Proprietary mirroring and cascoding
techniques maintain the linearity vs. the input current and
stability of the mirror ratio over a very wide range of supply and
V

voltages.

APD

05456-021

The VAPD adjustment range for a given high voltage supply,
VPHV, is limited to approximately 33 V (or less, for V

PHV

<
41 V). For example, VAPD is specified from 40 V to 73.5 V for
a 75 V supply, and 6 V (the minimum allowed) to 28.5 V for a
30 V supply. When VAPD is driven to its lower clamp voltage
via the VSET pin, the mirror can continue to operate, but the
VAPD bias voltage no longer responds to incremental changes
in V

.

SET

GARD INTERFACE

The GARD pins primarily shield the VAPD trace from leakage
currents and filter noise from the bias control interface. GARD
is driven by the V
resistor forms an RC network with an external capacitor from
GARD to ground that filters the thermal noise of the amplifier’s
feedback network and provides additional power supply
rejection. The series components, R
Figure 20, are necessary to ensure essential high frequency
compensation at the VAPD input pin over the full operating
range of the ADL5317.

Figure 20. Filtering VAPD Using the GARD Interface

The cutoff frequency of the GARD interface for small signals
and noise is defined by

=

F

3dB

where:

amplifier through a 20 k resistor. This

SET

and C

COMP

ADL5317

GARD

20kΩ

VAPD

V

SET

X30

AMPLIFIER

1

××

k202π

C

GRD

COMP

C

R

COMP

C

GRD

COMP

, shown in

05456-022

BIAS CONTROL INTERFACE

In the linear operating mode, the voltage at VAPD is referenced
to ground, and follows the simplified equation

= 30 × V

V

APD

GARD is driven to the same potential as VAPD for use in
shielding the highly sensitive VAPD pin from leakage currents.
The GARD and VAPD pins are clamped to within approxi­mately 40 V below the VPHV supply to prevent internal device
breakdowns, and VAPD is clamped to within a volt of GARD.

SET

Rev. 0 | Page 9 of 16

F

is the cutoff frequency of the low-pass filter formed by the

3dB

on-board 20 k and C

C

is the filter capacitor installed from GARD to ground.

GRD

A larger value for C

.

GRD

(up to approximately 0.01 F) provides

GRD

superior noise performance at the lowest input current levels,
but also slows the response time to changes in V

The pull-up of the V

amplifier is limited to approximately

SET

SET

.

2.5 mA, resulting in a slew limited region for large signals,
followed by an RC decay for the final 700 mV. This decay
corresponds to the above single-pole equation. The pull-down
of the V

amplifier is largely resistive, equivalent to

SET

approximately 90 k in parallel with 70 A to ground.

ADL5317

For small input currents, this pull-down must discharge not
only C

but also C

GRD

and VAPD diodes). The final 700 mV of settling for lower input
currents is dominated by the input current discharge of C
For larger input currents, the V
only C
(see

, since I

GRD

Figure 17).

Any dc load on GARD alters the gain from VSET to VAPD due
to the 20 k source impedance. Note that the load presented by
a multimeter or oscilloscope probe is sufficient to alter the VSET to
VAPD gain, and must be taken into account.

The GARD pin is internally clamped to approximately 40 V
below VPHV to prevent device breakdown, and VAPD is
clamped to within 1 V of GARD. For this reason, any short­circuit to ground from GARD or VAPD must be avoided for
VPHV voltages above 36 V, or device damage results.

VCLH INTERFACE

The voltage clamp high-side pin (VCLH) is typically connected
to VPHV for linear operation of the VSET interface and left
open for supply tracking mode (see the
section for more details). The voltage at VCLH represents a
high-side clamp above which the V
V

) is not allowed to rise. The voltage is internally set to a

APD

temperature stable 2.0 V below V

When V

is pulled up to 3 V or higher and VCLH is open,

SET

VAPD follows 2.0 V below VPHV as VPHV is varied. This
bypasses the linear VSET interface for applications where an
adjustable high voltage supply is preferred (see the
section). The 25 k source resistance allows VCLH to be
shorted to VPHV, removing the 2.0 V high-side clamp for
extended linear operating range (up to V
mode. VCLH can be left open in linear mode if a fixed clamp
point is desired.

NOISE PERFORMANCE

The noise performance for the ADL5317, defined as the rms
noise current as a fraction of the output dc current, improves
with increasing signal current. This partially results from the
relationship between quiescent collector current and shot noise
in bipolar transistors. At lower signal current levels, the noise
contribution from the V
appearing at VAPD dominate the noise behavior. Filtering the
VSET interface noise through an external capacitor from GARD
to ground, as well as selecting optimal external compensation

at the VAPD pin (through the GARD

COMP

amplifier pull-down discharges

SET

is capable of discharging C

APD

Supply Tracking Mode

amplifier output (and

SET

through a 25 k resistor.

PHV

− 1.5 V) in linear

PHV

amplifier and other noise sources

SET

quickly

COMP

Applications

COMP

.

components on VAPD, minimizes the amount of voltage noise
at VAPD that is converted to current noise at IPDM.

RESPONSE TIME

The response time for changes in signal current is fundamentally a
function of signal current, with small-signal bandwidth increasing
roughly in proportion to signal current. The value of the exter­nal compensating capacitor on VAPD strongly affects response
time, although the value must be chosen to maintain stability
and prevent noise peaking. Response time for changes in V

SET

voltage is primarily a function of the filter capacitance at the
GARD pin. See the

GARD Interface section for further details.

Figure 15 and Figure 17 show the response of the ADL5317 to
pulsed input current and V

voltage, respectively.

SET

DEVICE PROTECTION

Thermal and overcurrent protection are provided with fault
detection. The FALT pin is an open collector logic output
(active low) designed to assert when an overtemperature or
overcurrent condition is detected. A pull-up resistor to an
appropriate logic supply is required, and its value should be
chosen such that no more than 1 mA output current is used
when active.

When the die temperature of the ADL5317 exceeds 140°C
(typical), the current mirror shuts down, causing the bias
voltage at VAPD to be pulled down, and FALT asserts. FALT
remains asserted until the temperature falls below the trigger
temperature minus the thermal hysteresis (20°C typical), after
which the mirror and biaser again power up. The cycle may
repeat until the cause of the fault is removed.

When the input current, I

, exceeds 18 mA (typical), the

APD

current mirror and biaser attempt to maintain the threshold
current by allowing the V

voltage to fall to a point of

APD

equilibrium. In other words, the threshold current represents
the compliance of the bias voltage; in this case, the current at
which V

falls 500 mV below its midrange current value.

APD

FALT asserts, but is not guaranteed to remain asserted, as
VAPD is pulled down toward ground. If V
as in the case of a momentary short-circuit or being driven by a
programmable current source exceeding the threshold current,
bias current generators critical to device operation become satu­rated. This causes FALT to deassert and the mirror to shut down.
The mirror does not power up until the input current falls below
the current limit of the V

amplifier (approximately 2.5 mA),

SET

allowing VAPD to be pulled up to its normal operating level.
FALT pin can be grounded if the logic signal is not used.

falls below ~3 V,

APD

The

Rev. 0 | Page 10 of 16

ADL5317

V

APPLICATIONS

The ADL5317 is primarily designed for wide dynamic range
applications simplifying APD bias circuit architecture. Accurate
control of the bias voltage across the APD becomes critical to
maintain the proper avalanche multiplication factor as the
temperature and input power vary.

Figure 21 shows how to use
the ADL5317 with an external temperature sensor to monitor
the ambient temperature of the APD. Using a look-up table and
DAC to drive VSET, it is possible to apply the correct V

APD

for
the conditions. Note that Pin 9, Pin 10, and Pin 12 to Pin 15
were removed for simplification.

LOGIC

SUPPLY

COMM

FALT

LOOK-UP

TABLE

AND DAC

TEMPERATURE

SENSOR

5V

OVERCURRENT

PROTECTION

THERMAL

PROTECTION

VSET

VPLV

VPHV VCLH GARD VAPD

75V

FROM DC–DC

CONVERTER

30 × V

29 × R

R

C

GRD

CURRENT

MIRROR

5:1

SET

I

APD

APD

IPDM

I

APD

5

TRANSLINEAR

LOG AMP

TIA RECEIVER

OPTICAL
POWER

DATA

Figure 21. Typical APD Biasing Application Using the ADL5317

In this application, the ADL5317 is operating in linear mode.
The bias voltage to the APD, delivered at Pin VAPD, is
controlled by the voltage (V
VAPD is equal to 30 × V

) at Pin VSET. The bias voltage at

SET

.

SET

The range of voltages available at VAPD for a given high voltage
supply is limited to approximately 33 V (or less, for V

< 41 V).

APD

This is because the GARD and VAPD pins are clamped to within
~40 V below VPHV, preventing internal device breakdowns.

The input current, I

, is divided down by a factor of 5 and

APD

precisely mirrored to Pin IPDM. This interface is optimized for
use with any of the Analog Devices translinear logarithmic
amplifiers (for example, the

AD8304 or AD8305) to offer a

precise, wide dynamic range measurement of the optical power
incident upon the APD.

If a voltage output is preferred at IPDM, a single external
resistor to ground is all that is necessary to perform the
conversion. Voltage compliance at IPDM is limited to V
V

/3, whichever is lower.

APD

PLV

or

05456-023

SUPPLY TRACKING MODE

Some applications for the ADL5317 require a variable dc-to-dc
converter or alternative variable biasing sources to supply
VPHV. For these applications, it is necessary to configure the
ADL5317 for supply tracking mode, shown in

Figure 22. In this
mode, the VSET interface is bypassed. However, the full
functionality of the precision current mirror remains available.

5V

13

13

NC

CURRENT

MIRROR

5:1

IPDM

NC

GARD

8V TO 75V
BIAS ACROSS APD

TIA

12

11

LOG

10

9

DATA

RSSI

OUT

3V TO 5.5

4V TO 6V

10V TO 77V

COMM16COMM15COMM14COMM

FALT

1

OVERCURRENT

PROTECTION

THERMAL

PROTECTION

VSET

2

3

VPLV

4

VPHV

VPHV VCLH GARD VAPD

5 6 7 8

VARIABLE

DC SUPPLY

30 × V

SET

29 × R

R

Figure 22. Supply Tracking Mode

In supply tracking mode, the V

amplifier is pulled up beyond

SET

its linear operating range and effectively placed into a controlled
saturation. This is done by applying 3.0 V to 5.5 V at the VSET
pin. It is also necessary to remove the connection from VCLH,
which defines the saturation point, to VPHV. Once the ADL5317
is placed into supply tracking mode, V
below V

PHV

.

is clamped to 2.0 V

APD

For those designs where it is desirable to drive VSET from the
VPLV supply, it is necessary to place a 100 kΩ resistor between
VSET and VPLV for V

> 5.5 V. This is due to input current

PLV

limitations on the VSET pin.

TRANSLINEAR LOG AMP INTERFACING

The monitor current output, IPDM, of the ADL5317 is
designed to interface directly to an Analog Devices translinear
logarithmic amplifier, such as the

ADL5306. Figure 23 shows the basic connections necessary for

interfacing the ADL5317 to the
the designer is can use the full current mirror range of the
ADL5317 for high accuracy power monitoring.

AD8304, AD8305, or

AD8305. In this configuration,

05456-024

Rev. 0 | Page 11 of 16

ADL5317

V

P_LOW

10kΩ

0.1μF

AD8305 INPUT

COMPENSATION

NETWORK

14

15

16

M

1

I

PDM

1mA

VRDZ

2

VREF

3

IREF

4

INPT

0.1μF

14

15

16

FALT

VSET

VPLV

VPHV

0Ω

OMM

COMM

C

COMM13COMM

ADL5317

VPHV6VCLH7GARD8VAPD

5

I

APD

NC

IPDM

NC

GARD

1kΩ

APD

1nF

TIA

1

0.01μF

0.01μF

0.1μF
V

2

3

4

P_HIGH

V

SET

0Ω

1nF

2.5V

1kΩ

12

11

10

9

0.01μF

DATA
PATH

4.7nF

200kΩ

2kΩ

10nA TO

COMM

COMM

COMM13COM

AD8305

VSUM6VNEG7VNEG8VPOS

5

3V TO 12V

VOUT

SCAL

BFIN

VLOG

12

11

10

9

OUTPUT

= 0.2 ×

V

OUT

LOG

10

(I

/1nA)

PDM

05456-025

Figure 23. Interfacing the ADL5317 to the AD8305 for High Accuracy APD Power Monitoring

Measured rms noise voltage at the output of the AD8305 vs.
input current is shown in

Figure 24 for the AD8305 by itself
and in cascade with the ADL5317. The relatively low noise
produced by the ADL5317, combined with the additional noise
filtering inherent in the frequency response characteristics of
the

AD8305, result in minimal degradation to the noise

performance of the

5.5m

5.0m

4.5m

4.0m

3.5m

3.0m

2.5m

(V rms)

2.0m

1.5m

1.0m

0.5m
0

AD8305.

AD8305 AND

ADL5317

AD8305 ONLY

10n 1m

100n 1μ 10μ 100μ

(A)

05456-034

Figure 24. Measured RMS Noise of AD8305 vs. AD8305

Cascaded with ADL5317

CHARACTERIZATION METHODS

During characterization, the ADL5317 was treated as a high
voltage 5:1 precision current mirror. To make accurate
measurements throughout the entire current range, calibrated
Keithley 236 current sources were used to create and measure
the test currents. Measurements at low current and high voltage
are very susceptible to leakage to the ground plane.

To minimize leakage on the characterization board, the guard
pins are connected to traces that buffer VAPD and IPDM from
ground. The triax guard connector is also connected to the
GARD pin of the device to provide buffering along the cabling.

Figure 25 shows the primary characterization setup. The data
gathered is used directly, or with calculation, for all the static
measurements, including mirror error between IAPD and
IPDM

, supply tracking offset, incremental gain, and VAPD vs.
IAPD. Component selection is very similar to that of the
evaluation board, except that triax connectors are used in place
of the SMA connectors. To measure the pulse response, output
noise, and bandwidth measurements, more specialized test
setups are used.

ADL5317

CHARACTERIZATION BOARD

FALT VPHV VPLV VSET VCLH

DC SUPPLIES/DMM

VAPD

IPDM

Figure 25. Primary Characterization Setup

KEITHLEY 236

KEITHLEY 236

TRIAX CONNECTORS:
SIGNAL - VAPD AND IPDM PINS
GUARD - GUARD PIN
SHIELD - GROUND

05456-026

Rev. 0 | Page 12 of 16

ADL5317

ADL5317

VSET

AGILENT

33250A

to V

SET

APD

05456-037

ALKALINE

DP 8200

DC POWER SUPPLY

ALKALINE

D CELLS

Figure 26. Configuration for Noise Spectral Density and

D CELLS

+
–

+
–

+
–

+
–

ALKALINE

D CELL

+
–
+
–
+
–

VPHV

ADL5317

VAPD

33μF

GE 273

R1

20kΩ

Wideband Current Noise

+
–

VPLV VSET

R

604Ω

1kΩ

IPDM

FET BUFFER

L

+9V

+
–

+9V

83nF

–
+

HP89410A

VECTOR SIGNAL

ANALYZER

+12V

LNA

–12V

05456-041

TDS5104

Q1

R

C

EVALUATION BOARD

VAPD

FALT VPHV VPLV IPDM VCLH

DC SUPPLIES/DMM

Figure 28. Configuration for Pulse Response from V

1pF

ADL5317

EVALUATION BOARD

Q1

R

AGILENT

33250A

VAPD

FALT VPHV VPLV VSET VCLH

C

DC SUPPLIES/DMM

IPDM

Figure 27. Configuration for Pulse Response from I

R

C

AD8067

APD

to I

TDS5104

PDM

The setup in Figure 26 is used to measure the output current
noise of the ADL5317. Batteries are used in numerous places to
minimize introduced noise and remove the uncertainty
resulting from the use of multiple dc supplies. In application,
properly bypassed dc supplies provide similar results. The load
resistor is chosen for each current to maximize signal-to-noise
ratio while maintaining measurement system bandwidth (when
combined with the low capacitance JFET buffer). The custom
LNA is used to overcome noise floor limitations in the
HP89410A signal analyzer.

Figure 27 shows the configuration used to measure the I

APD

pulse response. To create the test current pulse, Q1 is used in a
common base configuration with the Agilent 33250A, generating a
negative biased square wave with an amplitude that results in a
one decade current step on IPDM.

is chosen according to what current range is desired. Only

R

C

one cable is used between the Agilent 33250A and R

while

C,

everything else is connected with SMA connectors. A FET
scope probe connects the output of the

AD8067 to the

TDS5104 input.

05456-027

NETWORK ANALYZER

OUTPUT R BA

POWER

SPLITTER

++

AD8138

EVAL BOARD

––

VAPD

VSET

R

F

50Ω

60V 5V

VPHV VPLV

ADL5317

EVAL BOARD

1V

COMM

IPDM

R

F

AD8045

Figure 29. Configuration for Small Signal AC Response

The configuration in
V

is pulsed. Q1 and RC are used to generate the operating

SET

Figure 28 is used to measure V

APD

while

current on the VAPD pin. An Agilent 33250A pulse generator is
used on the VSET pin to create a 1.6 V to 2.4 V square wave.
The capacitance on the GARD pin is 2 nF for this test.

The setup in
response from I

Figure 29 is used to measure the frequency

to I

APD

. The AD8138 differential op amp

PDM

delivers a −1.250 V dc offset to bias the NPN transistor and to
have a 500 mV drop across R
depth of 5% of full scale over frequency. The voltage across R
sets the dc operating point of I
in decade changes in I
is fed into an

AD8045 op amp configured to operate as a

transimpedance amplifier. The Feedback Resistor, R
same value as that on the output of the

. This voltage is modulated to a

F

. RF values are chosen to result

APD

. The output current at the IPDM pin

APD

, is the

F

AD8138. Note that any

F

noise at the VSET input is amplified by the ADL5317 with a
gain of 30. This noise shows up on VAPD and causes errors
when measuring nanoamp current levels. This noise can be
filtered by use of the GARD pin. See the

GARD Interface

section for more details.

05456-040

Rev. 0 | Page 13 of 16

ADL5317

EVALUATION BOARD

Table 4. Evaluation Board Configuration Options

Component Function Default Condition

VPHV, VPLV,
GND

High and Low Voltage Supply and Ground Pins. Not Applicable

VSET

R11, C8

VAPD, L1, C9

IPDM, R1

APD Bias Voltage Setting Pin. The dc voltage applied to VSET determines the APD bias
voltage at VAPD. V

= 30 × V

APD

SET

.

APD Input Compensation. Provides essential high frequency compensation at the VAPD
input pin.

Input Interface. The evaluation board is configured to accept an input current at the SMA
connector labeled VAPD. Filtering of this current can be done using L1 and C9.

Mirror Interface. The output current at the SMA connector labeled IPDM is 1/5 the value at

Not Applicable

C8 = 1 nF (size 0603)
R11 = 1 kΩ (size 0603)

L1 = 0 Ω (size 0805)
C9 = open (size 0805)

R1 = open (size 1206)

VAPD. R1 allows a resistor to be installed for applications where a scaled voltage referenced

instead of a current is desirable.

to I

APD

R7, R8, R9,
R10, C6, C7,
C10

VPLV, W1,
W2, R3

VCLH, W1,
C4, R6

Guard Options. By populating R9 and/or R10, the shell of the VAPD SMA connector is set to
the GARD potential. R7 and R8 are installed so that the guard potential can be driven by an
external source, such as the VSUM potential of the Analog Devices optical log amps. C7
filters noise from the VSET interface and provides a high frequency ac path to ground.
Additional filtering is possible by installing a capacitor at C10. C10 should equal C7.

Optional Supply Tracking Mode. Connecting Jumper W2 and opening Jumper W1 places
the ADL5317 into supply tracking mode. In this mode, the voltage at VAPD is typically 2 V
below V

. R3 = 100 kΩ for V

PHV

> 5.5 V.

PLV

Extended Linear Operating Range. Closing W1 connects Pin VPHV and Pin VCLH. This allows
for an extended linear control range of V

APD

using V

SET

.

R7 = R8 = 0 Ω (size 0402)
R9 = R10 = open (size 0402)
C7 = 0.01 µF (size 0805)
C6 = C10 = open (size 0402)

R3 = 0 Ω (size 0402)
W1 = open
W2 = closed

W1 = closed
C4 = open (size 0805)
R6 = 0 Ω (size 0402)

FALT, R2 FALT Interface. R2 is a resistive pull-up that is used to create the logic signal at FALT. R2 = 10 kΩ (size 0603)

C1, C2, C3,
C5, R4, R5

Supply Filtering/Decoupling. C1 = C2 = 0.01 µF (size 0402)

C3 = 0.1 µF (size 0603)
C5 = 0.1 µF (size 1206)
R4 = R5 = 0 Ω (size 0402)

Rev. 0 | Page 14 of 16

ADL5317

V

14

15

16

R8

FALT

VSET

PLV

10kΩ

C3

0.1μF

GND

1

FALT

2

C1

C5

0.1μF

3

4

VPHV

R5
0Ω

VSET

VPLV

VPHV

R3

0Ω

R2

W2

R4
0Ω

C2

0.01μF

0.01μF

COMM

COMM

ADL5317

VPHV6VCLH7GARD8VAPD

5

R6

W1

0Ω

C4

OPEN

C10

OPEN

R10

OPEN

COMM13COMM

L1

0Ω

VAPD

IPDM

GARD

R11
1kΩ

C9

OPEN

NC

NC

C8

1nF

Figure 30. ADL5317 Evaluation Board Schematic

0Ω

12

11

10

9

C6
OPEN

C7

0.01μF

R9
OPEN

R1

OPEN

IPDM
OUTPUT

R7
0Ω

05456-030

05456-032

Figure 31. ADL5317 Evaluation Board Layout

05456-031

Figure 32. ADL5317 Evaluation Board Silkscreen

Rev. 0 | Page 15 of 16

ADL5317 Preliminary Technical Data

R

R

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18
*

COMPLIANT

EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

12

9

13

(BOTTOM VIEW)

8

Figure 33. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm x 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADL5317ACPZ-REEL71–40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 R00
ADL5317ACPZ-WP
ADL5317-EVAL Evaluation Board R00

1

Z = Pb-free part.

1

–40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3 R00

EXPOSED

PAD

0.30

16

1

4

5

N

P

I

D

N

I

*

1.65

1.50 SQ

1.35

0.25 MIN

1

O

C

I

A

T

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05456-0-7/05(0)

Rev. 0 | Page 16 of 16