Datasheet ADL5310 Datasheet (Analog Devices)

120 dB Range (3 nA to 3 mA)

FEATURES

2 independent channels optimized for photodiode

interfacing

6-decade input dynamic range

Law conformance 0.3 dB from 3 nA to 3 mA
Temperature-stable logarithmic outputs
Nominal slope 10 mV/dB (200 mV/dec), externally scalable
Intercepts may be independently set by external resistors
User-configurable output buffer amplifiers
Single- or dual-supply operation
Space-efficient, 24-lead 4 mm × 4 mm LFCSP
Low power: < 10 mA quiescent current

APPLICATIONS

Gain and absorbance measurements
Multichannel power monitoring
General-purpose baseband log compression

PRODUCT DESCRIPTION

The ADL53101 low cost, dual logarithmic amplifier converts
input current over a wide dynamic range to a linear-in-dB
output voltage. It is optimized to determine the optical power
in wide-ranging optical communication system applications,
including control circuitry for lasers, optical switches, atten­uators, and amplifiers, as well as system monitoring. The device
is equivalent to a dual AD8305 with enhanced dynamic range
(120 dB). While the ADL5310 contains two independent signal
channels with individually configurable transfer function
constants (slope and intercept), internal bias circuitry is shared
between channels for improved power consumption and
channel matching. Dual converters in a single, compact LFCSP
package yield space-efficient solutions for measuring gain or
attenuation across optical elements. Only a single supply is
required; optional dual-supply operation offers added flexibility.

Dual Logarithmic Converter

ADL5310

FUNCTIONAL BLOCK DIAGRAM

665kΩ

VSUM

IRF1

V

BIAS

INP1

I

PD1

COMM

IRF2

V

BIAS

INP2

I

PD2

VSUM

665kΩ

The logarithmic slope is set to 10 mV/dB (200 mV/decade)
nominal and can be modified using external resistors and the
independent buffer amplifiers. The logarithmic intercepts for
each channel are defined by the individual reference currents,
which are set to 3 μA nominal for maximum input range by
connecting 665 kΩ resistors between the 2.5 V VREF pins and
the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets
the x-intercept four decades below the reference current—
typically 300 pA for a 3 µA reference.

VREF VRDZ

VNEG

2.5V0.5V

80kΩ20kΩ

VNEG

VREF

Figure 1.

COMM

TEMPERATURE

COMPENSATION

REFERENCE
GENERATOR

TEMPERATURE

COMPENSATION

6.69kΩ

I

LOG

14.2kΩ

14.2kΩ

I

LOG

6.69kΩ

COMM

451Ω

451Ω

OUT1

V

SCL1
BIN1

LOG1

OUT2

V

SCL2
BIN2

LOG2

OUT1

4.99kΩ

OUT2

4.99kΩ

04415-0-001

The ADL5310 employs an optimized translinear structure that
use the accurate logarithmic relationship between a bipolar
transistor’s base emitter voltage and collector current, with
appropriate scaling by precision currents to compensate for the
inherent temperature dependence. Input and reference current
pins sink current ranging from 3 nA to 3 mA (limited to ±60 dB
between input and reference) into a fixed voltage defined by the
VSUM potential. The VSUM potential is internally set to
500 mV but may be externally grounded for dual-supply opera­tion, and for additional applications requiring voltage inputs.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The use of individually optimized reference currents may
be valuable when using the ADL5310 for gain or absorbance
measurements where each channel input has a different current­range requirement. The reference current inputs
are also fully functional dynamic inputs, allowing log ratio
operation with the reference input current as the denominator.
The ADL5310 is specified for operation from –40°C to +85°C.

1

US Patents: 4,604,532, 5,519,308. Other patents pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADL5310

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

General Structure............................................................................ 11

Theory.......................................................................................... 11

Managing Intercept and Slope ..................................................12

Response Time and Noise Considerations.............................. 12

REVISION HISTORY

9/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Ordering Guide.......................................................... 20

11/03—Revision 0: Initial Version

Applications..................................................................................... 13

Calibration................................................................................... 14

Minimizing Crosstalk ................................................................ 14

Relative and Absolute Power Measurements.......................... 15

Characterization Methods......................................................... 16

Evaluation Board ............................................................................ 17

Outline Dimensions....................................................................... 20

Ordering Guide........................................................................... 20

Rev. A | Page 2 of 20

ADL5310

SPECIFICATIONS

VP = 5 V, VN = 0 V, TA = 25°C, R

Table 1.

Parameter Conditions Min Typ Max Unit

INPUT INTERFACE Pins 1 to 6: INP1 and INP2, IRF1 and IRF2, VSUM

Specified Current Range, I
Input Current Min/Max Limits Flows toward INP1 pin or INP2 pin 10 m A
Reference Current, I

, Range Flows toward IRF1 pin or IRF2 pin 3 n 3 m A

REF

Summing Node Voltage Internally preset; user alterable 0.46 0.5 0.54 V

Temperature Drift –40°C < TA < +85°C 0.030 mV/°C

Input Offset Voltage

LOGARITHMIC OUTPUTS Pin 15 and Pin 16: LOG1 and LOG2

Logarithmic Slope 190 200 210 mV/dec
–40°C < TA < +85°C 185 215 mV/dec
Logarithmic Intercept

1

–40°C < TA < +85°C 40 1940 pA

Law Conformance Error 10 nA < IPD < 1 mA 0.1 0.4 dB

3 nA < IPD < 3 mA 0.3 0.6 dB

Wideband Noise

2

Small Signal Bandwidth2 I
Maximum Output Voltage 1.7 V
Minimum Output Voltage Limited by VN = 0 V 0.10 V
Output Resistance 4.375 5 5.625 kΩ

REFERENCE OUTPUT Pin 7 and Pin 24 (internally shorted): VREF

Voltage wrt Ground 2.45 2.5 2.55 V

–40°C < TA < +85°C 2.42 2.58 V

Maximum Output Current Sourcing (grounded load) 20 mA
Incremental Output Resistance Load current < 10 mA 4 Ω

OUTPUT BUFFERS Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1,

Input Offset Voltage −20 +20 mV
Input Bias Current Flowing out of Pins 13, 14, 17, and 18 0.4 µA
Incremental Input Resistance 35 MΩ
Incremental Output Resistance Load current < 10 mA; gain = 1 0.5 Ω
Output High Voltage RL = 1 kΩ to ground

Output Low Voltage RL = 1 kΩ to ground 0.10 V
Peak Source/Sink Current 30 mA
Small-Signal Bandwidth Gain = 1 15 MHz
Slew Rate 0.2 V to 4.8 V output swing 15 V/µs

POWER SUPPLY Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG

Positive Supply Voltage (VP – VN ) ≤ 12 V 3 5 12 V

Quiescent Current Input currents < 10 µA 9.5 11.5 mA

Negative Supply Voltage (Optional) (VP – VN ) ≤ 12 V

1

Other values of logarithmic intercept can be achieved by adjustment of R

2

Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.

= 665 kΩ, and VRDZ connected to VREF, unless otherwise noted.

REF

PD

Flows toward INP1 pin or INP2 pin 3 n 3 m A

V

− V

, V

SUM

IREF

− V

SUM

IN

165 300 535 pA

IPD > 3 µA; output referred 0.5 µV/√Hz

= 3 µA 1.5 MHz

PD

and OUT1

.

REF

−20

+20 mV

V

−

P

V

0.1

−5.5

0 V

Rev. A | Page 3 of 20

ADL5310

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VP − V
Input Current 20 mA
Internal Power Dissipation 500 mW
θ

JA

Maximum Junction Temperature 125°C
Operating Temperature Range –40°C to +85°C
Storage Temperature Range

Lead Temperature Range (Soldering 60 sec) 300°C

N

12 V

1

35°C/W

−65°C to +150°C

1

With paddle soldered down.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 4 of 20

ADL5310

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VREF

VRDZ

COMMCOMMVNEG

23 22 21 20 19

24

OUT1

OUT2

18

SCL1

17

BIN1

16

LOG1

15

LOG2

14

BIN2

13

SCL2

04415-0-002

VSUM

INP1
IRF1
IRF2
INP2

VSUM

1

PIN 1
INDICATOR

2

3

4

5

6

7 8 9 10 11 12

VREF

ADL5310

DUAL LOG AMP

TOP VIEW

(Not to Scale)

VPOS

VPOS

VNEG

VNEG

Figure 2. 24-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1, 6 VSUM Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input

summing node potentials. Pin 1 and Pin 6 are internally shorted.

2 INP1 Channel 1 Numerator Input. Accepts (sinks) photodiode current I

. Usually connected to photodiode anode

PD1

such that photocurrent flows into INP1.
3 IRF1 Channel 1 Denominator Input. Accepts (sinks) reference current, I
4 IRF2 Channel 2 Denominator Input. Accepts (sinks) reference current, I
5 INP2 Channel 2 Numerator Input. Accepts (sinks) photodiode current I

.

RF1

.

RF2

. Usually connected to photodiode anode

PD2

such that photocurrent flows into INP2.
7, 24 VREF Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.
8, 9 VPOS Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally.
10, 11, 20 VNEG Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and

Applications sections. All VNEG pins must be connected externally.
12 OUT2 Buffer Output for Channel 2.
13 SCL2 Buffer Amplifier Inverting Input for Channel 2.
14 BIN2 Buffer Amplifier Noninverting Input for Channel 2.
15 LOG2 Output of the Logarithmic Front End for Channel 2.
16 LOG1 Output of the Logarithmic Front End for Channel 1.
17 BIN1 Buffer Amplifier Noninverting Input for Channel 1.
18 SCL1 Buffer Amplifier Inverting Input for Channel 1.
19 OUT1 Buffer Output for Channel 1.
21, 22 COMM Analog Ground. Pin 21 and Pin 22 are internally shorted.
23 VRDZ Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the

intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be

provided.

Rev. A | Page 5 of 20

ADL5310

TYPICAL PERFORMANCE CHARACTERISTICS

VP = 5 V, VN = 0 V, R

1.6

1.4

= 665 kΩ, TA = 25°C, unless otherwise noted.

REF

TA = –40°C, 0°C, +25°C, +70°C,

= 0V

V

IN

+85°C

2.0

1.5

1.2

1.0

(V)

0.8

LOG

V

0.6

0.4

0.2

0

1n 10n 100n 1µ 10µ 100µ 1m 10m

I

(A)

INP

vs. I

Figure 3. V

for Multiple Temperatures

LOG

INP

1.8

1.6

1.4

1.2

(V)

1.0

LOG

V

0.8

0.6

0.4

0.2

0

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 4. V

LOG

TA = –40°C, 0°C, +25°C, +70°C,

V

= 0V

IN

I

(A)

REF

vs. I

for Multiple Temperatures (I

REF

INP

1.8

1.6

1.4

1.2

(V)

1.0

LOG

V

0.8

0.6

0.4

0.2

0

1n 10n 100n 1µ 10µ 100µ 1m 10m

30nA

3nA

Figure 5. V

3µA

300nA

I

INP

vs. I

for Multiple Values of I

LOG

INP

300µA

30µA

(A)

Decade Steps from 3 nA to 3 mA

+85°C

= 3 µA)

3mA

,

REF

04415-0-003

04415-0-004

04415-0-005

1.0

0.5

0

–0.5

ERROR (dB (10mV/dB))

–1.0

–1.5

–2.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

+25°C

I

INP

Figure 6. Law Conformance Error vs. I

+70°C

0°C

(A)

–40°C

for Multiple Temperatures,

INP

Normalized to 25°C

2.0

1.5

1.0

0.5

0

–0.5

ERROR (dB (10mV/dB))

–1.0

–1.5

–2.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 7. Law Conformance Error vs. I

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (dB (10mV/dB))

–0.6

–0.8

–1.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 8. Law Conformance Error vs. I

+70°C

3µA

300nA

+85°C

Normalized to 25°C (I

300µA

30µA

I

REF

3mA

I

INP

–40°C

(A)

for Multiple Temperatures,

REF

= 3 µA)

INP

30nA3nA

(A)

for Multiple Values of I

INP

Decade Steps from 3 nA to 3 mA

+85°C

+25°C

0°C

04415-0-006

04415-0-007

04415-0-008

,

REF

Rev. A | Page 6 of 20

ADL5310

1.8

1.6

1.4

1.2

(V)

1.0

LOG

V

0.8
3nA

0.6

0.4

0.2

30nA

300nA

3µA

0

1n 10n 100n 1µ 10µ 100µ 1m 10m

I

REF

vs. I

Figure 9. V

for Multiple Values of I

LOG

REF

30µA

300µA

(A)

Decade Steps from 3 nA to 3 mA

3mA

INP

04415-0-009

,

1.0

I

REF

3nA

30nA

(A)

for Multiple Values of I

REF

300nA

0.8

0.6

0.4

0.2
3µA

0

–0.2

–0.4

ERROR (dB (10mV/dB))

–0.6

30µA

–0.8

–1.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

3mA

300µA

Figure 12. Law Conformance Error vs. I

Decade Steps from 3 nA to 3 mA

3mA

3µA

04415-0-012

,

INP

1.0

0.8
+5V, 0V

0.6

0.4

0.2

+3V, 0V

0

–0.2

+5V, –5V

–0.4

ERROR (dB (10mV/dB))

–0.6

–0.8

–1.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

Figure 10. Law Conformance Error vs. I

+9V, 0V

+12V, 0V

+5V, –5V

(A)

I

INP

for Various Supply Conditions

INP

+12V, 0V

2.0

1.5

1.0

0.5

0

MEAN ± 3σ AT 0°C

TA = 0°C, 70°C

MEAN + 3σ AT 70°C

04415-0-010

2.0

1.5

1.0

0.5

0

–0.5

ERROR (dB (10mV/dB))

–1.0

–1.5

–2.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

MEAN + 3σ

MEAN – 3σ

I

(A)

PD

TA = 25°C

Figure 13. Law Conformance Error Distribution (3σ to Either Side of Mean)

4

3

2

1

0

MEAN + 3σ AT +85°C

MEAN + 3σ AT –40°C

TA = –40°C, 85°C

04415-0-013

–0.5

ERROR (dB (10mV/dB))

–1.0

–1.5

–2.0

1n 10n 100n 1µ 10µ 100µ 1m 10m

I

(A)

PD

MEAN – 3σ AT 70°C

Figure 11. Law Conformance Error Distribution (3σ to Either Side of Mean)

Rev. A | Page 7 of 20

04415-0-011

–1

ERROR (dB (10mV/dB))

–2

–3

–4

1n 10n 100n 1µ 10µ 100µ 1m 10m

MEAN – 3σ AT –40°C

I

(A)

PD

Figure 14. Law Conformance Error Distribution (3σ to Either Side of Mean)

04415-0-014

ADL5310

15
10

5
0

–5
–10
–15
–20
–25
–30
–35

NORMALIZED RESPONSE (dB)

–40
–45
–50

Figure 15. Small Signal AC Response, I
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

15

10

5
0

–5
–10
–15
–20
–25
–30
–35

NORMALIZED RESPONSE (dB)

–40
–45
–50

Figure 16. Small Signal AC Response, I
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

100

3nA

30nA

3nA

10k 100k100 1k 1M 10M 100M

FREQUENCY (Hz)

300nA

3mA

3µA

to V

INP

OUT

30nA

300nA

3µA

30µA

10k 100k100 1k 1M 10M 100M

FREQUENCY (Hz)

3mA

to V

REF

OUT

30µA

300µA

(AV = 1)

300µA

(AV = 1)

04415-0-015

04415-0-016

1.6

1.4
T-RISE < 1µs T-FALL < 1µs 300µA TO 3mA

T-RISE < 1µs T-FALL < 1µs30µA TO 300µA

T-RISE < 1µs T-FALL < 5µs3µA TO 30µA

T-RISE < 5µs T-FALL < 10µs 300nA TO 3µA

T-RISE < 10µs T-FALL < 40µs 30nA TO 300nA

T-RISE < 30µs T-FALL < 80µs 3nA TO 30nA

0

0 20 40 60 80 100 120 140 160 180 200

TIME (µs)

to V

Figure 18. Pulse Response—I

(AV = 1)

INP

OUT

(V)

V

OUT

1.2

1.0

0.8

0.6

0.4

0.2

in Consecutive 1-Decade Steps

1.6

1.4
T-RISE < 80µs T-FALL < 30µs 3nA TO 30nA

T-RISE < 40µs T-FALL < 10µs 30nA TO 300nA

T-RISE < 10µs T-FALL < 5µs 300nA TO 3µA

T-RISE < 1µs T-FALL < 1µs3µA TO 30µA

T-RISE < 1µs T-FALL < 1µs30µA TO 300µA

T-RISE < 1µs T-FALL < 1µs 300µA TO 3mA

0

0 20 40 60 80 100 120 140 160 180 200

TIME (µs)

to V

Figure 19. Pulse Response—I

(AV = 1)

REF

OUT

(V)

V

OUT

1.2

1.0

0.8

0.6

0.4

0.2

in Consecutive 1-Decade Steps

5.0

04415-0-018

04415-0-019

3nA

10

1

V rms/ Hz

µ

0.1

300µA

0.01
100 1k 10k 100k 1M 10M

Figure 17. Spot Noise Spectral Density at V

for I

30nA

300nA

30µA

3mA

FREQUENCY (Hz)

in Decade Steps from 3 nA to 3 mA

INP

3µA

vs. Frequency (AV = 1)

OUT

04415-0-017

Rev. A | Page 8 of 20

4.0

3.0

mV rms

2.0

1.0

0

10n 100n 1µ 10µ 100µ 1m 10m1n

(A)

I

INP

Figure 20. Total Wideband Noise Voltage at V

OUT

vs. I

(AV = 1)

INP

04415-0-020

ADL5310

25

20

15

10

5

0

DRIFT (mV)

–5

REF

V

–10

–15

–20

–25

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

Figure 21. V

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Drift vs. Temperature (3σ to Either Side of Mean)

REF

Normalized to 25°C

6
5
4
3
2
1
0

–1

DRIFT (mV/dec)

Y

–2

V

–3
–4
–5
–6

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Figure 22. Slope Drift vs. Temperature (3σ to Either Side of Mean)

Normalized to 25°C

200

04415-0-021

04415-0-022

5
4
3
2
1
0

–1

DRIFT (mV)

INPT

–2

V

–3
–4
–5
–6

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

Figure 24. V

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Drift vs. Temperature (3σ to Either Side of Mean)

INPT

Normalized to 25°C

7
6
5
4
3
2
1
0

DRIFT (mV/dec)

–1

Y

∆V

–2
–3
–4
–5
–6

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Figure 25. Slope Mismatch Drift vs. Temperature
– VY2, 3σ to Either Side of Mean) Normalized to 25°C

(V

Y1

200

04415-0-024

04415-0-025

150

100

50

0

DRIFT (pA)

Z

I

–50

–100

–150

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Figure 23. Intercept Drift vs. Temperature

(3σ to Either Side of Mean) Normalized to 25°C

04415-0-023

Rev. A | Page 9 of 20

150

100

50

0

DRIFT (pA)

–50

Z

∆I

–100

–150

–200

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

Figure 26. Intercept Mismatch Drift vs. Temperature

– IZ2, 3σ to Either Side of Mean) Normalized to 25°C

(I

Z1

04415-0-026

ADL5310

700

600

500

400

COUNT

300

200

100

0

600

195190 200 205 210

SLOPE (mV/dec)

Figure 27. Distribution of Logarithmic Slope

04415-0-027

450

400

350

300

250

200

COUNT

150

100

50

0

–3 0–9 –6 3 6 9

SLOPE MISMATCH (mV/dec)

Figure 30. Distribution of Channel-to-Channel Slope Mismatch ( V

500

– VY2)

Y1

04415-0-030

500

400

300

COUNT

200

100

700

600

500

400

COUNT

300

200

100

0

200100 300 400 500

INTERCEPT (pA)

Figure 28. Distribution of Logarithmic Intercept

04415-0-028

400

300

COUNT

200

100

0

–100 0–300 –200 100 200 300

INTERCEPT MISMATCH (pA)

Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (I

500

400

300

COUNT

200

100

Z1

– IZ2)

04415-0-031

0

2.482.46 2.50 2.52 2.54
VREF VOLTAGE (V)

Figure 29. Distribution of V

(RL = 100 kΩ)

REF

04415-0-029

0

–3 0–9 –6 3 6 9

V

– V

INPT

VOLTAGE (mV)

SUM

Figure 32. Distribution of Offset Voltage (V

INPT

– V

SUM

04415-0-032

)

Rev. A | Page 10 of 20

ADL5310

GENERAL STRUCTURE

The ADL5310 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems and is
useful in many nonoptical applications. These notes explain the
structure of this unique style of translinear log amp. Figure 33
shows the key elements of one of the two identical on-board
log amps.

BIAS

GENERATOR

PHOTODIODE

CURRENT

I

PD

INP1

(INP2)

2.5V

INPUT

80kΩ

0.5V

VSUM

0.5V

VNEG (NORMALLY GROUNDED)

Figure 33. Simplified Schematic of Single Log Amp

20kΩ

VREF

V

BE1

COMM

IREF

Q2Q1

0.5V

I

REF

V

BE1

V

BE2

VRDZ

V

BE2

TEMPERATURE

COMPENSATION

(SUBTRACT AND

DIVIDE BY T°K)

44µA/dec

451Ω14.2kΩ

6.69kΩ

COMM

VLOG

04415-0-033

The photodiode current IPD is received at either Pin INP1 or
Pin INP2. The voltages at these nodes are approximately equal
to the voltage on the adjacent guard pins, VSUM, as well as
reference inputs IRF1 and IRF2, due to the low offset voltage
of the JFET operational amplifiers. Transistor Q1 converts I

PD

to a corresponding logarithmic voltage, as shown in Equation 1.
A finite positive value of V

is needed to bias the collector of

SUM

Q1 for the usual case of a single-supply voltage. This is inter­nally set to 0.5 V, one-fifth of the 2.5 V reference voltage that
appears on Pin VREF. Both VREF pins are internally shorted,
as are both VSUM pins. The resistance at the VSUM pin is
nominally 16 kΩ; this voltage is not intended as a general bias
source.

The ADL5310 also supports the use of an optional negative
supply voltage, V

, at Pin VNEG. When VN is 0.5 V or more

N

negative, VSUM may be connected to ground; thus, INP1, INP2,
IRF1, and IRF2 assume this potential. This allows operation as a
voltage-input logarithmic converter by the inclusion of a series
resistor at either or both inputs. Note that the resistor setting I

REF

for each channel needs to be adjusted to maintain the intercept
value. Also note that the collector-emitter voltages of Q1 and Q2
are the full V

and effects due to self-heating cause errors at

N

large input currents.

The input-dependent V

of a second transistor, Q2, operating at I

V

BE2

of Q1 is compared with the reference

BE1

. I

is gener-

REF

REF

ated externally to a recommended value of 3 µA. However, other
values over a several-decade range can be used with a slight
degradation in law conformance.

THEORY

The base-emitter voltage of a bipolar junction transistor (BJT)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:

V

= kT/q ln(IC/IS) (1)

BE

where:

I

is the collector current.

C

is a scaling current, typically only 10

I

S

kT/q is the thermal voltage, proportional to absolute

temperature (PTAT), and is 25.85 mV at 300 K.

is never precisely defined and exhibits an even stronger tem-

I

S

perature dependence, varying by a factor of roughly a billion
between −35°C and +85°C. Thus, to make use of the BJT as an
accurate logarithmic element, both of these temperature
dependencies must be eliminated.

The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current I
other operating at a reference current I

V

– V

BE1

= ln(10) kT/q log
= 59.5 mV log

= kT/q ln(IPD/IS) – kT/q ln(I

BE2

10(IPD/IREF

10(IPD/IREF

) (T = 300 K)

The uncertain, temperature-dependent saturation current, I
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperature­corrected current:

I

where I

= IY log10(IPD/I

LOG

is an accurate, temperature-stable scaling current that

Y

) (3)

REF

determines the slope of the function (change in current per
decade). For the ADL5310, I

is 44 µA, resulting in a

Y

temperature-independent slope of 44 µA/decade for all values

and I

of I

PD

voltage-mode output, V

. This current is subsequently converted back to a

REF

, scaled 200 mV/decade.

LOG

It is apparent that this output should be 0 for I
would need to swing negative for smaller values of input
current. To avoid this, I
smallest value of I

to shift it upward by 0.8 V when VRDZ is directly

V

LOG

would need to be as small as the

REF

. Accordingly, an offset voltage is added to

PD

connected to VREF. This moves the intercept to the left by four
decades (at 200 mV/decade), from 3 μA to 300 pA:

= IY log10(IPD/I

I

LOG

where I

is the operational value of the intercept current.

INTC

Because values of I

) (4)

INTC

< I

PD

result in a negative V

INTC

supply of sufficient value is required to accommodate this
situation.

–17

A.

and the

PD

, can be written as

REF

)

REF/IS

) (2)

,

S

= I

PD

and

REF

, a negative

LOG

Rev. A | Page 11 of 20

ADL5310

The voltage V
resistance of 4.55 kΩ, formed by the parallel combination of a

6.69 kΩ resistor to ground and a 14.2 kΩ resistor to Pin VRDZ
(typically tied to the 2.5 V reference, VREF). At the LOG1
(LOG2) pin, the output current I

V

LOG

= 44 µA × 4.55 kΩ × log
= V

Y

where V

Y

tive loading on LOG1 (LOG2) lowers this slope and results in
an overall scaling uncertainty. This is due to the variability of
the on-chip resistors compared to the off-chip load. As a con­sequence, this practice is not recommended.

may also swing below ground when dual supplies (VP and

V

LOG

) are used. When VN = −0.5 V or larger, the input Pins INP1

V

N

(INP2) and IRF1 (INP2) may be positioned at ground level
simply by grounding VSUM. Care must be taken to limit the
power consumed by the input BJT devices when using a larger
negative supply, because self-heating degrades the accuracy at
higher currents.

is generated by applying I

LOG

= I

× 4.55 kΩ

LOG

log10(IPD/I

INTC

)

generates a voltage of

LOG

10(IPD/IINTC

to an internal

LOG

) (5)

= 200 mV/decade or 10 mV/dB. Note that any resis-

Thus, the effective intercept current I
thousandth of I
recommended value of I

, corresponding to 300 pA when using the

REF

= 3 µA.

REF

is only one ten-

INTC

The slope can be reduced by attaching a resistor between the log
amp output pin, LOG1 or LOG2, and ground. This is strongly
discouraged given that the on-chip resistors do not ratio
correctly to the added resistance. Also, it is rare that one would
wish to lower the basic slope of 10 mV/dB; if this is needed, it
should be effected at the low impedance output of the buffer
amps, which are provided to avoid such miscalibration and to
allow higher slopes to be used.

Each of the ADL5310’s buffers is essentially an uncommitted
operational amplifier with rail-to-rail output swing, good load­driving capabilities, and a typical unity-gain bandwidth of
15 MHz. In addition to allowing the introduction of gain, using
standard feedback networks and thereby increasing the slope
voltage V

, the buffer can be used to implement multipole, low-

Y

pass filters, threshold detectors, and a variety of other functions.
Further details on these applications can be found in the
AD8304 data sheet.

MANAGING INTERCEPT AND SLOPE

When using a single supply, VRDZ should be directly connected
to VREF to allow operation over the entire 6-decade input
current range. As noted in the Theory section, this introduces
an accurate offset voltage of 0.8 V at the LOG1 and LOG2 pins,
equivalent to four decades, resulting in a logarithmic transfer
function that can be written as

V

= V

where I

= VY log10(104 × IPD/I

LOG

log10(IPD/I

Y

INTC

= I

REF

INTC

/104.

) (6)

REF

)

RESPONSE TIME AND NOISE CONSIDERATIONS

The response time and output noise of the ADL5310 are funda­mentally a function of the signal current, I
the bandwidth is proportional to I

, as shown in Figure 15. The

PD

output low frequency voltage-noise spectral-density is a
function of I
values of I

(see Figure 17) and also increases for small

PD

. Details of the noise and bandwidth performance

REF

of translinear log amps can be found in the AD8304 data sheet.

. For smal l cur rents,

PD

Rev. A | Page 12 of 20

ADL5310

APPLICATIONS

665kΩ

VREF VRDZ VPOS

VNEG

2.5V0.5V

80kΩ

VNEG

VREF VNEG COMM

665kΩ

V

V

4.7nF

BIAS

I

4.7nF

BIAS

I

2kΩ

PD1

1kΩ

1nF

2kΩ

PD2

1kΩ

1nF

1nF

VSUM

I

RF1

IRF1

INP1

20kΩ

COMM
IRF2

I

RF2

INP2
VSUM

Figure 34. Basic Connections for Fixed Intercept Use

The ADL5310 is easy to use in optical supervisory systems
and in similar situations where a wide-ranging current is to
be converted to its logarithmic equivalent—that is, represented
in decibel terms. Basic connections for measuring a single
current at each input are shown in Figure 34, which also
includes various nonessential components, as explained next.

The 2 V difference in voltage between the VREF and Input Pins
INP1 and INP2, in conjunction with the external 665 kΩ resis­tors R

RF1

and R

, provides 3 µA reference currents I

RF2

RF1

and I

RF2

into Pins IRF1 and IRF2. Connecting VRDZ to VREF raises the
voltage at LOG1 and LOG2 by 0.8 V, effectively lowering each
intercept current I
A wide range of other values for I

by a factor of 104 to position it at 300 pA.

INTC

, from 3 nA to 3 mA, may be

REF

used. The effect of such changes is shown in Figure 5 and
Figure 8.

(R

Any temperature variation in R

) must be taken into

RF1

RF2

account when estimating the stability of the intercept. Also, the

(I

overall noise increases when using very low values of I

RF1

RF2

).
In fixed-intercept applications there is little benefit in using a
large reference current, because doing so only compresses the
low-current-end of the dynamic range when operated from a
single supply. The capacitor between VSUM and ground is

TEMPERATURE

COMPENSATION

TEMPERATURE

COMPENSATION

5V

COMM

REFERENCE

GENERATOR

COMM

I

0.5log

FLT1

0.5log

FLT2

04415-0-034

( )

10

( )

10

PD1

1nA

I

PD2

1nA

6.69kΩ

I

LOG

14.2kΩ

14.2kΩ

I

LOG

6.69kΩ

451Ω

451Ω

OUT1

SCL1

BIN1

LOG1

OUT2

SCL2

BIN2

LOG2

V

12kΩ

V

12kΩ

OUT1

OUT2

8kΩ

C
10 nF

8kΩ

C
10 nF

strongly recommended to minimize the noise on this node, to
reduce channel-to-channel crosstalk, and to help provide clean
reference currents.

In addition, each input and reference pin (INP1, INP2, IRF1,
and IRF2) has a compensation network made up of a series
resistor and capacitor. The junction capacitance of the photo­diode along with the network capacitance of the board artwork
around the input system creates a pole that varies widely with
input current. The RC network stabilizes the system by simul­taneously reducing this pole frequency and inserting a zero to
compensate an additional pole inherent in the input system. In
general, the 1 nF, 1 kΩ network handles almost any photodiode
interface. In situations where larger active area photodiodes are
used, or when long input traces are used, the capacitor value
may need to be increased to ensure stability. Although the signal
and reference input systems are similar, additional care is
required to ensure stable operation of the reference inputs at

(I

temperature extremes across the full current range of I

RF1

RF2

).
It is recommended that filter components of 4.7 nF and 2 kΩ
should be used from Pin IRF1 (IRF2) to ground. Temperature­stable components should always be used in critical locations
such as the compensation networks; Y5V-type chip capacitors
are to be avoided due to their poor temperature stability.

Rev. A | Page 13 of 20

ADL5310

The optional capacitor from LOG1 (LOG2) to ground forms a
single-pole, low-pass filter in combination with the 5 kΩ resis­tance at this pin. For example, when using a C
3 dB corner frequency is 3.2 kHz. Such filtering is useful in
minimizing the output noise, particularly when I
Multipole filters are more effective in reducing the total noise;
examples are provided in the AD8304 data sheet.

Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade,
and thus a 4 V swing at the buffer output would correspond to
20 decades, it is often useful to raise the slope to make better use
of the rail-to-rail voltage range. For illustrative purposes, both
channels in Figure 34 provide a 0.5 V/decade overall slope
(25 mV/dB). Thus, using I

= 3 nA to 1.4 V at IPD = 3 mA; the buffer output runs from

I

PD

= 3 μA, V

REF

LOG

0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB
(electrical, that is, 60 dB optical power).

Further information on adjusting the slope and intercept, using
a negative supply, and additional operations can be found in the
AD8305 data sheet.

CALIBRATION

Each channel of the ADL5310 has a nominal slope and intercept
at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively,
when configured as shown in Figure 34. These values are
untrimmed and the slope alone may vary by as much as 7.5%
over temperature. For this reason, it is recommended that a
simple calibration be done to achieve increased accuracy. While
the ADL5310 offers improved slope and intercept matching
compared to a randomly selected pair of AD8305 log amps, the
specified accuracy can only be achieved by calibrating each
channel individually.

1.4

1.2

1.0

0.8

(V)

LOG

0.6

V

0.4

0.2

0

Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy

MEASURED OUTPUT

10n 100n 1µ 10µ 100µ 1m 10m1n

UNCALIBRATED ERROR

CALIBRATED ERROR

IDEAL OUTPUT

I

(A)

PD

of 10 nF, the

FLT

is small.

PD

runs from 0.2 V at

4

3

2

1

0

–1

–2

–3

ERROR (dB (10mV/dB))

04415-0-035

Figure 35 shows the improvement in accuracy when using a 2­point calibration method. To perform this calibration,
apply two known currents, I

and I2, in the linear operating

1

range between 10 nA and 1 mA. Measure the resulting output,

and V2, respectively, and calculate the slope m and the

V

1

intercept b:

m = (V

– V2)/[log10(I1) – log10(I2)] (7)

1

– m × log10(I1) (8)

b = V

1

The same calibration could be performed with two known
optical powers, P

and P2. This allows for calibration of the

1

entire measurement system while providing a simplified
relationship between the incident optical power and V

LOG

voltage:

m = (V

– V2)/(P1 – P2) (9)

1

– m × P1 (10)

b = V

1

The uncalibrated error line in Figure 35 was generated assum­ing that the slope of the measured output was 200 mV/decade
when in fact it was actually 194 mV/decade. Correcting for this
discrepancy decreased measurement error up to 3 dB.

MINIMIZING CROSSTALK

Combining two high-dynamic-range logarithmic converters in
one IC carries potential pitfalls concerning channel-to-channel
isolation. Special care must be taken in several areas to ensure
acceptable crosstalk performance, particularly when one or both
channels may operate at very low input currents. Fastidious sup­ply bypassing—also necessary for overall stability—and careful
board layout are important first steps for minimizing crosstalk.

While the shared bias circuitry improves channel-to-channel
matching and reduces power consumption, it is also a source of
crosstalk that must be mitigated. The VSUM pins, which are
internally shorted, should be bypassed with at least 1 nF to
ground, and 20 nF is recommended for operation at the lowest
currents (<30 nA). VSUM is of particular importance because it
acts as a reference voltage input for each input system, but
without the bandwidth limitation at low currents that the
primary inputs incur. Disturbances at the VSUM pin that are
well within the bandwidth of the input are tracked by the loop
and do not generate disturbances at the output (aside from the
generally minor perturbation in reference currents caused by
voltage variations at IRF1 and IRF2).

For this reason, the pole frequency at VSUM, which has a 16 kΩ
typical source resistance, should be set below the minimum
input system bandwidth for the lowest input current to be
encountered. Because the low frequency noise at VSUM is also
tracked by the loop within its available bandwidth, this is also a
criterion for reducing the noise contribution at the output from
the thermal noise of the 16 kΩ source resistance at VSUM.

Rev. A | Page 14 of 20

ADL5310

A 10 nF capacitor on each VSUM pin (20 nF parallel equivalent)
combined with the 16 kΩ source resistance yields a 500 Hz pole,
which is sufficiently below the bandwidth for the minimum
input current of 3 nA.

Residual crosstalk disturbance is particularly problematic at the
lowest currents for two reasons. First, the loop is unable to reject
summing node disturbances beyond the limited bandwidth.
Second, the settling response at the lowest currents to any
residual disturbance is significantly slower than that for input
currents even one or two decades higher (see Figure 18).

12

ACTIVE CHANNEL OUTPUT PULSE, 1-DECADE STEP
3µA TO 30µA

9

6

– 3nA

I

INP

3

0

I

INP

–3

INACTIVE CHANNEL OUTPUT (mV)

INACTIVE CHANNEL RESPONSE

–6

0 0.5 1.0 1.5 2.0 2.5

– 30nA

I

– 10nA

INP

TIME (ms)

I

INP

– 100nA

1.2

1.0

0.8

0.6

0.4

0.2

0

ACTIVE CHANNEL OUTPUT (V)

04415-0-036

Figure 36. Crosstalk Pulse Response for Various Input Current Values

Figure 36 shows the measured response of an inactive channel
(dc input) to a 1-decade current step on the input of the active
channel for several inactive channel dc current values. Addi­tional system considerations may be necessary to ensure
adequate settling time following a known transient when one or
both channels are operating at very low input currents.

RELATIVE AND ABSOLUTE POWER MEASUREMENTS

When properly calibrated, the ADL5310 provides two inde­pendent channels capable of accurate absolute optical power
measurements. Often, it is desirable to measure the relative
gain or absorbance across an optical network element, such as
an optical amplifier or variable attenuator. If each channel has
identical logarithmic slopes and intercepts, this can easily be
done by differencing the output signals of each channel. In
reality, channel mismatch can result in significant errors over a
wide range of input levels if left uncompensated. Postprocessing
of the signal can be used to account for individual channel
characteristics. This requires a simple calculation of the
expected input level for a measured log voltage, followed by
differencing of the two signal levels in the digital domain for a

relative gain or absorbance measurement. A more straight­forward analog implementation includes the use of a current
mirror, as shown in Figure 37. The current mirror is used to
feed an opposite polarity replica of the cathode photocurrent of
PD2 into Channel 2 of the ADL5310. This allows one channel to
be used as an absolute power meter for the optical signal
incident on PD2, while the opposite channel is used to directly
compute the log ratio of the two input signals.

VPOS

10

BIAS

10

5V

COMM

I

IN2

()

100pA

I

LOG2

I

IN1

()

I

PD2

I

LOG1

COMM

OUT2

SCL2

BIN2

LOG2

OUT1

SCL1

BIN1

LOG1

1nF

1nF

*

Φ

2

α

**

21

5V

0.1µF

PD2

InGaAs PIN

5V

PD1

InGaAs PIN

I

IN2=IPD2

1kΩ

4.7nF

2MΩ

1kΩ

4.7nF

I

PD2

1kΩ

4.7nF

I

IN1

1kΩ

4.7nF0.1µF

1nF

1nF

VSUM

INP2

IRF2

VRDZ

VREF

IRF1

INP1

VSUM

ADL5310

*Φ

log

log

**α21(V) ≅ 0.2log

log

log

(V) ≅ 0.2log

2

TEMPERATURE

COMPENSATION

GENERATOR

TEMPERATURE

COMPENSATION

VNEG COMM

Figure 37. Absolute and Relative Power Measurement Application

Using Modified Wilson Current Mirror

The presented current mirror is a modified Wilson mirror.
Other current mirror implementations would also work, though
the modified Wilson mirror provides fairly constant perfor­mance over temperature. It is essential to use matched pair
transistors when designing the current mirror to minimize the
effects of temperature gradients and beta mismatch.

04415-0-037

Rev. A | Page 15 of 20

ADL5310

The solution in Figure 37 is no longer subject to potential
channel mismatch issues. Individual channel slope and intercept
characteristics can be calibrated independently. The accuracy
was verified using a pair of calibrated current sources. The
performance of the circuit depicted in Figure 37 is shown in
Figure 38 and Figure 39. Multiple transfer functions and error
plots are provided for various power levels. The accuracy is
better than 0.1 dB over a 5-decade range. The dynamic range is
slightly reduced for strong I
limited available swing of the VLOG pin and can be recovered
through careful selection of input and output optical tap
coupling ratios.

1.8

1.6

φ2 WHEN I

1.4

1.2

1.0

0.8

0.6

OUTPUT VOLTAGE (V)

0.4

0.2

0

Figure 38. Absorbance and Absolute Power Transfer Functions for

0.5

0.4

0.3

0.2

0.1

0

I

=10µ A

–0.1

PD1

ERROR (dB)

–0.2

–0.3

–0.4

–0.5

–30 –20 –10 0 10 20 30–40

Figure 39. Log Conformance for Wilson Mirror ADL5310 Combination,

Normalized to 10 mA Channel 1 Input Current, I

PD1

–10 0 10 20 30 40 50–20

Wilson Mirror ADL5310 Combination

I

=1µA

PD1

input currents. This is due to the

IN

= 100µA

α21 FOR MULTIPLE VALUES OF I

LOG

[I

PD1/IPD2

= 100µA

[I

PD1/IPD2

] (dB)

40 50 60

] (dB)

I

LOG

10

PD1

10

PD1

60

04415-0-038

04415-0-039

IN1

CHARACTERIZATION METHODS

During the characterization of the ADL5310, the device was
treated as a precision current-input logarithmic converter,
because it is impractical to generate accurate photocurrents by
illuminating a photodiode. The test currents were generated by
using either a well-calibrated current source, such as the
Keithley 236, or a high value resistor from a voltage source to
the input pin. Great care is needed when using very small input
currents. For example, the triax output connection from the
current generator was used with the guard tied to VSUM. The
input trace on the PC board was guarded by connecting
adjacent traces to VSUM.

These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INP1
(INP2) pin, a leakage-path resistance of 1 GΩ to ground would
subtract 0.5 nA from the input, which amounts to a −1.6 dB
error for a 3 nA source current. Additionally, the very high
sensitivity at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reducing the pickup of these spurious
signals.

Additional information, including test setups, can be found in
the AD8305 and ADL5306 data sheets.

Rev. A | Page 16 of 20

ADL5310

EVALUATION BOARD

An evaluation board is available for the ADL5310 (Figure 40 shows the schematic). It can be configured for a wide variety of experiments.
The gain of each buffer amp is factory-set to unity, providing a slope of 200 mV/dec, and the intercept is set to 300 pA. Table 4 describes
the various configuration options.

Table 4. Evaluation Board Configuration Options

Component Function Default Condition

P1 Supply Interface. Provides access to the Supply Pins VNEG, COMM, and

VPOS.

P2, R1, R3, R8, R9,
R17, R22, R25, R30

R5, R6, R7, R16,
R18, R19, R20,
R21, R31, R32, C4,
C14, C15, C16,
C19, C20

R2, R28, R29 Intercept Adjustment. The voltage dropped across Resistors R28 and R29

R4, R10, R11, C2,
C3, C5, C6, C8, C9

C1, C7 Filtering VSUM. C1 = C7 = 0.01 µF (size 0402)
R12, R13, R14,

R15, C10, C11,
C12, C13

IREF, INPT Input Interface. The test board is configured to accept current through the

J1, J2 SC-Style Photodiode. Provides for the direct mounting of SC-style

Monitor Interface. By adding 0 Ω resistors to R1, R3, R8, R9, R17, R22, and
R25, the VRDZ, VREF, VSUM, BIN1, BIN2, OUT1, and OUT2 pin voltages
can be monitored using a high impedance probe. VBIAS allows for the
external bias voltages to be applied to J1 and J2. If R30 = 0 Ω,
VBIAS = VREF.

Buffer Amplifier/Output Interface. The logarithmic slopes of the ADL5310
can be altered using each buffer’s gain-setting resistors, R5 and R6, and
R18 and R19. R7, R16, R31, R32, C19, and C20 allow for variation in the
buffer loading. R20, R21, C4, C14, C15, and C16 are provided for a variety
of filtering applications.

determines the intercept reference current for each log amp, nominally
set to 3 µA using a 665 kΩ 1% resistor. R2 can be used to adjust the
output offset voltage at the LOG1 and LOG2 outputs.

Supply Decoupling. C2 = C5 = C9 = 100 pF (size 0402)

Input Compensation. Provides essential HF compensation at the Input
Pins INP1, INP2, IRF1, and IRF2.

SMA connectors labeled INP1 and INP2. Through-holes are provided to
connect photodiodes in place of the INP1 and INP2 SMAs for optical
interfacing. By removing R28 (R29 for INP2), a second current can be
applied to the IRF1 (IRF2 for INP2) input (also SMA) for evaluating the
ADL5310 in log ratio applications.

photodiodes.

P1 = installed

P2 = not installed
R1 = R3 = R8 = open (size 0402)
R9 = R17 = open (size 0402)
R22 = R25 = R30 = open (size 0402)

R5 = R19 = 0 Ω (size 0402)
R7 = R16 = 0 Ω (size 0402)
R20 = R21 = 0 Ω (size 0402)
R6 = R18 = open (size 0402)

R31 = R32 = open (size 0402)
C4 = C14 = open (size 0402)

C19 = C20 = open (size 0402)
C15 = C16 = open (size 0402)
LOG1 = OUT1 = installed
LOG2 = OUT2 = installed

R28 = R29 = 665 kΩ (size 0402)
R2 = 0 Ω (size 0402)

C3 = C6 = C8 = 0.01 µF (size 0402)
R4 = R10 = R11 = 0 Ω (size 0402)

R12 = R15 = 1 kΩ (size 0402)
R13 = R14 = 2 kΩ (size 0402)
C10 = C13 = 1 nF (size 0402)
C11 = C12 = 4.7 nF (size 0402)

IREF = INPT = installed

J1 = J2 = open

Rev. A | Page 17 of 20

ADL5310

VSUM

INP1

IRF1

IRF2

INP2

J2

PHOTODIODE

R14

R15

2kΩ

1kΩ

C12

C13

4.7nF

1nF

J1

PHOTODIODE

C1 0.01µF

R1

OPEN

R13
2kΩ

C11

4.7nF

C7 0.01µF

R12
1kΩ

C10
1nF

VNEGVRDZ

VNEG

VNEG

VNEG

R32

OPEN

R8 OPEN
C4 OPEN

OUT1

SCL1

BIN1
LOG1
LOG2

BIN2

SCL2

OUT2

R5 0Ω

OPEN

18

17

16

15

14

13

R19

R17

OPEN

0Ω

R31

3
2

1

3
2

1

R28

665kΩ

VBIAS

R29

665kΩ

VREF

VBIAS

OPEN

R2

0Ω

23 22 21 20 19

24

1

2

3

4

5

6

OPEN

VREF

VSUM
INP1
IRF1
IRF2
INP2
VSUM

VREF

789101112

R9

C5 100pF

C6 0.01µF

VPOS

123

P1

100pF

VRDZ

COMM

ADL5310

VPOS

VPOS

R10

0Ω

AGND

R4
0Ω

C2

COMM

VNEG

C9 100pF

R11
0Ω
C8 0.01µF

C3 0.01µF

R3

C20
OPEN

OPEN

R18

OPEN

R6

R26 0Ω
R27 0Ω

R7 0Ω

C16

OPEN

C14

OPEN

C19
OPEN

R16 0Ω

C15

OPEN

OUT2
OUT2

VREF

VBIAS

OUT1

OUT1

R200ΩR24

R21

0Ω

OUT1

BIN1

LOG1

LOG2

BIN2

OUT2

R30 OPEN

0Ω

R25

OPEN

R22

OPEN

R23

0Ω

1

2

3

4

5

6

7

8

P2

LOG1

LOG1
BIN1
LOG2
BIN2

LOG2

04415-0-040

Figure 40. Evaluation Board Schematic

Rev. A | Page 18 of 20

ADL5310

04415-0-041

Figure 41. Component-Side Layout

Figure 42. Component-Side Silkscreen

04415-0-042

Rev. A | Page 19 of 20

ADL5310

OUTLINE DIMENSIONS

0.60 MAX

19

18

EXPOSED

(BOTTOM VIEW)

13

12

PAD

24

6

7

2.50 REF

1

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

4.00

BSC SQ

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

TOP

VIEW

0.80 MAX

0.65TYP

COMPLIANTTO JEDEC STANDARDS MO-220-VGGD-2

0.05 MAX

0.02 NOM

0.60 MAX

0.50
BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Outline Branding

ADL5310ACP-R2 –40°C to +85°C 24-Lead LFCSP CP-24-1 JQA
ADL5310ACP-REEL7 –40°C to +85°C 24-Lead LFCSP CP-24-1 JQA
ADL5310-EVAL Evaluation Board

1

1

Branding is as follows:
Line 1 — JQA
Line 2 — Lot Code
Line 3 — (Date Code) Date Code is in YYWW format

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04415–0–9/04(A)

Rev. A | Page 20 of 20