Datasheet ADL5306 Datasheet (Analog Devices)

60 dB Range (100 nA to 100 µA)

FEATURES

Optimized for fiber optic photodiode interfacing
Measures current over 3 decades

Law conformance 0.1 dB from 100 nA to 100 μA
Single- or dual-supply operation (3 V to ±5.5 V total)
Full log-ratio capabilities
Temperature stable
Nominal slope of 10 mV/dB (200 mV/decade)
Nominal intercept of 1 nA (set by external resistor)

Optional adjustment of slope and intercept
Rapid response time for a given current level
Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)
Low power: ~5 mA quiescent current

APPLICATIONS

Low cost optical power measurement
Wide range baseband logarithmic compression
Measurement of current and voltage ratios
Optical absorbance measurement

GENERAL DESCRIPTION

The ADL5306∗ is a low cost microminiature logarithmic converter
optimized for determining optical power in fiber optic systems. The
ADL5306 is derived from the AD8304 and AD8305 translinear
logarithmic converters. This family of devices provides wide
measurement dynamic range in a versatile and easy-to-use form. A
single-supply voltage between 3 V and 5.5 V is adequate; dual
supplies may optionally be used. Low quiescent current (5 mA
typical) permits use in battery-operated applications.

I

, the 100 nA to 100 µA input current applied to the INPT pin, is

PD

the collector current of an optimally scaled NPN transistor that
converts this current to a voltage (V
relationship. A second converter is used to handle the reference
current, I

, applied to IREF. These input nodes are biased slightly

REF

above ground (0.5 V). This is generally acceptable for photodiode
applications where the anode does not need to be grounded.
Similarly, this bias voltage is easily accounted for in generating I
The logarithmic front end’s output is available at VLOG.

The basic logarithmic slope at this output is 200 mV/decade
(10 mV/dB) nominal; a 60 dB range corresponds to a 600 mV
output change. When this voltage (or the buffer output) is applied
to an ADC that permits an external reference voltage to be
employed, the ADL5306’s 2.5 V voltage reference output at VREF
can be used to improve scaling accuracy.

) with a precise logarithmic

BE

REF

Low Cost Logarithmic Converter

ADL5306

FUNCTIONAL BLOCK DIAGRAM

+5V

NC

VREF

200kΩ

V

BIAS

1kΩ

1nF

R

REF

1kΩ

1nF

0.5V

IREF

I

PD

INPT

VSUM

1nF

0.5V

20kΩ

80kΩ

COMM

Q2

Q1

VNEG

Figure 1. Functional Block Diagram

The logarithmic intercept (reference current) is nominally
positioned at 1 nA by using the externally generated, 100 µA I
current provided by a 200 kΩ resistor connected between VREF, at

2.5 V, and IREF, at 0.5 V. The intercept can be adjusted over a
narrow range by varying this resistor. The part can also operate in a
log-ratio mode, with limited accuracy, where the numerator and
denominator currents are applied to INPT and IREF, respectively.

A buffer amplifier is provided to drive substantial loads, raise the
basic 10 mV/dB slope, serve as a precision comparator (threshold
detector), or implement low-pass filters. Its rail-to-rail output stage
can swing to within 100 mV of the positive and negative supply
rails, and its peak current-sourcing capacity is 25 mA.

A fundamental aspect of translinear logarithmic converters is that
small-signal bandwidth falls as current level diminishes, and low
frequency noise-spectral density increases. At the 100 nA level, the
ADL5306’s bandwidth is about 100 kHz; it increases in proportion
to I

.

up to a maximum of about 10 MHz. The increase in noise

PD

level at low currents can be addressed by using a buffer amplifier to
realize low-pass filters of up to three poles.

The ADL5306 is available in a 16-lead LFCSP package and is
specified for operation from–40°C to +85°C.

∗

Protected by US Patents 4,604,532 and 5,519,308; other patents pending.

VPOS

2.5V
GENERATOR

V

BE2

TEMPERATURE

COMPENSATION

V

BE1

BIAS

COMM

0.2 log

14.2kΩ

I

6.69kΩ

COMM

LOG

I

PD

10

( )

1nA

451Ω

VOUT

SCAL
BFIN

VLOG

03727-0-001

REF

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADL5306

TABLE OF CONTENTS

Specifications..................................................................................... 3

Response Time and Noise Considerations ............................. 10

Absolute Maximum Ratings............................................................ 4

Pin Configuration and Pin Function Descriptions...................... 5

Typical Performance Characteristics ............................................. 6

General Structure.............................................................................. 9

Theory............................................................................................ 9

Managing Intercept and Slope.................................................. 10

REVISION HISTORY

Rev. 0: Initial Version

Applications..................................................................................... 11

Using a Negative Supply ............................................................ 11

Characterization Methods ........................................................ 12

Evaluation Board............................................................................ 14

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

ADL5306

SPECIFICATIONS

Table 1. VP = 5 V, VN = 0, TA = 25°C, R

Parameter Conditions Min1 Typ Max1 Unit

INPUT INTERFACE INPT (Pin 4), IREF (Pin 3)

Specified Current Range, I

PD

Input Current Min/Max Limits Flows toward INPT pin 1 mA
Reference Current, I

, Range Flows toward IREF pin 100n 100µ A

REF

Summing Node Voltage Internally preset; may be altered by user 0.46 0.5 0.54 V
Temperature Drift

Input Offset Voltage VIN – V

LOGARITHMIC OUTPUT VLOG (Pin 9)

Law Conformance Error 100 nA < IPD < 100 µA 0.1 0.4 dB
Wideband Noise
Small-Signal Bandwidth

3

3

Maximum Output Voltage 1.7 V
Minimum Output Voltage Limited by VN = 0 V 0.01 V
Output Resistance 4.375 5 5.625 kΩ

REFERENCE OUTPUT VREF (Pin 2)

Maximum Output Current Sourcing (grounded load) 20 mA
Incremental Output Resistance Load current < 10 mA 2 Ω

OUTPUT BUFFER BFIN (Pin 10); SCAL (Pin 11); VOUT (Pin 12)

Input Offset Voltage –20 +20 mV
Input Bias Current Flowing out of Pin 10 or Pin 11 0.4

Incremental Input Resistance 35 MΩ
Output Range RL = 1 kΩ to ground VP – 0.1 V

Incremental Output Resistance Load current < 10 mA 0.5 Ω
Peak Source/Sink Current 50 mA
Small-Signal Bandwidth
Slew Rate 0.2 V to 4.8 V output swing 15 V/µs

POWER SUPPLY VPOS (Pin 8); VNEG (Pin 6)

Positive Supply Voltage

Quiescent Current 5.4 6.6 mA

Negative Supply Voltage (Optional)

= 200 kΩ, unless otherwise noted

REF

Flows toward INPT pin 100n 100µ A

–40°C < T

SUM

< +85°C

A

, V

– V

IREF

–20 +20 mV

SUM

0.015

190 200 210 mV/dec Logarithmic Slope
–40°C < TA < +85°C

185 215 mV/dec

0.3 1 1.7 nA Logarithmic Intercept2
–40°C < TA < +85°C

0.1 2.5 nA

IPD > 1 µA 0.7 µV/√Hz
IPD > 1 µA 0.7 MHz

2.435 2.5 2.565 V Voltage wrt Ground
–40°C < TA < +85°C

2.4 2.6 V

GAIN = 1 15 MHz

– VN ) ≤ 11 V

(V

P

– VN ) ≤ 11 V

(V

P

3 5 5.5 V

–5.5 0 V

mV/°C

µA

1

Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.

2

Other values of logarithmic intercept can be achieved by adjusting R

3

Output noise and incremental bandwidth are functions of input current measured using the output buffer connected for GAIN = 1.

.

REF

Rev. 0 | Page 3 of 16

ADL5306

ABSOLUTE MAXIMUM RATINGS

Table 2. ADL5306 Absolute Maximum Ratings

Parameter Rating

Supply Voltage VP – V
Input Current 20 mA
Internal Power Dissipation 500 mW
θJA 135°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C

N

12 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 4 of 16

ADL5306

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

COMMCOMMCOMM

COMM

13141516

VOUT

NC

1

12

VREF

2

SCAL

11

ADL5306

BFIN

VPOS

10

9

03727-0-002

VLOG

IREF

INPT

3

4

5678

VNEGVSUM

VNEG

Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 NC N/A
2 VREF Reference Output Voltage of 2.5 V.
3 IREF Accepts (Sinks) Reference Current I
4 INPT

Accepts (Sinks) Photodiode Current I

.

REF

. Usually connected to photodiode anode such that photocurrent flows

PD

into INPT.
5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential.
6, 7 VNEG Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section.
8 VPOS Positive Supply, ( VP – VN ) ≤ 11 V.
9 VLOG Output of the Logarithmic Front End.
10 BFIN Buffer Amplifier Noninverting Input.
11 SCAL Buffer Amplifier Inverting Input.
12 VOUT Buffer Output.
13–16 COMM Analog Ground.

Rev. 0 | Page 5 of 16

ADL5306

TYPICAL PERFORMANCE CHARACTERISTICS

(VP = 5 V, VN = 0 V, R

1.2
TA= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

1.0

= 200 kΩ, TA = 25°C, unless otherwise noted.)

REF

1.5
TA= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

1.0

0.8

(V)

0.6

LOG

V

0.4

0.2

0

10n 100n 1µ 10µ 100µ 1m

(A)

I

PD

vs. IPD for Multiple Temperatures

LOG

TA= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

(V)

V

LOG

Figure 3. V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

03727-0-003

–40°C

+85°C

0°C

+70°C

+25°C

I

PD

(A)

(I

= 10 µA) for Multiple

PD

REF

03727-0-006

0.5

0

–0.5

ERROR (dB (10mV/dB))

–1.0

–1.5

10n 100n 1µ 10µ 100µ 1m

Figure 6. Law Conformance Error vs. I

Temperatures, Normalized to 25°C

1.5

TA= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

V

N

1.0

+85°C

+70°C

+25°C

–40°C

0°C

–0.5

ERROR (dB (10mV/dB))

–1.0

0.5

0

0

10n 100n 1µ 10µ 100µ 1m

(A)

I

REF

vs. I

Figure 4. V

1.6

1.4

1.2

1.0

(V)

0.8

LOG

V

0.6

0.4

0.2

0

10n 100n 1µ 10µ 100µ 1m

100nA

Figure 5. V

for Multiple Temperatures

LOG

REF

1µA

10µA

100µA

I

(A)

PD

vs. IPD for Multiple Values of I

LOG

REF

(Decade Steps from 10 nA to 1 mA)

–1.5

10n 100n 1µ 10µ 100µ 1m

(A)

03727-0-004

Figure 7. Law Conformance Error vs. I

I

REF

(IPD = 10 µA) for Multiple

REF

03727-0-007

Temperatures, Normalized to 25°C

0.3

0.2

1µA

100µA

IPD (A)

100nA

for Multiple Values of I

PD

03727-0-008

REF

0.1

10µA

0

–0.1

ERROR (dB (10mV/dB))

–0.2

–0.3

10n 100n 1µ 10µ 100µ 1m

03727-0-005

Figure 8. Law Conformance Error vs. I

(Decade Steps from 10 nA to 1 mA)

Rev. 0 | Page 6 of 16

ADL5306

1.6

0.3

1.4

1.2

1.0

(V)

0.8

LOG

V

0.6

0.4

0.2

0

10n 100n 1µ 10µ 100µ 1m

100nA

Figure 9. V

100µA

10µA

1µA

(A)

I

REF

vs. I

for Multiple Values of IPD

LOG

REF

(Decade Steps from 10 nA to 1 mA)

0.3

0.2

–0.1

ERROR (dB (10mV/dB))

–0.2

0.1
+3V, –0.5V

0

+3V, 0V

+5V, 0V

+5V, –5V

03727-0-009

0.2

0.1

100µA

0

1µA

ERROR (dB)

–0.1

–0.2

–0.3

10n 100n 1µ 10µ 100µ 1m

(A)

I

REF

Figure 12. Law Conformance Error vs. I

100nA

10µA

for Multiple Values of IPD

REF

03727-0-012

(Decade Steps from 10 nA to 1 mA)

1.2

(V)

V

OUT

1.0

0.8

0.6

0.4

0.2

10µA TO 100µA:

1µA TO 10µA:

100nA TO 1µA:

t

RISE

t

FALL

t
t

t

RISE

t

FALL

RISE
FALL

< 1µs,

< 1µs

< 1µs,

< 5µs

< 5µs,

< 20µs

–0.3

10n 100n 1µ 10µ 100µ 1m

(A)

I

PD

Figure 10. Law Conformance Error vs. I

for Various Supply Conditions

PD

4

3

2

1

0

–1

ERROR (dB (10mV/dB))

–2

–3

–4

10n 100n 1µ 10µ 100µ 1m

MEAN + 3 @ –40°C

MEAN ±3 @ +85°C

MEAN – 3 @ –40°C

I

PD

Figure 11. V

INPT

(A)

– V

TA = –40°C, +85°C

vs. IPD

SUM

03727-0-010

03727-0-011

0

–20 0 20 40 60 80 100 120 140 160 180

t

RISE

t

FALL

t
t

RISE
FALL

t

RISE

t

FALL

TIME (µs)

= 30µs,

= 5µs

= 5µs,

< 1µs

= 1µs,

< 1µs

TIME (µs)

to V

(G = 1)

PD

OUT

to V

(G = 1)

REF

OUT

Figure 13. Pulse Response: I

1.4

(V)

OUT

V

1.2

1.0

0.8

0.6

0.4

0.2

100nA TO 1µA:

1µA TO 10µA:

10µA TO 100µA:

0

–20 0 20 40 60 80 100 120 140 160 180

Figure 14. Pulse Response: I

03727-0-013

03727-0-014

Rev. 0 | Page 7 of 16

ADL5306

10

5

0

–5

–10

–15

–20

–25

NORMALIZED RESPONSE (dB)

–30

–35

–40

Figure 15. Small-Signal AC Response (5% Sine Modulation), from I

(G = 1) for I

100nA

100k10k1k100 1M 10M 100M

FREQUENCY (Hz)

in Decade Steps from 10 nA to 1 mA

PD

100µA

10µA

1µA

03727-0-015

to V

PD

OUT

5

0

–5

–10

–15

NORMALIZED RESPONSE (dB)

–20

–25

100k10k 1M 10M 100M

Figure 18. Small-Signal AC Response of the Buffer for Various

Av = 5

Av = 2.5

FREQUENCY (Hz)

Av = 1

Av = 2

03727-0-018

Closed-Loop Gains (RL = 1 kΩ, CL < 2 pF)

10

5

0

–5

–10

–15

–20

–25

NORMALIZED RESPONSE (dB)

–30

–35

–40

100nA

100µA

10µA

1µA

100k10k1k100 1M 10M 100M

FREQUENCY (Hz)

Figure 16. Small-Signal AC Response (5% Sine Modulation), from I

(G = 1) for I

100

10

1

µVrms/ Hz

0.1

in Decade Steps from 10 nA to 1 mA

REF

100nA

1µA

10µA

100µA

03727-0-016

to V

REF

OUT

2.0

1.5

1.0

0.5

0

DRIFT (mV)

OS

–0.5

V

–1.0

–1.5

–2.0

–40 –30 –20 –10 0 20 6010 30 40 50 70 80 90

Figure 19. Buffer Input Offset Drift vs. Temperature

MEAN + 3σ

MEAN – 3σ

TEMPERATURE (°C)

03727-0-019

(3σ to Either Side of Mean)

6

5

4

3

mVrms

2

1

0.01
100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 17. Spot Noise Spectral Density at V

for I

in Decade Steps from 10 nA to 1 mA

PD

(G = 1) vs. Frequency

OUT

03727-0-017

Rev. 0 | Page 8 of 16

0

10n 100n 1µ 10µ 100µ 1m

(A)

I

PD

Figure 20. Total Wideband Noise Voltage at V

vs. IPD (G = 1)

OUT

03727-0-020

ADL5306

GENERAL STRUCTURE

The ADL5306 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and is
useful in many nonoptical applications. This section explains
the structure of this unique style of translinear log amp. The
simplified schematic in Figure 21 shows the key elements.

BIAS

GENERATOR

PHOTODIODE

CURRENT

I

PD

INPT

2.5V

INPUT

80kΩ

20kΩ

0.5V

VSUM

0.5V

VNEG (NORMALLY GROUNDED)

VREF

V

BE1

COMM

IREF

Q2Q1

0.5V

I

REF

V

BE1

V

BE2

2.5V

V

BE2

TEMPERATURE
COMPENSATION
(SUBTRACT AND

DIVIDE BY T°K)

44µA/dec

451Ω14.2kΩ

VLOG

6.69kΩ

COMM

03727-0-021

Figure 21. Simplified Schematic

The photodiode current IPD is received at Pin INPT. The voltage
at this node is essentially equal to the voltage on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts I

PD

to a
corresponding logarithmic voltage, as shown in Equation 1. A
finite positive value of V

is needed to bias the collector of Q1

SUM

for the usual case of a single-supply voltage. This is internally
set to 0.5 V, one fifth of the 2.5 V reference voltage appearing on
Pin VREF. The resistance at the VSUM pin is nominally 16 kΩ;
this voltage is not intended as a general bias source.

The ADL5306 also supports the use of an optional negative
supply voltage, V

, at Pin VNEG. Whe n VN is –0.5 V or more

N

negative, VSUM may be connected to ground; thus, INPT and
IREF assume this potential. This allows operation as a voltage­input logarithmic converter by the inclusion of a series resistor
at either or both inputs. Note that the resistor setting, I

REF

, will
need to be adjusted to maintain the intercept value. It should
also be noted that the collector-emitter voltages of Q1 and Q2
are now the full V

, and effects due to self-heating will cause

N

errors at large input currents.

The input-dependent V

of a second transistor, Q2, operating at I

V

BE2

of Q1 is compared with the reference

BE1

. This is

REF

generated externally to a recommended value of 10 µA.
However, other values over a several-decade range can be used
with a slight degradation in law conformance (see Figure 8).

THEORY

The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by the following equation, which immediately
shows its basic logarithmic nature:

= kT/q ln(IC / IS) (1)

V

BE

where:

is the collector current

I

C

is a scaling current, typically only 10

I

S

kT/q is the thermal voltage, proportional to absolute

temperature (PTAT), and is 25.85 mV at 300 K.

is never precisely defined and exhibits an even stronger

I

S

temperature dependence, varying by a factor of roughly a
billion between –35°C and +85°C. Thus, to make use of the BJT
as an accurate logarithmic element, both of these temperature­dependencies must be eliminated.

The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current I
the other operating at a reference current I

– V

V

BE1

= ln(10) kT/q log

= 59.5 mV log

= kT/q ln(IPD / IS) – kT/q ln(I

BE2

/ I

10(IPD

REF

/ I

10(IPD

) (T = 300 K)

REF

The uncertain, temperature-dependent saturation current, I
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperature­corrected current:

I

where I

= IY log10(IPD / I

LOG

is an accurate, temperature-stable scaling current that

Y

) (3)

REF

determines the slope of the function (change in current per
decade). For the ADL5306, IY is 44 µA, resulting in a
temperature-independent slope of 44 µA/decade for all values

and I

of I

PD

voltage-mode output, V

. This current is subsequently converted back to a

REF

, scaled 200 mV/decade.

LOG

–17

A

and

PD

, can be written as

REF

/ IS)

REF

) (2)

,

S

Rev. 0 | Page 9 of 16

ADL5306

It is apparent that this output should be zero for IPD = I
would need to swing negative for smaller values of input
current. To avoid this, I
smallest value of I
is added to V

to shift it upward by 0.8 V. This moves the

LOG

would need to be as small as the

REF

. In the ADL5306, an internal offset voltage

PD

intercept to the left by four decades, from 10 µA to 1 nA:

= IY log10(IPD / I

I

LOG

where I

is the operational / value of the intercept current.

INTC

Since values of I

< I

PD

) (4)

INTC

result in a negative V

INTC

LOG

supply of sufficient value is required to accommodate this
situation (discussed later).

The voltage V

is generated by applying I

LOG

to an internal

LOG

resistance of 4.55 kΩ, formed by the parallel combination of a

6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the
internal 2.5 V reference. At the VLOG pin, the output current

generates a voltage of

I

LOG

= I

V

LOG

= 44 µA × 4.55 kΩ × log10 (IPD / I

× 4.55 kΩ

LOG

) (5)

REF

, and

REF

, a negative

MANAGING INTERCEPT AND SLOPE

As previously noted, the internally generated 2.5 V bias
combines with the on-chip resistors to introduce an accurate
offset voltage of 0.8 V at the VLOG pin, equivalent to four
decades. This results in a logarithmic transfer function that can
be written as

= VY log10 (104 × IPD / I

V

LOG

where I

INTC

= I

REF

/104

Thus, the effective intercept current, I
thousandth of I
recommended value of I

, corresponding to 10 nA when using the

REF

REF

The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged because the on-chip resistors
will not ratio correctly to the added resistance. Also, it is rare
that one would wish to lower the basic slope of 10 mV/dB; if
this is necessary, it should be done at the low impedance output
of the buffer, which is provided to avoid such miscalibration
and allow higher slopes to be used.

)= VY log10 (IPD / I

REF

= 100 µA.

is only one ten-

INTC,

) (6)

INTC

= V

where V

log10 (IPD / I

Y

= 200 mV/decade or 10 mV/dB. Note that any

Y

REF

)

resistive loading on VLOG will lower this slope and will result
in an overall scaling uncertainty due to the variability of the on­chip resistors. Consequently, this practice is not recommended.

may also swing below ground when dual supplies (VP and

V

LOG

) are used. When VN = -0.5 V or more negative, the input

V

N

pins INPT and IREF may be positioned at ground level simply
by grounding VSUM.

The ADL5306 buffer is essentially an uncommitted op amp
with rail-to-rail output swing, good load driving capabilities,
and a unity-gain bandwidth of >20 MHz. In addition to
allowing the introduction of gain using standard feedback
networks, thereby increasing the slope voltage, V

, the buffer

Y

can be used to implement multipole low-pass filters, threshold
detectors, and a variety of other functions. For more details, see
the AD8304 Data Sheet.

RESPONSE TIME AND NOISE CONSIDERATIONS

The response time and output noise of the ADL5306 are
fundamentally a function of the signal current I
currents, the bandwidth is proportional to I
frequency voltage-noise spectral density is a function of I
increases for small values of I

. For details of noise and

REF

bandwidth performance of translinear log amps, see the
AD8304 Data Sheet.

. For small

PD

. The output’s low

PD

PD

, and

Rev. 0 | Page 10 of 16

ADL5306

APPLICATIONS

The ADL5306 is easy to use in optical supervisory systems and
in similar situations where a wide-ranging current is to be
converted to its logarithmic equivalent (i.e., represented in
decibel terms). Basic connections for measuring a single current
input are shown in Figure 22, which includes various
nonessential components, as will be explained.

+5V

VPOS

2.5V
GENERATOR

V

BE2

TEMPERATURE

COMPENSATION

V

BE1

BIAS

0.5 log

14.2kΩ

6.69kΩ

COMM

COMM

I

LOG

I

PD

10

( )

1nA

VLOG

451Ω

VOUT

12kΩ

SCAL
BFIN

C

FLT

10nF

8kΩ

03727-0-022

V

1kΩ

1nF

200kΩ

BIAS

R

1kΩ

1nF

REF

1nF

I

PD

NC

VREF

IREF

INPT

VSUM

0.5V

20kΩ

0.5V

80kΩ

COMM

Q2

Q1

VNEG

Figure 22. Basic Connections for Fixed Intercept Use

The 2 V difference in voltage between VREF and INPT, in
conjunction with the external 200 kΩ resistor R
reference current I

of 100 µA into Pin IREF. The internal

REF

, provides a

REF

reference raises the voltage at VLOG by 0.8 V, effectively
lowering the intercept current I
it at 1 nA. Any temperature variation in R

by a factor of 104 to position

INTC

must be taken into

REF

account when estimating the stability of the intercept. Also, the
overall noise will increase when using very low values of I

REF

. In
fixed-intercept applications, there is little benefit in using a large
reference current, since this only compresses the low current
end of the dynamic range when operated from a single supply,
shown here as 5 V. The capacitor between VSUM and ground is
recommended to minimize the noise on this node and to help
provide a clean reference current.

Since the basic scaling at VLOG is 0.2 V/dec and a swing of 4 V
at the buffer output would therefore correspond to 20 decades,
it will often be useful to raise the slope to make better use of the
rail-to-rail voltage range. For illustrative purposes, the circuit in
Figure 22 provides an overall slope of 0.5 V/dec (25 mV/dB).
Thus, using I
to 0.8 V at I

= 100 µA, V

REF

= 100 µA. The buffer output runs from 0.5 V to

PD

runs from 0.2 V at IPD = 100 nA

LOG

2.0 V, corresponding to a dynamic range of 60 dB electrical
(30 dB optical) power.

The optional capacitor from VLOG to ground forms a single­pole low-pass filter in combination with the 4.55 kΩ resistance
at this pin. For example, using a C

of 10 nF, the –3 dB corner

FLT

frequency is 3.2 kHz. Such filtering is useful in minimizing the
output noise, particularly when I

is small. Multipole filters are

PD

more effective in reducing the total noise. For examples, see the
AD8304 Data Sheet.

The dynamic response of this overall input system is influenced
by the external RC networks connected from the two inputs
(INPT, IREF) to ground. These are required to stabilize the
input systems over the full current range. The bandwidth
changes with the input current due to the widely varying pole
frequency. The RC network adds a zero to the input system to
ensure stability over the full range of input current levels. The
network values shown in Figure 22 will usually suffice, but some
experimentation may be necessary when the photodiode’s
capacitance is high.

Although the two current inputs are similar, some care is
needed to operate the reference input at extremes of current
(<100 nA) and temperature (<0°C). Modifying the RC network
to 4.7 nF and 2 kΩ will allow operation to –40°C at 10 nA. By
inspecting the transient response to perturbations in I

REF

at
representative current levels, the capacitor value can be adjusted
to provide fast rise and fall times with acceptable settling. To
fine-tune the network zero, the resistor value should be
adjusted.

USING A NEGATIVE SUPPLY

Most applications of the ADL5306 require only a single supply
of 3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 23.

+5V

VPOS

2.5V

V

BE2

TEMPERATURE

COMPENSATION

V

BE1

– VF≤ –0.5V

V

SUM

C

1

BIAS

GENERATOR

COMM

0.5 log

14.2kΩ

6.69kΩ

COMM

I

10

LOG

I

PD

( )

1nA

VLOG

451Ω

C
10nF

03727-0-023

VOUT

12k Ω

SCAL
BFIN

FLT

8kΩ

V

1kΩ

1nF

200kΩ

BIAS

R

REF

1kΩ

1nF

I

PD

NC

VREF

80kΩ

20kΩ

COMM

0.5V

IREF

Q2

Q1

INPT

VSUM

0.5V

Iq+ I

= IPD+ I

VN– V

Iq+ I

sig

sigmax

VNEG

REF

F

V

RS≤

V

F

I

sig

N

Figure 23. Negative Supply Application

Rev. 0 | Page 11 of 16

ADL5306

The use of a negative supply, VN, allows the summing node to be
placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When

= –0.5 V, the VCE of Q1 and Q2 will be the same value as in

V

N

the default case when VSUM is grounded. This bias need not be
accurate, and a poorly defined source can be used. However, the
source must be able to support the quiescent current as well as
the INPT and IREF signal current. For example, it may be
convenient to utilize a forward-biased junction voltage of about

0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the
summing node at ground, the ADL5306 may now be used as a
voltage-input log amp, at either the numerator input INPT or
the denominator input IREF by inserting a suitably scaled
resistor from the voltage source to the relevant pin. The overall
accuracy for small input voltages is limited by the voltage offset
at the inputs of the JFET op amps.

The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of I

. However, the voltage V

PD

referenced to the ACOM pin, and while V
negative for default operating conditions, it is free to do so.
Thus, adding a resistor from VLOG to the negative supply
lowers all values of V

, which raises the intercept. The

LOG

disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistance causes errors in both the slope
and intercept. A more accurate method for repositioning the
intercept follows.

remains

LOG

does not swing

LOG

KEITHLEY 236

KEITHLEY 236

TRIAX CONNECTORS

(SIGNAL – INPT AND IREF

GUARD – VSUM

SHIELD – GROUND)

IREF

INPT

VNEG VPOSVREF

ADL5306

CHARACTERIZATION

BOARD

DC MATRIX / DC SUPPLIES / DMM

VOUT

BFIN

VLOG

VSUM

RIBBON

CABLE

03727-0-024

Figure 24. Primary Characterization Setup

The primary characterization setup shown in Figure 24 is used
to measure V

, the static (dc) performance, logarithmic

REF

conformance, slope and intercept, the voltages appearing at Pins
VSUM, INPT, and IREF, and the buffer offset and V

REF

drift
with temperature. In some cases, a fixed resistor between Pins
VREF and IREF was used in place of a precision current source.
For the dynamic tests, including noise and bandwidth
measurements, more specialized setups are required. This
includes close attention to the input stabilizing networks; for
example, to ensure stable operation over the full current range

and temperature extremes, filter components C1 = 4.7 nF

of I

REF

and R13 = 2 kΩ are used at Pin IREF to ground.

HP3577A

NETWORK ANALYZER

OUTPUT INPUT R INPUT A INPUT B

CHARACTERIZATION METHODS

During the characterization of the ADL5306, the device was
treated as a precision current-input logarithmic converter,
because it is impractical to generate accurate photocurrents by
illuminating a photodiode. The test currents were generated by
using either a well-calibrated current source, such as the
Keithley 236, or a high value resistor from a voltage source to
the input pin. Great care is needed when using very small input
currents. For example, the triax output connection from the
current generator was used with the guard tied to VSUM. The
input trace on the PC board was guarded by connecting
adjacent traces to VSUM.

These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GΩ to ground would subtract

0.5 nA from the input, which amounts to a –0.44 dB error for a
10 nA source current. Additionally, the very high output
resistance at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reducing the pickup of these
spurious signals.

13141516

VNEG

COMMCOMMCOMM COMM

VOUT

SCAL

BFIN

VLOG

VPOS

12

11

10

9

+V

0.1µF

03727-0-025

S

+IN B

AD8138

EVALUATION

BOARD

AD8138 PROVIDES DC OFFSET

A

BNC-T

NC

1

VREF

2

ADL5306

IREF

3

INPT

4

VNEGVSUM

5678

Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement

Figure 25 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
provisions to offset V
measurements over the full range of I

at the buffer input, allowing

LOG

using a single supply.

PD

The network analyzer input impedances are set to 1 MΩ.

Rev. 0 | Page 12 of 16

ADL5306

A

HP3577A

NETWORK ANALYZER

OUTPUT INPUT R INPUT A INPUT B

VNEG

13141516

COMMCOMMCOMM COMM

VOUT

SCAL

BFIN

VLOG

VPOS

12

11

10

9

+V

µ

0.1

03727-0-026

S

F

+IN B

AD8138

EVALUATION

BOARD

POWER

SPLITTER

R1

A

1nF 1nF

NC

1

VREF

2

R2

1kΩ1kΩ

ADL5306

IREF

3

INPT

4

VNEGVSUM

5678

Figure 26. Configuration for Logarithmic Amplifier Bandwidth Measurement

Figure 26 shows the configuration used for frequency response
measurements of the logarithmic amplifier section. The
AD8138 output is offset to 1.5 V dc and modulated to a depth
of 5% at frequency. R1 is chosen (over a wide range of values up
to 1.0 GΩ) to provide I

. The buffer is used to deload VLOG.

PD

HP89410A

The configuration of Figure 27 is used to measure the noise
performance. Batteries provide both the supply voltage and the
input current in order to minimize the introduction of spurious
noise and ground loop effects. The entire evaluation system,
including the current setting resistors, is mounted in a closed
aluminum enclosure to provide additional shielding to external
noise sources.

LeCROY 9210

9213

R1

CH A

200kΩ

1kΩ50kΩ

1nF

1kΩ

1nF

16

NC

1

VREF

2

IREF

3

INPT

4

Figure 28. Configuration for Logarithmic Amplifier Pulse Response

Measurement

TDS5104

131415

COMMCOMMCOMM COMM

VOUT

SCAL

ADL5306

VNEGVSUM

5678

VNEG

BFIN

VLOG

VPOS

12

11

10

9

+V

0.1µF

CH 1

S

03727-0-028

SOURCE TRIGGER CHANNEL 1 CHANNEL 2

13141516

COMMCOMMCOMM COMM

VNEG

0.1

VOUT

SCAL

BFIN

VLOG

VPOS

µ

F

LKALINE

"D" CELL

NC

1

VREF

200k

R1

1k

1nF

2

Ω

1k

Ω

Ω

1nF

ADL5306

IREF

3

INPT

4

VNEGVSUM

5678

Figure 27. Configuration for Noise Spectral Density Measurement

12

11

10

9

ALKALINE
"D" CELL

03727-0-027

Figure 28 shows the setup used to make the pulse response
measurements. As with the bandwidth measurement, VLOG is
connected directly to BFIN and the buffer amplifier is
configured for a gain of 1. The buffer’s output is connected
through a short cable to the TDS5104 scope, with the input
impedance set to 1 MΩ. The LeCroy’s output is offset to create
the initial pedestal current for a given R1 value. The pulse then
creates a 1-decade current step.

Rev. 0 | Page 13 of 16

ADL5306

EVALUATION BOARD

An evaluation board is available for the ADL5306, the schematic
of which is shown in 29. It can be configured for a wide variety
of experiments. The buffer gain is factory-set to unity, providing

Table 4. Evaluation Board Configuration Options

Component Function Default Conditions

P1

P2, R8, R9, R10, R18

R2, R3, R4, R6, R11, R14, C2, C7, C9, C10

R1, R19

R12, R15, C3, C4, C5, C6

C11
R13, R16, C1, C8

IREF, INPT, PD, LK1, R5

J1

Supply Interface. Provides access to supply pins VNEG,
COMM, and VPOS.

Monitor Interface. By adding 0 Ω resistors to R8, R9, R10,
and R18, the VREF, VSUM, VOUT, and VLOG pin voltages
can be monitored using a high impedance probe.

Buffer Amplifier/Output Interface. The logarithmic slope
of the ADL5306 can be altered using the buffer’s gain­setting resistors, R2 and R3. R4, R6, R11, R14, C2, C7, C9, and
C10 are provided for a variety of filtering applications.

Intercept Adjustment. The voltage dropped across
resistor R1 determines the intercept reference current,

nominally set to 10 µA using a 200 kΩ 1% resistor.

Supply Decoupling

Filtering VSUM
Input Compensation. Provides essential HF compensation

at the input pins, INPT and IREF.
Input Interface. The test board is configured to accept a

current through the SMA connector labeled INPT. An SC
style packaged photodiode can be used in place of the
INPT SMA for optical interfacing. By removing R1 and
adding a 0 Ω short for R5, a second current can be applied
to the IREF input (also SMA) for evaluating the ADL5306 in
log-ratio applications.

SC Style Photodiode

a slope of 200 mV/dec, and the intercept is set to 1 nA. Table 4
describes the various configuration options.

P1 = Installed

P2 = Not Installed
R8 = R9 = R10 = Open (Size 0603)
R18 = Open (Size 0603)
R2 = R6 = 0 Ω (Size 0603)
R3 = R4 = Open (Size 0603)
R11 = R14 = 0 Ω (Size 0603)
C2 = C7 = Open (Size 0603)
C9 = C10 = Open (Size 0603)
VLOG = VOUT = Installed
R1 = 200 kΩ (Size 0603)
R19 = 0 Ω (Size 0603)

C3 = C4 = 0.01 µF (Size 0603)
C5 = C6 = 0.1 µF (Size 0603)

R12 = R15 = 0 Ω (Size 0603)
C11 = 1 nF (Size 0603)
R13 = R16 = 1 kΩ (Size 0603)
C1 = C8 = 1 nF (Size 0603)
IREF = INPT = Installed
PD = Not Installed
LK1 = Installed
R5 = Open (Size 0603)

J1 = Open

Rev. 0 | Page 14 of 16

ADL5306

R10

13141516

COMMCOMMCOMM COMM

VOUT

12

R2
0

Ω

C7

OPEN

R3

OPEN

R6

Ω

0

C10

OPEN

SCAL

11

BFIN

10

VLOG

9

VPOS

VNEG

C4

µ

F

0.01

C5

0.1

µ

AGND

F

VPOS

P1 P2

AGND

VOUT

VREF

VSUM

VLOG

C9

OPEN

C2

OPEN

1

2

3

4

5

R4

OPEN

OPEN

R8

R11

0

VREF

IREF

SC-STYLE
PD

INPT

OPEN

OPEN

1

2
3

LK1

C11 C8

1nF

R18

R5

R9

VSUM

OPEN

R1
200k
1%

R13
1k

C1
1nF

NC

1

R19

0

Ω

Ω

R16

VREF

2

Ω

I

REF

I

PD

1k

Ω

1nF

ADL5306

IREF

3

INPT

4

VNEGVSUM

5678

C3

µ

F

0.01

C6

0.1

µ

F

VNEG

123

Figure 29. Evaluation Board Schematic

OPEN

R14

0

Ω

VOUT

VOUT

Ω

VLOG

VLOG

03727-0-029

Figure 30. Component Side Layout

03727-0-030

Rev. 0 | Page 15 of 16

03727-0-031

Figure 31. Component Side Silkscreen

ADL5306

R

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.90

0.80

SEATING

PLANE

3.00

BSC SQ

TOP

VIEW

12°MAX 0.80 MAX

0.30

0.23

0.18

2.75

BSC SQ

0.65 NOM

0.05 MAX

0.01 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

Figure 32. 16-Lead Leadframe Chip Scale Package [LFCSP]

(CP-16)

Dimensions shown in millimeters

BOTTOM

VIEW

0.50

0.40

0.30

1

2

PIN 1 INDICATO

1.45

1.30

SQ

1.15

0.25 MIN

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ORDERING GUIDE

ADL5306 Products Temperature Package Package Description Package Outline Branding1

ADL5306ACP2 –40°C to +85°C 16-Lead LFCSP CP-16 JSA

ADL5306ACP-R2 –40°C to +85°C Tape and Reel CP-16 JSA

ADL5306ACP-REEL7 –40°C to +85°C 7” Tape and Reel CP-16 JSA

ADL5306-EVAL Evaluation Board

1

Branding is as follows:
Line 1—Logo
Line 2—JSA
Line 3—K (Date Code). Date code is in YWW format.

2

Contact factory for availability.

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C03727–0–7/03(0)

Rev. 0 | Page 16 of 16