Datasheet ADL5201 Datasheet (ANALOG DEVICES)

Wide Dynamic Range, High Speed,

Data Sheet

FEATURES

−11.5 dB to +20 dB gain range

0.5 dB ± 0.1 dB step size
150 Ω differential input and output

7.5 dB noise figure at maximum gain
OIP3 > 50 dBm at 200 MHz

−3 dB upper frequency bandwidth of 700 MHz
Multiple control interface options

Parallel 6-bit control interface (with latch)
Serial peripheral interface (SPI) (with fast attack)

Gain up/down mode
Wide input dynamic range
Low power mode option
Power-down control
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP package

APPLICATIONS

Differential ADC drivers
High IF sampling receivers
High output power IF amplification
Instrumentation

MODE0,
MODE1

VIN+

VIN–

PM

Digitally Controlled VGA

ADL5201

FUNCTIONAL BLOCK DIAGRAM

SPI WITH FA,

PARALLEL WITH LATCH,

UP/DOWN I NTERFACE VPOS GND PWUP

LOGIC

150Ω 150Ω

0dB TO 31.5dB

+20dB

ADL5201

Figure 1.

VOUT+

VOUT–

09388-001

GENERAL DESCRIPTION

The ADL5201 is a digitally controlled, variable gain, wide band­width amplifier that provides precise gain control, high IP3, and
low noise figure. The excellent distortion performance and high
signal bandwidth make the ADL5201 an excellent gain control
device for a variety of receiver applications. The ADL5201 also
incorporates a low power mode option that lowers the supply
current.

For wide input dynamic range applications, the ADL5201 provides
a broad 31.5 dB gain range with 0.5 dB resolution. The gain is
adjustable through multiple gain control interface options: parallel,
serial peripheral interface, and up/down.

Incorporating proprietary distortion cancellation techniques,
the ADL5201 achieves an output IP3 of greater than 47 dBm at
frequencies approaching 200 MHz for most gain settings.

The ADL5201 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the ADL5201
is typically 80 mA in low power mode. When configured in high
performance mode for more demanding applications, the quiescent
current is 110 mA. When powered down, the ADL5201 consumes
less than 7 mA and offers excellent input-to-output isolation.
The gain setting is preserved during power-down.

Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5201 provides precise gain adjustment capabilities with
good distortion performance and low phase error. The ADL5201
amplifier comes in a compact, thermally enhanced, 24-lead,
4 mm × 4 mm LFCSP package and operates over the temperature
range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADL5201 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Characterization and Test Circuits............................................... 14

Theory of Operation ......................................................................15

Digital Interface Overview ........................................................ 15

Parallel Digital Interface............................................................ 15

Serial Peripheral Interface (SPI)............................................... 15

Up/Down Interface .................................................................... 15

Circuit Description......................................................................... 17

Basic Structure............................................................................ 17

Input System ............................................................................... 17

Output Amplifier........................................................................ 17

Gain Control............................................................................... 17

Applications Information.............................................................. 18

Basic Connections...................................................................... 18

ADC Driving............................................................................... 18

Layout Considerations............................................................... 20

Evaluation Board............................................................................ 21

Evaluation Board Control Software......................................... 21

Schematics and Artwork ...........................................................22

Evaluation Board Configuration Options............................... 24

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

10/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

Data Sheet ADL5201

SPECIFICATIONS

VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V
Slew Rate
Input Return Loss (S11) 100 MHz
Output Return Loss (S22) 100 MHz

INPUT STAGE VIN+ and VIN− pins

Maximum Input Swing (Differential) Gain code = 111111
Differential Input Resistance
Common-Mode Input Voltage
CMRR Gain code = 000000

GAIN

Maximum Voltage Gain Gain code = 000000 20 dB
Minimum Voltage Gain Gain code = 111111 −11.5 dB
Gain Step Size 0.5 dB
Gain Flatness 30 MHz < fC < 200 MHz 0.285 dB
Gain Temperature Sensitivity Gain code = 000000

Gain Step Response For VIN = 0.2 V, gain code = 111111 to 000000
Gain Conformance Error Over 10 dB gain range
Phase Conformance Error Over 10 dB gain range

OUTPUT STAGE VOUT+ and VOUT− pins

Output Voltage Swing At P1dB, gain code = 000000
Differential Output Resistance Differential

NOISE/HARMONIC PERFORMANCE

46 MHz Gain code = 000000, high performance mode

Second Harmonic V
Third Harmonic V
Output IP3 (OIP3) V

70 MHz Gain code = 000000, high performance mode

Second Harmonic V
Third Harmonic V
Output IP3 (OIP3) V

140 MHz Gain code = 000000, high performance mode

Noise Figure
Second Harmonic V
Third Harmonic V
Output IP3 (OIP3) V
Output 1 dB Compression Point (OIP1dB)

300 MHz Gain code = 000000, high performance mode

Second Harmonic V
Third Harmonic V
Output IP3 (OIP3) V

< 2 V p-p (5.2 dBm)

OUT

700

5.5

−18.73

−18.8

MHz
V/ns
dB
dB

10.8
150

1.5

51.44

V p-p
Ω
V
dB

0.0089 dB/°C
15 ns
±0.03 dB

1.0 Degrees

10
150

V p-p
Ω

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p composite

OUT

−86

−104
50

dBc
dBc
dBm

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p composite

OUT

−91

−103
51

dBc
dBc
dBm

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p composite

OUT

7.5

−89

−97
51

19.8

dB
dBc
dBc
dBm
dBm

= 2 V p-p

OUT

= 2 V p-p

OUT

= 2 V p-p composite

OUT

−85

−90
50

dBc
dBc
dBm

Rev. 0 | Page 3 of 28

ADL5201 Data Sheet

Parameter Test Conditions/Comments Min Typ Max Unit

POWER-UP INTERFACE PWUP pin

Power-Up Threshold Minimum voltage to enable the device 1.4 V

Maximum voltage to enable the device 3.3 V

PWUP Input Bias Current 1 μA
GAIN CONTROL INTERFACE

VIH Minimum/maximum voltage for a logic high 1.4 3.3 V

VIL Maximum voltage for a logic low 0.8

Maximum Input Bias Current 1 μA
SPI TIMING LATCH, SCLK, SDIO, data pins

f

1/t

SCLK

tDH Data hold time 5 ns

tDS Data setup time 5 ns

tPW SCLK high pulse width 5 ns
POWER INTERFACE

Supply Voltage 4.5 5.5 V

Quiescent Current High performance mode

85°C

Low power mode

85°C

Power-Down Current PWUP low

20 MHz

SCLK

110 mA
120 mA
80 mA

95 mA

7 mA

TIMING DIAGRAMS

SCLK

t

DS

CS

tDSt

DH

SDIO

DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0

t

SCLK

t

PW

Figure 2. SPI Interface Read/Write Mode Timing Diagram

UPDN_DAT

UPDN_CLK

t

PW

DNUP

t

DS

Figure 3. Up/Down Mode Timing Diagram

LATCH

t

DH

09388-002

t

t

DS

DS

RESET

t

DH

09388-003

A5 TO A0

t

DH

Figure 4. Parallel Mode Timing Diagram

Rev. 0 | Page 4 of 28

09388-104

Data Sheet ADL5201

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage, VPOS 5.5 V
PWUP, A0 to A5, MODE0, MODE1, PM, LATCH 3.6 V
Input Voltage, VIN+ and VIN− +3.6 V to −1.2 V
Internal Power Dissipation 676.5 mW
θJA (Exposed Paddle Soldered Down) 37.16°C/W
θJC (at Exposed Paddle) 2.29°C/W
Maximum Junction Temperature 140°C
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Lead Temperature (Soldering, 60 sec) 240°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 28

ADL5201 Data Sheet

P

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPOS

VPOS
23

24

1

GND

2

VIN+

3

VIN–

GND

MODE1

MODE0

NOTES

1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
A LOW I MPEDANCE GROUND PAD.

4

5

6

ADL5201

TOP VIEW

(Not to Scale)

8

7

SDIO/A5

SCLK/A4

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.
2 VIN+ Positive Input.
3 VIN− Negative Input.
5 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.
6 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.
7 SDIO/A5

Serial Data Input/Output (SDIO). When CS
Bit 5 for Parallel Gain Control Interface (A5).

8 SCLK/A4

Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Parallel Gain Control Interface (A4).

9

/A3 MSB for Gain Step Size Control in Up/Down Mode (GS1).

GS1/CS

SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface.
Bit 3 for Parallel Gain Control Interface (A3).

10 GS0/FA/A2

LSB for Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack (FA). In serial mode, a logic high (1.4 V ≤ FA ≤ 3.3 V) attenuates according to the FA setting in the SPI
word. Bit 2 for Parallel Gain Control Interface (A2).

11 UPDN_CLK/A1

Clock Interface for Up/Down Function (UPDN_CLK).
Bit 1 for Parallel Gain Control Interface (A1).

12 UPDN_DAT/A0

Data Pin for Up/Down Function (UPDN_DAT).
Bit 0 for Parallel Gain Control Interface (A0).

13 LATCH

A logic low (0 V ≤ LATCH ≤ 0.8 V) allows gain changes. A logic high (1.4 V ≤ LATCH ≤ 3.3 V) disallows gain

changes.
14, 16 VOUT+ Positive Output.
15, 17 VOUT− Negative Output.
18, 21,

VPOS Positive Power Supply.

22, 23, 24
19 PWUP Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part.
20 PM

Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V)

enables low power mode.

U

PM

PW

VPOS

VPOS

21

20

22

19

18

VPOS

17

VOUT–

16

OUT+

V

15

VOUT–

14

VOUT+

H

LATC

13

9

11

12

10

GS0/FA/A2

GS1/CS/A3

PDN_CLK/A1

UPDN_DAT/A0

U

09388-004

is pulled low, SDIO is used for reading and writing to the SPI port.

Rev. 0 | Page 6 of 28

Data Sheet ADL5201

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 200 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.

25

20

15

10

5

GAIN (dB)

0

–5

–10

–15

0 10203040506070

GAIN CODE

46MHz
140MHz
300MHz

Figure 6. Gain vs. Gain Code at 46 MHz, 140 MHz, and 300 MHz

09388-005

25

20dB
19dB

20

15

10

5

0

GAIN (dB)

–5

–10

–15

4dB
3dB

–20

10 100 1000

2dB
1dB

18dB
17dB

0dB
–1dB

16dB

14dB

15dB

13dB

–2dB

–4dB

–3dB

–5dB

FREQUENCY (MHz)

12dB
11dB

–6dB
–7dB

10dB
9dB

–8dB
–9dB

8dB
7dB

Figure 9. Gain vs. Frequency Response (Every 1 dB Step)

6dB
5dB

–10dB
–11dB

09388-008

45

40

35

30

25

20

15

NOISE F IGURE (d B)

10

5

0

–15 –10 –5 0 5 10 15 20 25

PROGRAMMED G AIN (dB)

Figure 7. Noise Figure vs. Programmed Gain at 140 MHz

25

20

15

10

OP1dB (dBm)

INPUT

MAX RATINGS

5

BOUNDARY

0

–15 –10 –5 0 5 10 15 20 25

PROGRAMMED GAIN (dB)

Figure 8. OP1dB vs. Programmed Gain at 140 MHz

45

40

35

30

25

20

15

NOISE FIGURE (d B)

10

5

0

09388-006

TA = –40°C TA = +25°C TA = +85°C

MIN GAIN (–11. 5dB)

MID GAIN (+5dB)

MAX GAIN (+20dB)

0 100 200 300 400 500 600

FREQUENCY (MHz)

09388-009

Figure 10. Noise Figure vs. Frequency at Max, Mid, and Min Gain Outputs

20

18

16

14

TA = –40°C

12

T

= +25°C

A

T

= +85°C

A

10

8

OP1dB (dBm)

6

4

2

0

0 50 100 150 200 250 300 350 400

09388-007

FREQUENCY (MHz)

09388-010

Figure 11. OP1dB vs. Frequency at Maximum Gain, Three Temperatures

Rev. 0 | Page 7 of 28

ADL5201 Data Sheet

–

–

60

–11.5dB
0dB
+10dB
+20dB

55

50

45

OIP3 (dBm)

40

35

30

0 50 100 150 200 250 300 350 400

FREQUENCY (MHz)

Figure 12. Output Third-Order Intercept vs. Frequency

at Four Gain Codes

60

TA = –40°C

= +25°C

T

A

= +85°C

T

A

55

50

45

OIP3 (dBm)

40

09388-011

60

–11.5dB
0dB
+10dB

55

+20dB

50

45

40

OIP3 (dBm)

35

30

25

20

–4 –3 –2 –1 0 1 2 3 4 5 6

P

(dBm)

OUT

INPUT

MAX RATINGS

BOUNDARY

Figure 15. Output Third-Order Intercept vs. Power at Four Gain Codes,

Frequency = 140 MHz at 2 V p-p Composite

60

TA = –40°C
T

= +25°C

A

T

= +85°C

A

55

50

45

OIP3 (dBm)

40

09388-014

35

30

0 50 100 150 200 250 300 350 400

FREQUENCY ( MHz)

Figure 13. Output Third-Order Intercept vs. Frequency,

Three Temperatures at 2 V p-p Composite

60

46MHz
140MHz
300MHz

–70

–80

–90

IMD3 (dBc)

–100

–110

–120

–15 –10 –5 0 5 10 15 20 25

PROGRAMME D GAIN (dB)

Figure 14. Two-Tone Output IMD3 vs. Programmed Gain

at 46 MHz, 140 MHz, and 300 MHz

35

30

–4 –3 –2 –1 0 1 2 3 4 5 6

P

(dBm)

09388-012

OUT

09388-015

Figure 16. Output Third-Order Intercept vs. Power, Frequency = 140 MHz,

Three Temperatures

60

TA = –40°C

= +25°C

T

A

= +85°C

T

A

–70

–80

–90

IMD3 (dBc)

–100

–110

–120

0 50 100 150 200 250 300 350 400

09388-013

FREQUENCY (MHz)

09388-016

Figure 17. Two-Tone Output IMD3 vs. Frequency,

Three Temperatures

Rev. 0 | Page 8 of 28

Data Sheet ADL5201

–

–

–

–

–

–

–

–50

–11.5dB
0dB

–60

+10dB
+20dB

–70

–80

–90

–100

–110

–120

–130

HARMONIC DI STORTI ON HD2 (dBc)

–140

–150

0 50 100 150 200 250 300 350

FREQUENCY (MHz)

Figure 18. Harmonic Distortion vs. Frequency at Four Gain Codes

60

TA = –40°C
T

= +25°C

A

–70

T

= +85°C

A

–80

–90

–100

20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

40

–50

–60

–70

–80

HARMONIC DI STORTI ON HD3 (dBc)

60

–11.5dB
0dB
+10dB

–70

+20dB

–80

–90

–100

–110

–120

HARMONIC DIS TORTION HD2 (d Bc)

–130

–140

–6–5–4–3–2–10123456

P

(dBm)

09388-017

OUT

40

–50

–60

–70

–80

–90

–100

–110

–120

HARMONIC DIS TORTION HD3 (d Bc)

09388-020

Figure 21. Harmonic Distortion vs. Power at Four Gain Codes,

Frequency = 140 MHz

60

–70

–80

–90

–90

–100

–110

80

TA = –40°C

= +25°C

T

A

= +85°C

T

A

–110

–120

HARMONIC DIS TORTION HD2 (dBc)

–130

–140

0 50 100 150 200 250 300 350

FREQUENCY (MHz)

–90

–100

–110

–120

Figure 19. Harmonic Distortion vs. Frequency, Three Temperatures

25

20

15

10

OP1dB (dBm)

INPUT

MAX RATING S

5

BOUNDARY

0

–15 –10 –5 0 5 10 15 20 25

PROGRAMMED GAIN (dB)

Figure 20. OP1dB vs. Programmed Gain at 140 MHz, Low Power Mode

HARMONIC DIS TORTION HD3 (dBc)

–120

–130

HARMONIC DIS TORTIO N HD2 (dBc)

–140

–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6

P

(dBm)

09388-018

OUT

–100

–110

–120

HARMONIC DIS TORTIO N HD3 (dBc)

09388-021

Figure 22. Harmonic Distortion vs. Power, Frequency = 140 MHz,

Three Temperatures

20

18

16

14

TA = –40°C

12

T

= +25°C

A

T

= +85°C

A

10

8

OP1dB (dBm)

6

4

2

0

0 50 100 150 200 250 300 350 400

09388-019

FREQUENCY (MHz)

09388-022

Figure 23. OP1dB vs. Frequency at Maximum Gain, Three Temperatures,

Low Power Mode

Rev. 0 | Page 9 of 28

ADL5201 Data Sheet

–

60

–11.5dB
0dB
+10dB

55

+20dB

50

60

–11.5dB
0dB

55

+10dB
+20dB

50

45

45

OIP3 (dBm)

40

35

30

0 50 100 150 200 250 300 350 400

FREQUENCY (MHz)

Figure 24. Output Third-Order Intercept vs. Frequency

at Four Gain Codes, Low Power Mode at 2 V p-p Composite

60

TA = –40°C
T

= +25°C

A

T

= +85°C

A

55

50

45

OIP3 (dBm)

40

35

30

0 50 100 150 200 250 300 350 400

FREQUENCY (MHz)

Figure 25. Output Third-Order Intercept vs. Frequency,

Three Temperatures, Low Power Mode

60

46MHz
140MHz
300MHz

–70

40

OIP3 (dBm)

35

30

25

20

–4 –3 –2 –1 0 1 2 3 4 5 6

09388-023

P

(dBm)

OUT

INPUT

MAX RATINGS

BOUNDARY

09388-026

Figure 27. Output Third-Order Intercept vs. Power at Four Gain Codes,

Frequency = 140 MHz, Low Power Mode

60

TA = –40°C
T

= +25°C

A

T

55

50

45

OIP3 (dBm)

40

35

30

09388-024

= +85°C

A

–4 –3 –2 –1 0 1 2 3 4 5 6

P

(dBm)

OUT

09388-027

Figure 28. Output Third-Order Intercept vs. Power,

Three Temperatures, Low Power Mode at 2 V p-p Composite

–60

TA = –40°C

= +25°C

T

A

= +85°C

T

A

–70

–80

–90

IMD3 (dBc)

–100

–110

–120

–15 –10 –5 0 5 10 15 20 25

PROGRAMMED GAIN (dB)

Figure 26. Two-Tone Output IMD3 vs. Programmed Gain

at 46 MHz, 140 MHz, and 300 MHz; Low Power Mode

09388-025

–80

–90

IMD3 (dBc)

–100

–110

–120

0 50 100 150 200 250 300 350 400

FREQUENCY (MHz)

Figure 29. Two-Tone Output IMD3 vs. Frequency,

Three Temperatures, Low Power Mode

09388-028

Rev. 0 | Page 10 of 28

Data Sheet ADL5201

–

–

–

–

–

–

–

–

O

50

–11.5dB
0dB

–60

+10dB
+20dB

–70

–80

–90

–100

–110

–120

–130

HARMONIC DISTORTION HD2 (dBc)

–140

–150

0 50 100 150 200 250 300 350

FREQUENCY (MHz)

Figure 30. Harmonic Distortion vs. Frequency at Four Gain Codes,

Low Power Mode

50

TA = –40°C
T

= +25°C

A

–60

T

= +85°C

A

–70

–80

–90

–100

–110

–120

–130

HARMONIC DIS TORTI ON HD2 (dBc)

–140

–150

0 50 100 150 200 250 300 350

FREQUENCY ( MHz)

Figure 31. Harmonic Distortion vs. Frequency, Three Temperatures,

Low Power Mode

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

20

HARMONIC DISTORTION HD3 (dBc)

09388-029

60

–11.5dB
0dB
+10dB

–70

+20dB

–80

–90

–100

–110

–120

HARMONIC DIS TORTIO N HD2 (dBc)

–130

–140

–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6

P

(dBm)

OUT

40

–50

–60

–70

–80

–90

–100

–110

–120

HARMONIC DIS TORTIO N HD3 (dBc)

09388-032

Figure 33. Harmonic Distortion vs. Power at Four Gain Codes,

Frequency = 140 MHz, Low Power Mode

70

TA = –40°C
T

= +25°C

A

T

= +85°C

A

–80

–90

–100

–110

HARMONIC DIS TORTI ON HD3 (dBc)

09388-030

–120

HARMONIC DI STORTION HD2 (d Bc)

–130

–6–5–4–3–2–10123456

P

(dBm)

OUT

50

–60

–70

–80

–90

–100

–110

HARMONIC DI STORTION HD3 (d Bc)

09388-033

Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz,

Three Temperatures, Low Power Mode

CH4 1mV/DIV

CH1 200mV/DIV

VOLTAGE

CH1 200mV/DIV

TIME (10ns/DIV)

Figure 32. Enable Time Domain Response

09388-031

LTAG E
V

TIME (10ns/DIV )

Figure 35. Disable Time Domain Response

CH4 1V/DIV

09388-034

Rev. 0 | Page 11 of 28

ADL5201 Data Sheet

A

CH2 500mV/DIV

CH3 50mV/DIV

VO LTAG E

TIME (10ns/DI V)

Figure 36. Gain Step Time Domain Response

0

–10

–20

–30

–40

–50

S11 MAGNITUDE (d B)

–60

MAGNITUDE MAX GAIN

–70

MAGNITUDE MIN GAIN
PHASE MAX GAIN
PHASE MIN GAIN

–80

10 100 1000

FREQUENCY ( MHz)

Figure 37. S11 Magnitude and Phase vs. Frequency

200

150

100

50

0

–50

–100

–150

–200

0pF

INPUT

VO LTAG E

200mV/DIV

09388-035

TIME (1ns/DIV)

5.6pF DIFFERENTIAL

09388-038

Figure 39. Large Signal Pulse Response, 0 pF and 5.6 pF, 2 V p-p Composite

0

–10

–20

–30

–40

–50

–60

S11 PHASE (Degrees)

09388-036

–70

S22 MAGNITUDE (dB)

–80

MAGNITUDE MAX GAIN
MAGNITUDE MIN GAIN

–90

PHASE MAX GAIN
PHASE MIN GAI N

–100

10 100 1000

FREQUENCY ( MHz)

300

250

200

150

100

50

0

–50

–100

–150

–200

S22 PHASE (Degrees)

09388-039

Figure 40. S22 Magnitude and Phase vs. Frequency

1.0

0.8

0.6

0.4

0.2

0

–0.2

GAIN ERRO R (dB)

–0.4

–0.6

–0.8

–1.0

–15 –10 –5 0 5 10 15 20 25

PROGRAMMED GAIN (dB)

Figure 38. Gain Step Error, Frequency = 140 MHz

0

–10

–20

TION (dB)

–30

–40

–50

REVERSE ISOL

–60

–70

10 100 1000

09388-037

FREQUENCY (MHz)

09388-041

Figure 41. Reverse Isolation vs. Frequency

Rev. 0 | Page 12 of 28

Data Sheet ADL5201

A

A

A

1.0
MIN
MID
MAX

0.8

0.6

Y (ns)

0.4

GROUP DEL

0.2

0

10 100 1000

FREQUENCY (MHz)

Figure 42. Group Delay vs. Frequency at Max, Mid, and Min Gain Outputs

4.0

3.5

3.0

350MHz

2.5

300MHz
250MHz

TION (Degrees)

PHASE VARI

200MHz

2.0

150MHz
100MHz

1.5

1.0

0.5

50MHz

0

0 10203040506070

GAIN CODE

Figure 43. Phase Variation vs. Gain Code

0

–10

–20

TION (dB)

–30

–40

REVERSE ISOL

–50

–60

09388-042

10 100 1000

FREQUENCY (MHz)

09388-044

Figure 44. Disable-State Reverse Isolation vs. Frequency

60

50

40

30

20

10

COMMON-MO DE REJECTIO N RATIO, CMRR (dB)

0

10 100 1000

09388-043

FREQUENCY (M Hz)

09388-045

Figure 45. Common-Mode Rejection Ratio vs. Frequency

Rev. 0 | Page 13 of 28

ADL5201 Data Sheet

V

A

V

CHARACTERIZATION AND TEST CIRCUITS

C1 C3

50Ω

C

50Ω

Figure 46. Test Circuit for S-Parameters on Dedicated 50 Ω Differential-to-Differential Board

TC3-1T

T1

50Ω

AC

0.1µF

ADL5201

0.1µF
C2 C4

6

A0 TO A5

L1

C1

0.1µF

1µHL21µH

ADL5201

C2

0.1µF

6

A0 TO A5

Figure 47. Test Circuit for Distortion, Gain, and Noise

L1

1µHL21µH

+5

+5

0.1µF

50Ω TRACES50Ω TRACES

0.1µF

C3

R1

0.1µF

62Ω

PAD LOSS = 11dB

R2

C4

62Ω

0.1µF

R4
25Ω

R3
25Ω

ETC1-1-13

50Ω

AC

50Ω

09388-046

T2

50Ω

09388-047

09388-048

Figure 48. Differential-to-Differential Characterization Board

Rev. 0 | Page 14 of 28

Data Sheet ADL5201

THEORY OF OPERATION

DIGITAL INTERFACE OVERVIEW

The ADL5201 DVGA has three digital gain control options:
parallel control interface, serial peripheral interface, and gain
up/down interface. The desired gain control option is selected via
two control pins, MODE0 and MODE1 (see Table 4 for the
truth table for the mode control pins). The gain code is in 6-bit
binary format. A voltage from 1.4 V to 3.3 V is required for a
logic high.

Two pins are common to all gain control options: PM and PWUP.
PM allows the user to choose operation in low power mode or
high performance mode. PWUP is the power-up pin. Physical
pins are shared among the three interfaces, resulting in as many
as three different functions per digital pin (see Table 3).

Table 4. Digital Control Interface Selection Truth Table

MODE1 MODE0 Interface

0 0 Parallel control
0 1 Serial peripheral (SPI)
1 0 Up/down
1 1 Up/down

To write to the SPI register, CS must be pulled low and 16 clock
pulses must be applied to SCLK. To read the SPI register value,
the R/W bit must be set high,

CS

must be pulled low, and the
part must be clocked. After the register is read out during the
next 16 clock cycles, the SPI is automatically placed in write mode.

Fast Attack

The fast attack feature, accessible via the SPI, allows the gain to
be reduced from its present gain setting by a predetermined step
size. Four different attenuation step sizes are available. The
truth table for fast attack is shown in Table 5.

Table 5. SPI 2-Bit Attenuation Step Size Truth Table

FA1 FA 0 Step Si z e (dB)

0 0 2
0 1 4
1 0 8
1 1 16

SPI fast attack mode is controlled by the FA pin. A logic high
on the FA pin results in an attenuation that is selected by
Bits[FA1:FA0] in the SPI register.

PARALLEL DIGITAL INTERFACE

The parallel digital interface uses six binary bits (Bits[A5:A0])
and a latch pin (LATCH). The Latch pin controls whether the
input data latch is transparent or latched. In transparent mode,
the gain changes as the input gain control bits change. In latched
mode, gain is determined by the latched gain setting and does
not change with the input gain control bits.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI uses three pins: SDIO, SCLK, and CS. The SPI data
register consists of two bytes: six gain control bits, two attenu­ation step size address bits, one read/write bit, and seven don’t
care bits. SDIO is the serial data input and output pin. The
SCLK pin is the serial clock, and

DATA

D0 D1 D2 D3 D4 D5 FA0 FA1

MSB LSB MSB

Figure 49. 16-Bit SPI Register

CS

is the channel select pin.

R/W DNC DNC DNC DNC DNC DNC DNC

DO NOT CARE
(7 BITS)

READ/WRITE

FAST ATT ACK AT TENUATION
STEP SIZ E ADDRESS

GAIN CONTRO L

09388-050

UP/DOWN INTERFACE

The GS1 and GS0 pins control the up/down gain step function.
Gain is increased by a clock pulse on the UPDN_CLK pin
(rising and falling edges) when the UPDN_DAT pin is high.
Gain is decreased by a clock pulse on the UPDN_CLK pin
when the UPDN_DAT pin is low.

UPDN_DAT

UPDN_CLK

Figure 50. Up/Down Timing

Reset is detected by a rising edge latching data having one polarity,
with the falling edge latching the opposite polarity. Reset results
in a minimum binary gain code of 111111.

The truth table for the gain step function is shown in Table 6.
The step size is selectable using the GS1 and GS0 pins. The gain
is limited by the top and bottom of the control range.

Table 6. Gain Step Size Control Truth Table

GS1 GS0 Step Size (dB)

0 0 0.5
0 1 1
1 0 2
1 1 4

DNUP RESET

09388-049

Rev. 0 | Page 15 of 28

ADL5201 Data Sheet

Truth Table

Table 7. Gain Code vs. Voltage Gain Lookup Table

6-Bit Binary
Gain Code

Voltage
Gain (dB)

6-Bit Binary
Gain Code

Voltage
Gain (dB)

000000 20 100000 4
000001 19.5 100001 3.5
000010 19 100010 3
000011 18.5 100011 2.5
000100 18 100100 2
000101 17.5 100101 1.5
000110 17 100110 1
000111 16.5 100111 0.5
001000 16 101000 0
001001 15.5 101001 −0.5
001010 15 101010 −1
001011 14.5 101011 −1.5
001100 14 101100 −2
001101 13.5 101101 −2.5
001110 13 101110 −3
001111 12.5 101111 −3.5
010000 12 110000 −4
010001 11.5 110001 −4.5
010010 11 110010 −5
010011 10.5 110011 −5.5
010100 10 110100 −6
010101 9.5 110101 −6.5
010110 9 110110 −7
010111 8.5 110111 −7.5
011000 8 111000 −8
011001 7.5 111001 −8.5
011010 7 111010 −9
011011 6.5 111011 −9.5
011100 6 111100 −10
011101 5.5 111101 −10.5
011110 5 111110 −11
011111 4.5 111111 −11.5

LOGIC TIMING

To write to the ADL5201, refer to the timing shown in Figure 51.
The write mode uses a 16-bit serial word on the SDIO pin. The
R/W bit of the word must be low to write Bits[D5:D0], which are
the binary weighted codes for the attenuation level (0 = minimum
attenuation, 63 = maximum attenuation). The FA0 and FA1 bits
control the fast attack step size. The DNC bits are nonfunctional,
do not care bits.

Reading the ADL5201 SPI register requires the following two steps:

1. Set the R/W bit high using a 16-bit word and the timing

shown in Figure 51. All other bits are ignored when the
R/W bit is high.

2. The SDIO is used as an output during the next sequence.

The written pattern is serially clocked out on SDIO using
16 clocks and the timing shown in Figure 51. The R/W bit
automatically returns low to the write state following the
read sequence.

t

PW

t

DH

09388-151

SCLK

CS

SDIO

t

SCLK

t

DS

tDSt

DH

DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0

Figure 51. SPI Interface Read/Write Mode Timing Diagram

Rev. 0 | Page 16 of 28

Data Sheet ADL5201

CIRCUIT DESCRIPTION

BASIC STRUCTURE

The ADL5201 is a differential variable gain amplifier (VGA)
consisting of a 150  digitally controlled passive attenuator
followed by a highly linear transconductance amplifier with
feedback.

ADL5201

VIN+

VIN–

ATTENUAT OR

LOGIC REF

DIGITAL INPUTS
PARALLEL, SPI,

FAST ATTACK

UP/DOWN

Figure 52. Simplified Schematic

g

AMP

m

VOUT+

VOUT–

09388-051

INPUT SYSTEM

The dc voltage level at the input of the amplifier is set by an
independent internal voltage reference circuit to approximately

1.6 V. The reference is not accessible and cannot be adjusted.
The amplifier can be powered down by pulling the PWUP pin

low. In power-down mode, the total current is reduced to 7 mA
(typical). The dc level at the input remains at approximately

1.6 V, regardless of the state of the PWUP pin.

OUTPUT AMPLIFIER

Gain of the output amplifier is set to be 22 dB when driving
a 150  load. The input and output resistance of this amplifier
is set to 150  in matched condition. If the load or the source
resistance is not equal to 150 , the following equations can be
used to determine the resulting gain and input/output resistances.

Voltage Gain = A

R

= (2000 + RL)/(1 + 0.09 × RL)

IN

S21 (Gain) = 2 × R

R

= (2000 + RS)/(1 + 0.09 × RS)

OUT

Note that the at maximum attenuation setting, R
the output amplifier, is the output resistance of the attenuator,
which is 150 Ω. However, at the minimum attenuation setting,
R

is the source resistance that is connected to the input of the part.

S

= 0.09 × (2000)//RL

V

/(RIN + RS) × AV

IN

, as seen by

S

The dc current to the outputs of each amplifier is supplied through
two external chokes. The inductance of the chokes and the
resistance of the load, in parallel with the output resistance of
the device, add a low frequency pole to the response. The para­sitic capacitance of the chokes adds to the output capacitance of the
part. This total capacitance, in parallel with the load and output
resistance, sets the high frequency pole of the device. Generally,
the larger the inductance of the choke, the higher its parasitic
capacitance. Therefore, this trade-off must be considered when
the value and type of the choke are selected. For an operation
frequency of 15 MHz to 700 MHz driving a 150  load, 1 H
chokes with an SRF of 160 MHz or higher are recommended
(such as the 0805LS-102XJBB from Coilcraft). If higher value
chokes are used, a 4 MHz zero, due to the internal ac-coupled
feedback, causes an increase in S21 of up to 6 dB at frequencies
below 4 MHz.

The supply current of the amplifier consists of about 35 mA
through the VPOS pin and 50 mA through the two chokes
combined. The latter increases with temperature at
approximately 2.5 mA per 10°C. The total choke current increases
to 75 mA for high performance mode. The amplifier has two
output pins for each polarity, and they are oriented in an
alternating fashion. When designing the board, care should be
taken to minimize the parasitic capacitance due to the routing
that connects the corresponding outputs together. To minimize
the parasitic capacitance, a good practice is to avoid any ground
or power plane under this routing region and under the chokes.

GAIN CONTROL

The gain can be adjusted using the parallel control interface, the
serial peripheral interface, or the gain up/down interface. In
general, the gain step size is 0.5 dB, but larger sizes can be
programmed using the various interfaces, as described in the
Digital Interface Overview section. The amplifier has a maximum
gain of +20 dB (Code 0) to −11.5 dB (Code 63).

The noise figure of the amplifier is approximately 7.5 dB at the
maximum gain setting, and it increases as the gain is reduced.
The increase in noise figure is equal to the reduction in gain.
The linearity of the part, measured at the output, is first-order
independent of the gain setting. From −4 dB to +20 dB gain,
the OIP3 is approximately 50 dBm into a 150  load at 200 MHz
(0 dBm per tone). At gain settings below −4 dB, the OIP3 drops
to approximately 40 dBm.

Rev. 0 | Page 17 of 28

ADL5201 Data Sheet

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 53 shows the basic connections for operating the ADL5201.
A voltage between 4.5 V and 5.5 V should be applied to the
VPOS pins. Each supply pin should be decoupled with at least
one low inductance, surface-mount ceramic capacitor of 0.1 F,
placed as close as possible to the device.

The outputs of the ADL5201 must be pulled up to the positive
supply with 1 µH RF chokes. The differential outputs are biased
to the positive supply and require ac coupling capacitors, preferably

0.1 µF. Similarly, the input pins are at bias voltages of about 1.6 V
above ground and should be ac-coupled, as well. The ac coupling
capacitors and the RF chokes are the principle limitations for
operation at low frequencies.

The digital pins (mode control pins, associated SPI and parallel
gain control pins, PM, and PWUP) operate on a voltage of 3.3 V.

To enable the ADL5201, the PWUP pin must be pulled high
(1.4 V ≤ PWUP ≤ 3.3 V). Taking PWUP low puts the ADL5201
in sleep mode, reducing current consumption to approximately
7 mA at ambient temperature.

ADC DRIVING

The ADL5201 is a highly linear, variable gain amplifier that
is optimized for ADC interfacing. The output IMDs and noise
floor remain constant throughout the 31.5 dB gain range. This
is a valuable feature in a variable gain receiver, where it is
desirable to maintain a constant instantaneous dynamic range
as the receiver range is modified. The output noise is 15 nV/√Hz,
which is compatible with 14- or 16-bit ADCs. The two-tone
IMDs are usually greater than −100 dB for −1 dBm into 150 Ω
or 2 V p-p output. The 150 Ω output impedance makes the task
of designing a filter for the high input impedance ADCs more
straightforward.

+V

R

L

POS

10µF

BALANCED

LOAD

09388-052

R

S

BALANCED

SOURCE

GAIN MODE INTERFACE

AC

2

R

S

2

0.1µF

0.1µF

MODE0

0.1µF 0.1µF 0.1µF 0. 1µF

0.1µF

24 23 22 21 20 19

S

S

VPOS

VPO

VPO

GND

1

VIN+

2

VIN–

3

ADL5201

GND

4

MODE1

5

MODE0

6

SDIO/A5

GAIN CONT ROL INTERFACE

GS1/CS/A3

SCLK/A4

POS
V

/A2

GS0/FA

3.3V 3.3V

PM

N_CLK/A1

UPD

127891011

UP

PW

VOUT–

VOUT+

VOU

VOUT+

LATCH

N_DAT/A0

UPD

VPOS

1µH

18

17

16

T–

15

14

13

0.1µF

1µH

0.1µF

Figure 53. Basic Connections

Rev. 0 | Page 18 of 28

Data Sheet ADL5201

A

V

0.1µF

1:3

50Ω

C

0.1µF

ADL5201

DIGITAL

INTERFACE

5

5V

5V

Figure 54. Wideband ADC Interfacing Example Featuring the ADL5201 and the AD9467

Figure 54 shows the ADL5201 driving a two-pole, 100 MHz, low­pass filter into the AD9467. The AD9467 is a 16-bit, 200 MSPS
to 250 MSPS ADC with a buffered wideband input that presents
a 530 Ω differential input impedance and requires a 2 V or 2.5 V
input swing to reach full scale. For optimum performance, the

ADL5201 should be driven differentially, using an impedance

transformer or input balun.

0

–1

–2

–3

–4

–5

–6

–7

–8

INSERTION LOSS (dB)

–9

–10

–11

–12

0 20 40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

09388-054

Figure 55. Measured Frequency Response of the Wideband

ADC Interface Shown in Figure 54

Figure 54 uses a 1:3 impedance transformer to provide the
150 Ω input impedance of the ADL5201 with a matched input.
The outputs of the ADL5201 are biased through the two 1 µH
inductors, and the two 0.1 F capacitors on the outputs decouple
the 5 V inductor voltage from the input common-mode voltage
of the AD9467. The two 75 Ω resistors provide the 150 Ω load to
the ADL5201, whose gain is load dependent. The 47 nH induc­tors and 14 pF capacitor constitute the (100 MHz − 1 dB) low-pass
filter. The two 33 Ω isolation resistors suppress any switching
currents from the ADC input sample-and-hold circuitry. The
circuit depicted in Figure 54 provides variable gain, isolation,
filtering, and source matching for the AD9467. By using this
circuit with the ADL5201 in a gain of 20 dB (maximum gain),
an SNR of 68 dB and an SFDR performance of 88 dBc are
achieved at 100 MHz, as shown in Figure 56.

1µH

1µH

V

0.1µF

0.1µF

75Ω

75Ω

47nH

V

REF

47nH

–15

–30

–45

–60

–75

–90

AMPLITUDE (dBFS)

–105

–120

–135

–150

33Ω

14pF

33Ω

SNR = 68dB

0

SFDR = 88dBc
NOISE FLOOR = –114dBFS
FUND = –1.05dBF S
SECOND = –94.7dBc
THIRD = –88.75dBc

5

0 15 30 45 60 75 90 105 120

REF

AD9467

3

+

2

FREQUENCY (MHz)

09388-053

Figure 56. Measured Single-Tone Performance of the Circuit Shown

in Figure 54 for a 100 MHz Input Signal

The two-tone 100 MHz IMDs of two 1 V p-p signals have
an SFDR of greater than 91 dBc, as shown in Figure 57.

FUND1 = –6.682dBFS

0

FUND2 = –7.096dBFS
2f1 – f2 = –93.2dBF S

–15

2f2 – f1 = –92.58dBc
NOISE FLOOR = –115. 3dBFS

–30

–45

–60

–75

–90

AMPLITUDE (dBFS)

f2 – f1

–105

–120

–135

–150

0 15 30 45 60 75 90 105 120

Figure 57. Measured Two-Tone Performance of the

Circuit Shown in Figure 54 for a 100 MHz Input Signal

2f1 + f2

2f2 + f1

f1 + f2

FREQUE NCY (MHz)

4

6

09388-055

2f1 – f22f2 – f1

+

09388-056

Rev. 0 | Page 19 of 28

ADL5201 Data Sheet

A

V

An alternative narrow-band approach is presented in Figure 58.
By designing a narrow band-pass antialiasing filter between the

ADL5201 and the target ADC, the output noise of the ADL5201

outside the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves by several decibels (dB) when a reasonable order
antialiasing filter is included. In this example, a low loss 1:3
input transformer is used to match the 150  balanced input
of the ADL5201 to a 50  unbalanced source, resulting in
minimum insertion loss at the input.

Figure 58 shows the ADL5201 optimized for driving some of
the popular unbuffered Analog Devices ADCs: the AD9246,

AD9640, and AD6655. Table 8 includes antialiasing filter

component recommendations for popular IF sampling center
frequencies. Inductor L5 works in parallel with the on-chip
ADC input capacitance and a portion of the capacitance
presented by C4 to form a resonant tank circuit. The resonant tank
helps to ensure that the ADC input looks like a real resistance at

5

the target center frequency. In addition, the L6 inductor shorts
the ADC inputs at dc, which introduces a zero into the transfer
function. The ac coupling capacitors and the bias chokes introduce
additional zeros into the transfer function. The final overall fre­quency response takes on a band-pass characteristic, helping to
reject noise outside of the intended Nyquist zone. Table 8 provides
initial suggestions for prototyping purposes. Some empirical
optimization may be needed to help compensate for actual PCB
parasitics.

LAYOUT CONSIDERATIONS

Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
To minimize the parasitic capacitance, a good practice is to avoid
any ground or power planes under this routing region and under
the chokes.

50Ω

C

5V

1nF

1:3

ADL5201

1nF

DIGITAL

INTERFACE

Figure 58. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications

1µH

1nF

1nF

1µH

5V

L1 L3 L5

C2

L1 L3 L5

75Ω

CMLC4

75Ω

L6

AD9246
AD9640
AD6655

09388-057

Table 8. Interface Filter Recommendations for Various IF Sampling Center Frequencies

Center Frequency
(MHz)

1 dB Bandwidth
(MHz)

L1 (nH) C2 (pF) L3 (nH) C4 (pF) L5 (nH) L6 (nH)

96 27 68 15 220 15 68 150
140 31 47 11 150 11 47 82
170 25 39 10 120 10 47

51

211 40 30 7 100 7.5 30 43

Rev. 0 | Page 20 of 28

Data Sheet ADL5201

EVALUATION BOARD

The ADL5201 evaluation board is available with software to
program the variable gain control. It is a 4-layer board with a split
ground plane for analog and digital sections. Special care is
taken to place the power decoupling capacitors close to the
device pins. The board is designed for easy single-ended
(through a Mini-Circuits TC3-1T+ RF transformer) or
differential configuration for each channel.

EVALUATION BOARD CONTROL SOFTWARE

The ADL5201 evaluation board is configured with a USB-friendly
interface to program the gain of the ADL5201. The software
graphical user interface (see Figure 59) lets users select a particular
gain mode and gain level to write to the device. The GUI also
allows users to read back data from the SDIO pin, showing the
currently programmed gain setting. The software setup files can be
downloaded from the ADL5201 product page at www.analog.com.

09388-058

Figure 59. Evaluation Board Control Software

Rev. 0 | Page 21 of 28

ADL5201 Data Sheet

SCHEMATICS AND ARTWORK

09388-059

AGND

A0

AGND

543 2

1

3

2

0Ω

R47

VPOS

R29

TBD0402

R28

TBD0402

0Ω

0.1µF

12117

VOUT_NEG

UPDN_CLK_A1

UPDN_DAT_A0

MODE1

MODE0

5

6

13

0

R13

AGND

0.1µF

3

TCM3-1T+

4

R3

0Ω

AGND

TBD0402

C12

0.1µF

8

9

10

SCLK_A4

GS0_FA_A2

GS1_CS_N_A3

PM

PWUP

LATCH

19

20

TBD0402

R11

REMOVE PLANE UNDER TRACES

R4

TBD0402

AGND

1

J1

R35

1kΩ

R34

DNI

3.3V

DNI

AGND

AGND

UPDN_DAT/A0

SDIO_A5

PAD

PAD

4

GND_ZAP
GND

1

AGND

PA5

R2R1

1kΩ

3.3V

1kΩ

5432

AGND

MODE1

50Ω TRACES

4

2

3

TCM3-1T+

R25

C11

L1

1µH

0Ω

R20

0Ω

R19

16

17

15

14

VOUT_POS

VOUT_POS

VOUT_NEG

VPOS_IG
VPOS_ID

VIN_NEG

VIN_POS

2

3

75Ω TRACES

0

TBD0402

R10

C1

T2
1

2

6

5432

1

MOLEX22-03-2031

C13

1

1

3

2

A1

AGND

1kΩ

PB0

R36

1kΩ

TBD0402

R30

AGND

MODE1

2

TBD0402

DNI

AGND

3.3V

AGND

DNI

UPDN_CLK/A1

MODE0

PB1

1kΩ

R8R7

PA6

1kΩ

R65R

3.3V

1kΩ

3.3V

LATCH

1kΩ

1

3

2

AGND

MODE0

3

MOLEX22-03-2031

1

3

2

MOLEX22-03-2031

1kΩ

R37

TBD0402

C14

R31

TBD0402

LATCH

PWUP

1

3

2

AGND

MOLEX22-03-2031

A2

AGND

PA4

R42

1kΩ

R38

3.3V
DNI

C15

AGND

AGND

DNI

R32

GSO/FA/A2

PM

PWUP

3.3V

1kΩ

R14

1

2

PM

3.3V
AGND

1

3

2

AGND

MOLEX22-03-2031

MOLEX22-03-2031

1

PWRUP

1kΩ

TBD0402

1

3

2

MOLEX22-03-2031

A3

AGND

PA3

AGND

AGND

TBD0402

PA7

1kΩ

R15

AGND

3

MOLEX22-03-2031JOHNSON142-0701-851

AGND

5432

AGND

1kΩ

R46

R43

3.3V

PA2

1kΩ

TBD0402

DNI

C16

AGND

AGND

DNI

R33

A4

TBD0402

1

3

2

AGND

MOLEX22-03-2031

1kΩ

R23

1kΩ

R22

3.3V

GS1/CS /A3

PA1

DNI

TBD0402

C8

AGND

AGND

DNI

R21

TBD0402

MOLEX22-03-2031

SCLK/A4

A5

1

3

2

AGND

PA0

1kΩ

R18

1kΩ

R17

DNI

C6

TBD0402

AGND

DNI

SIDO/A5

0.1µF

YEL

3.3V
1

C17

3.3V

AGND

R16

TBD0402

AGND

Figure 60. Evaluation Board Schematic

Rev. 0 | Page 22 of 28

VXB

VXA

VPOS

543 2

OUTB–

AGND

VPOS

AGND

0

R24

REDRED
1

1

RED

VPOS

1

0.1µF

C7 C9

0

0.1µF

R51

VPOS

AGND

0.1µF

C4 C5

0.1µF 0. 1µF

C3

C2

10µF

AGND

NP

BLK

AGND

1

AGND

6

1

T1

TBD0402

R27

0Ω

R26

C10

0.1µF

1µH

L2

U1

24
23

VPOS

18
22
21

AGND

R12

TBD0402

R9

INB-

Data Sheet ADL5201

09388-060

Figure 61. Logic Schematic

Figure 62. Top Layer

09388-061

Figure 63. Bottom Layer

09388-062

Rev. 0 | Page 23 of 28

ADL5201 Data Sheet

EVALUATION BOARD CONFIGURATION OPTIONS

Configuration Options for the Main Section

Table 9. Bill of Materials for Main Section

Components Function Default Conditions

C2 to C5, C7, C9, C17

U1 Device under test. Installed
INB−

T2
J1
C1
R3, R4, R9 to R13

T1
C10 to C12
L1, L2
R19, R20, R24 to R28,
R47, R48, R51
OUTB+, OUTB−

PWUP, PWRUP

A0 to A5
LATCH
PM
MODE0, MODE1
R1, R2, R5 to R8,
R14 to R18, R21 to R23,
R30 to R38, R42, R43, R46
C6, C8, C13 to C16

Power supply decoupling. Nominal supply decoupling consists of
a 0.1 μF capacitor to ground.

Input interface. INB− is the RF input. T2 is a 3:1 impedance ratio balun
used to transform a single ended 50 Ω signal into a 150 Ω balanced
differential signal. The input can be configured for a differential by
removing R3 and installing a 0 Ω jumper at R4.
C1 provides dc blocking. R12 and R13 are placeholders and can be
replaced with blocking capacitors when driving the ADL5201 from
a fully differential source.
R3 grounds one side of the differential drive interface for single-ended
applications. R9, R10, and R11 are provided for generic placement of
matching components.

Output interface. T1 is a 3:1 impedance ratio balun used to transform
a 150 Ω balanced differential signal to a 50 Ω singled-end signal.

C10 and C11 are dc blocks.
L1 and L2 provide dc bias to the open-collector output.
R24 to R28 are provided for the generic placement of matching
components. R47 grounds one side of the differential output interface

for single-ended applications.

Power-up interface. The ADL5201 is powered up by applying a logic
high (1.4 V ≤ PWUPA/B ≤ 3.3 V) to PWUP from an external source or by
installing a shunt between Pin 1 and Pin 2 of the 3-pin header, PWUP.

Gain control interface. All of the gain control functions are fully
controlled via the USB microcontroller using the supplied software.
Three-pin headers allow for manual operation of the gain control, if
desired.
R1, R2, R5 to R8, R14, R15, R17, R18, R22, R23, R34 to R38, R42, R43, and
R46 isolate the digital control pins from the microcontroller and
provide current limiting.
The R16, R21, and R30 to R33 resistors and the C6, C8, and C13 to C16
capacitors allow for the generic placement of filter components.

C2 = 10 μF (Size C7343)
C3 to C5, C7, C9, C17 = 0.1 μF (Size 0603)

T2 = TC3-1T+ (Mini-Circuits)
C1 = 0.1 μF (Size 0402)
R3, R12, R13 = 0 Ω (Size 0402)
R4, R9 to R11 = open
INB− (SMA connector) installed
J1 (SMA connector) installed

T1 = TC3-1T+ (Mini-Circuits)
C10 to C12 = 0.1 μF (Size 0402)
R19, R20, R24 to R26, R47, R51 = 0 Ω
(Size 0402)
R27, R28, R48 = open
L1, L2 = 1 μH (Size 0805)
OUTB+ (SMA connector) installed
OUTB− (SMA connector) installed

PWUP (3-pin header) installed
PWRUP (SMA connector) installed

A0 to A5 (3-pin header) installed
LATCH (3-pin header) installed
MODE0 (3-pin header) installed
MODE1 (3-pin header) installed
PM (3-pin header) installed
R1, R2, R5 to R8, R14, R15, R17, R18,
R22, R23, R34 to R38, R42, R43, R46 =
1 kΩ (Size 0402)
R16, R21, R30 to R33 = open
C6, C8, C13 to C16 = open

Rev. 0 | Page 24 of 28

Data Sheet ADL5201

Configuration Options for the USB Section

Table 10. Bill of Materials for USB Section

Components Default Conditions

C31, C62 22 pF (Size 0603)
C49 1000 pF (Size 0603)
C28 to C30, C53 to C55, C57 to C61 0.1 μF (Size 0402)
C47, C50 1 μF (Size 0402)
C52, C56 10 pF (Size 0402)
D6 Green LED (Panasonic LNJ308G8TRA)
J16 USB SMT connector (Hirose Electric UX60A-MB-5ST 240-0003-4)
R39, R49, R50 2 kΩ (Size 0603)
R41 78.7 kΩ (Size 0603)
R40 140 kΩ (Size 0603)
R44, R45 100 kΩ (Size 0603)
R58 0 Ω (Size 0603)
U6 USB microcontroller (Cypress CY7C68013A-56LFXC)
U7 64 kbit EEPROM (Microchip 24LC64-I/SN)
U5 Low dropout regulator (Analog Devices ADP3334ACPZ)
Y2 24 MHz crystal oscillator (AEL Crystals X24M000000S244)

Rev. 0 | Page 25 of 28

ADL5201 Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

0.30

0.25

0.18

19

18

13

12

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

1

P

N

I

D

C

I

A

N

I

24

1

EXPOSED

PAD

7

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

2.65

2.50 SQ

2.45

6

0.25 MIN

R

O

T

COMPLIANTTOJEDEC STANDARDS MO-220-WGGD.

112108-A

Figure 64. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-24-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADL5201ACPZ-R7 −40°C to +85°C 24 Lead LFCSP_WQ, 7” Tape and Reel CP-24-7
ADL5201-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 26 of 28

Data Sheet ADL5201

NOTES

Rev. 0 | Page 27 of 28

ADL5201 Data Sheet

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09388-0-10/11(0)

Rev. 0 | Page 28 of 28