Datasheet ADG888 Datasheet (ANALOG DEVICES)

0.4 Ω CMOS, Dual DPDT Switch

S2BS2A

S

S1A

S4BS4AD4S

S3A

in WLCSP/LFCSP/TSSOP Packages

ADG888

FEATURES FUNCTIONAL BLOCK DIAGRAM

1.8 V to 5.5 V operation
Ultralow on resistance

0.4 Ω typical

0.6 Ω maximum at 5 V supply

Excellent audio performance, ultralow distortion

0.07 Ω typical

0.14 Ω maximum R

flatness

ON

High current carrying capability

400 mA continuous

600 mA peak current at 5 V
Automotive temperature range: −40°C to +125°C
Rail-to-rail switching operation
Typical power consumption (<0.1 μW)

IN1

1B

3B

ADG888

D1

D2

D3

APPLICATIONS

Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
Data switching

IN2

SWITCHES SHOWN
FOR A LOGIC 1 INPUT

Figure 1.

05432-001

GENERAL DESCRIPTION

The ADG888 is a low voltage, dual DPDT (double pole double
throw) CMOS device optimized for high performance audio
switching. With its low power and small physical size, it is ideal
for portable devices.

This device offers ultralow on resistance of less than 0.8 Ω over
the full temperature range making it an ideal solution for
applications requiring minimal distortion through the switch.
The ADG888 also has the capability of carrying large amounts
of current, typically 400 mA at 5 V operation.

When on, each switch conducts equally well in both directions
and has an input signal range that extends to the supplies. The
ADG888 exhibits break-before-make switching action.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADG888 is available in a 4 × 4 bump, 2.0 mm × 2.0 mm
WLCSP; a 4 mm × 4 mm, 16-lead LFCSP; and a 16-lead TSSOP.
These packages make the ADG888 the ideal solution for space­constrained applications.

PRODUCT HIGHLIGHTS

1. <0.6 Ω over full temperature range of −40°C to +125°C.

2. High current handling capability (400 mA continuous
current at 5 V).

3. Low THD + N (0.008% typical).

4. Tiny 2 mm × 2 mm, 16-ball WLCSP package, and 16-lead
LFCSP and TSSOP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

ADG888

TABLE OF CONTENTS

Features.............................................................................................. 1

Pin Configuration and Function Descriptions..............................6

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

REVISION HISTORY

7/05—Revision 0: Initial Version

Truth Table .....................................................................................6

Typical Performance Characteristics..............................................7

Test Circuits........................................................................................9

Terminology.................................................................................... 11

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

ADG888

SPECIFICATIONS

to
+85°C

1

to
+125°C Unit Test Conditions/Comments

or V

INL

Adjacent channel; R
f = 100 kHz; see

Adjacent switch; R

Figure 23

see

INH

= 50 Ω, CL = 5 pF,

L

Figure 25

= 50 Ω, CL = 5 pF, f = 100 kHz;

L

VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 1.

−40°C −40°C

Parameter +25°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.4 Ω typ VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA;

0.48 0.55 0.6 Ω max See Figure 16
On Resistance Match Between 0.04 Ω typ VDD = 4.2 V, VS = 2.2 V, IDS = 100 mA

Channels (∆RON) 0.06 0.07 0.075 Ω max

On Resistance Flatness (R

) 0.07 Ω typ VDD = 4.2 V, VS = 0 V to VDD,

FLAT (ON)

0.11 0.13 0.14 Ω max IDS = 100 mA
LEAKAGE CURRENTS VDD = 5.5 V

Source Off Leakage IS (OFF) ±0.2 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 17
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 1 V or 4.5 V; see Figure 18

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current

I

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max
CIN, Digital Input Capacitance 2 pF typ

DYNAMIC CHARACTERISTICS

2

tON 22 ns typ RL = 50 Ω, CL = 35 pF
30 33 35 ns max VS = 3 V/0 V; see Figure 19
t

13 ns typ RL = 50 Ω, CL = 35 pF

OFF

17 18 19 ns max VS = 3 V/0 V; see Figure 19
Break-Before-Make Time Delay (t

) 9 ns typ RL = 50 Ω, CL = 35 pF

BBM

5 ns min VS1 = VS2 = 3 V; see Figure 20
Charge Injection 70 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
Channel-to-Channel Crosstalk −99 dB typ

−67 dB typ

Total Harmonic Distortion (THD + N) 0.008 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3 V p-p
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 24

−3 dB Bandwidth 29 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24
CS (OFF) 58 pF typ
CD, CS (ON) 110 pF typ

POWER REQUIREMENTS VDD = 5.5 V

IDD 0.003 μA typ Digital inputs = 0 V or 5.5 V
1 4 μA max

1

Temperature range, Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

Rev. 0 | Page 3 of 16

ADG888

VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted1.

Table 2.

−40°C −40°C
Parameter +25°C to +85°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.5 Ω typ VDD = 2.7 V, VS = 0 V to VDD,

0.7 0.75 0.8 Ω max IS = 100 mA; see Figure 16
On Resistance Match Between 0.045 Ω typ VDD = 2.7 V, VS = 1 V,

Channels (∆RON) 0.065 0.07 0.075 Ω max IS = 100 mA

On Resistance Flatness (R

0.25 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 3.6 V

Source Off Leakage IS (OFF) ±0.2 nA typ VS = 1 V/2.6 V, VD = 2.6 V/1 V; see Figure 17
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 1 V or 2.6 V; see Figure 18

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

0.8 V max

INL

Input Current

I

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max
CIN, Digital Input Capacitance 2 pF typ

DYNAMIC CHARACTERISTICS

tON 28 ns typ RL = 50 Ω, CL = 35 pF; see Figure 19
43 47 50 ns max VS = 1.5 V/0 V
t

13 ns typ RL = 50 Ω, CL = 35 pF; see Figure 19

OFF

20 21 22 ns max VS = 1.5 V/0 V
Break-Before-Make Time Delay (t
5 ns min VS1 = VS2 = 1.5 V; see Figure 20
Charge Injection 50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 21
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
Channel-to-Channel Crosstalk −99 dB typ

−67 dB typ

Total Harmonic Distortion (THD + N) 0.01 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1 V p-p
Insertion Loss −0.04 dB typ RL = 50 Ω, CL = 5 pF; see Figure 24
–3 dB Bandwidth 29 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 24
CS (OFF) 60 pF typ
CD, CS (ON) 115 pF typ

POWER REQUIREMENTS VDD = 3.6 V

IDD 0.003 μA typ Digital inputs = 0 V or 3.6 V

1 2 μA max

1

Temperature range, Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

) 0.16 Ω typ VDD = 2.7 V, VS = 0 V to VDD,

FLAT (ON)

1.3 V min

or V

INL

INH

2

) 14 ns typ RL = 50 Ω, CL = 35 pF

BBM

Adjacent channel; R
see

Figure 25

Adjacent switch; R

Figure 23

see

= 50 V, CL = 5 pF, f = 100 kHz;

L

= 50 Ω, CL = 5 pF, f = 100 kHz;

L

Rev. 0 | Page 4 of 16

ADG888

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 3.

Parameter Rating

VDD to GND −0.3 V to +6 V
Analog Inputs1, Digital Inputs1

Peak Current, S or D

Continuous Current, S or D 400 mA
Operating Temperature Range

Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP Package

θJA Thermal Impedance

(4-Layer Board)

θJC Thermal Impedance 27.6°C/W
16-Lead WLCSP Package

θJA Thermal Impedance

(4-Layer Board)

16-Lead LFCSP Package

θJA Thermal Impedance

(4-Layer Board)

IR Reflow, Peak Temperature <20 sec 235°C

1

Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to

the maximum ratings given.

−0.3 V to V
10 mA, whichever
occurs first

600 mA (pulsed at 1 ms,

10% duty cycle max)

112°C/W

130°C/W

30.4°C/W

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating may be applied at any one
time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16

ADG888

A

A

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BUMP A1
INDICATOR

A

BCD

D4

1

S4B

2

S3B

3

D3

4

(BUMP SIDE DOWN)

S1A

S4A

V

GND

IN2

IN1

S2A

S3A

TOP VIEW

Not to Scale

D1

DD

S1B

S2B

D2

05432-002

1D1
2S1B
3S2B
4D2

Figure 3. 16-Lead LFCSP_VQ (CP-16-4)

TOP VIEW

(Solder Bumps on Opposite Side)

Figure 2. 16-Lead WLCSP (CB-16)

Table 4. Pin Function Descriptions

Bump No. WL CSP Pin No. LFCSP_VQ Pin No. TSSOP Mnemonic Description

2c 15 1 VDD Most Positive Power Supply Potential.
2b 14 16 GND Ground (0 V) Reference.
1b, 1c, 2a, 2d, 3a, 3d, 4b, 4c 2, 3, 5, 8, 10, 11, 13, 16 2, 4, 5, 7, 10, 12, 13, 15 S Source Terminal. May be an input or output.
1a, 1d, 4a, 4d 1, 4, 9, 12 3, 6, 11, 14 D Drain Terminal. May be an input or output.
3b, 3c 6, 7 8, 9 IN Logic Control Input.

DD

S1A

V

GN
14

16

15

PIN 1
INDICATOR

ADG888

TOP VIEW

(Not to Scale)

7

5

6

IN1

IN2

S2A

1

S4A
13

12 D4
11 S4B
10 S3B
9D3

8

S3A

05432-003

V

DD

2

S1

3

D1
S1B
S2B

D2
S2

IN1 IN2

ADG888

TOP VIEW

4

(Not to Scale)

5

6

7

8

16

GND

15

S4A

14

D4

13

S4B

12

S3B

11

D3

10

S3A

9

05432-004

Figure 4. 16-Lead TSSOP (RU-16)

TRUTH TABLE

Table 5.

Logic (IN1/IN2) Switch 1A/2A/3A/4A Switch 1B/2B/3B/4B

0 Off On
1 On Off

Rev. 0 | Page 6 of 16

ADG888

TYPICAL PERFORMANCE CHARACTERISTICS

0.40

0.35

0.30

0.25

(Ω)

0.20

ON

R

0.15

0.10

0.05

0

05

Figure 5. On Resistance vs. V

0.6

0.5

0.4

(Ω)

0.3

ON

R

0.2

0.1

0

0

Figure 6. On Resistance vs. V

VDD = 4.2V

V

= 4.5V

DD

= 5V

V

V

DD

1

VDD = 2.7V

0.5 1.0 1.5 3.5

2

VDD = 3.3V

DD

= 5.5V

34

VS,VD(V)

(VS) VDD = 4.2 V to 5.5 V

D

VDD = 3V

VDD = 3.6V

2.0 2.5 3.0

VS,VD(V)

(VS) VDD = 2.7 V to 3.6 V

D

TA = 25°C

= 100mA

I

DS

TA = 25°C

= 100mA

I

DS

05432-005

05432-006

0.7

0.6

0.5

0.4

(Ω)

ON

R

0.3

0.2

0.1

0

0

TA=+125°C

TA=+25°C

0.5 1.0 1.5 2.0 2.5

Figure 8. On Resistance vs. V

Tem per atu re, V

400

350

300

250

(pC)

200

INJ

Q

150

100

50

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD = 3V

TA=–40°C

VS,VD (V)

DD

V

(V)

D

TA=+85°C

(VS) for Different

D

= 3 V

VDD = 5V

Figure 9. Charge Injection vs. Source Voltage

VDD = 3V

= 100mA

I

DS

TA = 25°C

3.0

05432-008

05432-009

0.45

0.40

0.35

0.30

0.25

(Ω)

ON

0.20

R

0.15

0.10

0.05

0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 7. On Resistance vs. V

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

VS,VD (V)

Tem per atu re, V

(VS) for Different

D

= 5 V

DD

VDD = 5V

= 100mA

I

DS

05432-007

5.0

Rev. 0 | Page 7 of 16

45

VDD = 3V; SxA CHANNELS
VDD = 3V; SxB CHANNELS

40

VDD = 5V; SxA CHANNELS

35

VDD = 5V; SxB CHANNELS

30

25

t

ON

20

TIME (ns)

15

t

OFF

10

5

0

–40 –20 0 20 40 60 80 100 120

Figure 10. tON/t

VDD = 3V, 5V; SxB CHANNELS
V

= 3V, 5V; SxA CHANNELS

DD

TEMPERATURE (°C)

Times vs. Temperature

OFF

05432-010

ADG888

0

–1

–2

–3

–4

–5

–6

ON RESPONSE (dB)

–7

–8

TA = 25°C

–9

V

–10

10k 100k 1M 10M 100M

= 3V, 4.2V, 5V

DD

FREQUENCY (Hz)

Figure 11. Bandwidth

05432-011

0.025
VDD = 3V, VS = 2V p-p

0.020
VDD = 5V, VS = 4V p-p

0.015

VDD = 3V, VS = 1V p-p

0.010

THD + N (%)

VDD = 5V, VS = 3V p-p
VDD = 3V, VS = 0.5V p-p

0.005

VDD = 5V, VS = 1V p-p

0

0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k

FREQUENCY (Hz)

Figure 14. Total Harmonic Distortion + Noise (THD + N)

TA = 25°C

05432-014

0

TA=25°C
V

= 3V, 4.2V, 5V

DD

–20

–40

–60

–80

ATTENUATION (dB)

–100

–120

100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 12. Off Isolation vs. Frequency

0

TA = 25°C

= 3V, 4.2V, 5V

V

DD

–20

–40

–60

–80

ATTENUATION (dB)

–100

–120

ADJACENT CHANNELS (S1A-S2A)

ADJACENT SWITCHES (S1A-S1B)

S1A-S4A

05432-012

20

TA=25°C

= 3V, 4.2V, 5V

V

DD

NO DECOUPLING ON SUPPLIES

0

–20

–40

–60

ATTENUATION (dB)

–80

–100

100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 15. AC PSRR

05432-023

–140

100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

05432-013

Figure 13. Cross talk vs. Frequency

Rev. 0 | Page 8 of 16

ADG888

V

V

TEST CIRCUITS

I

DS

V1

SD

V

S

RON = V1/I

Figure 16. On Resistance

DS

05432-015

IS (OFF) ID (OFF)

SD

A A

V

S

Figure 17. Off Leakage Figure 18. On Leakage

V

D

05432-016

NC

SD

ID (ON)

A

V

D

05432-017

V

DD

0.1μF

V

DD

S1B

V

S

S1A

IN

GND

D1

R

L

50Ω

V

C

L

35pF

OUT

V

IN

V

OUT

Figure 19. Switching Times, tON, t

50% 50%

90% 90%

t

ON

OFF

t

OFF

05432-018

V

DD

0.1μF

V

DD

S1B

S

S1A

IN

GND

D1

R

L

50Ω

C

L

35pF

V

OUT

0V

V

IN

V

OUT

Figure 20. Break-Before-Make Time Delay, t

50% 50%

80%

t

BBM

BBM

80%

t

BBM

05432-019

V

DD

SW ON

V

OUT

IN

V

OUT

ΔV

OUT

S1B

D1

S

IN

S1A

GND

NC
V

1nF

Figure 21. Charge Injection

Q

INJ

SW OFF

= CL ×ΔV

OUT

05432-020

Rev. 0 | Page 9 of 16

ADG888

0.1μF

V

DD

0.1μF

V

DD

V

DD

NC

S1B

OFF ISOLATION = 20 log

GND

S1A

D

50Ω

V

OUT

VS

Figure 22. Off Isolation

0.1μF

V

OUT

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

V

R
50Ω

50Ω

S

L

S1A

S1B

Figure 23. Channel-to-Channel Crosstalk (S1A to S1B)

GND

V

V

V

OUT

VS

DD

DD

NETWORK
ANALYZER

50Ω

V

V

OUT

R

L

50Ω

D

V

DD

GND

S1AS1B

D

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

S

05432-021

INSERTION LOSS = 20 log

NETWORK
ANALYZER

50Ω

V

V

OUT

R

L

50Ω

S

05432-022

Figure 24. Bandwidth

NETWORK
ANALYZER

V

R
50Ω

L

05432-024

OUT

50Ω

NC

50Ω
V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

NC

S2A
S2B

S1A
S1B

D2

D1

V

OUT

VS

NC

50Ω

05432-025

Figure 25. Channel-to-Channel Crosstalk (S1A to S2A)

Rev. 0 | Page 10 of 16

ADG888

TERMINOLOGY

I

DD

Positive supply current.

V

(VS)

D

Analog voltage on Terminal D and Terminal S.

RON

Ohmic resistance between Terminal D and Terminal S.

R

FLAT (ON)

Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.

RON

Δ

On resistance match between any two channels.

(OFF)

I

S

Source leakage current with the switch off.

I

, IS (ON)

D

Channel leakage current with the switch on.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

(I

INL

INH

)

I

Input current of the digital input.

(OFF)

C

S

Off switch source capacitance. Measured with reference to
ground.

, CS (ON)

C

D

On switch capacitance. Measured with reference to ground.

C

IN

Digital input capacitance.

t

ON

Delay time between the 50% and the 90% points of the digital
input and switch on condition.

t

OFF

Delay time between the 50% and the 90% points of the digital
input and switch off condition.

t

BBM

On or off time measured between the 80% points of both
switches when switching from one to another.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. This is
specified for two conditions:

Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to
S4A, or S3B to S4B.

Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to
S3B, or S4A to S4B.

−3 dB Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitudes plus signal noise to the
fundamental.

Rev. 0 | Page 11 of 16

ADG888

R

OUTLINE DIMENSIONS

BUMP 1
IDENTIFIER

TOP VIEW

(BUMP SIDE DOWN)

0.65

0.59

0.53
SEATING

PLANE

0.36

0.32

2.06

2.00 SQ

1.94

0.50
BUMP
PITCH

0.28

0.24

0.20

0.28

0.11

0.09

0.07

Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16)

Dimensions shown in millimeters

5.10

5.00

4.90

BOTTOM VIEW

(BUMP SIDE UP)

ABCD

1

2

3

4

PIN 1

INDICATO

1.00

0.85

0.80

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

12° MAX

SEATING
PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

16

1

4

5

1.95 BSC

0.75

0.60

0.45

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

Rev. 0 | Page 12 of 16

ADG888

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADG888YRUZ
ADG888YRUZ-REEL
ADG888YRUZ-REEL72−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADG888YCPZ-REEL
ADG888YCPZ-REEL7
ADG888YCBZ-REEL
ADG888YCBZ-REEL72−40°C to +125°C 16-Ball Wafer Level Chip Scale Package (WLCSP) CB-16 S0D

1

Branding on these packages is limited to three characters due to space constraints.

2

Z = Pb-free part.

2

−40°C to +125°C 16 Lead Thin Shrink Small Outline Package (TSSOP) RU-16

2

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

2

−40°C to +125°C 16- Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 S0D

2

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 S0D

2

−40°C to +125°C 16-Ball Wafer Level Chip Scale Package (WLCSP) CB-16 S0D

1

Rev. 0 | Page 13 of 16

ADG888

NOTES

Rev. 0 | Page 14 of 16

ADG888

NOTES

Rev. 0 | Page 15 of 16

ADG888

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05432-0-7/05(0)

Rev. 0 | Page 16 of 16