600 mA peak current at 5 V supply
Rail-to-rail switching operation
Typical power consumption (<0.1 µW)
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communications systems
GENERAL DESCRIPTION
The ADG884 is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of less than
0.4 Ω over the full temperature range, making the part an ideal
solution for applications that require minimal distortion
through the switch. The ADG884 also has the capability of
carrying large amounts of current, typically 600 mA at 5 V
operation.
The ADG884 is available in a 10 bump, 2.0 mm × 1.50 mm
WLCSP package, a 10-lead LFCSP package, and a 10-lead
MSOP package. These tiny packages make the ADG884 the
ideal solution for space-constrained applications.
When on, each switch conducts equally well in both directions
and has an input signal range that extends to the supplies. The
ADG884 exhibits break-before-make switching action.
flatness
ON
2:1 MUX/SPDT Audio Switch
ADG884
FUNCTIONAL BLOCK DIAGRAM
ADG884
S1A
S1B
IN1
IN2
S2A
S2B
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
PRODUCT HIGHLIGHTS
1. Single 1.8 V to 5.5 V operation.
2. High current handling capability (400 mA continuous
current at 3.3 V).
3. 1.8 V logic-compatible.
4. Low THD + N (0.01% typ).
5. Tiny 2 mm × 1.5 mm WLCSP package and 3 mm × 3 mm
10-lead LFCSP package.
Table 1. ADG884 Truth Table
Logic (IN1/IN2) Switch 1A/2A Switch 1B/2B
0 Off On
1 On Off
D1
D2
05028-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance, R
ON
0.28 Ω typ VDD = 4.5 V, VS = 0 V to VDD, IS = 100 mA
0.34 0.38 Ω max See Figure 18
On Resistance Match Between 0.01 Ω typ VDD = 4.5 V, VS = 2 V, IS = 100 mA
Channels, ∆R
ON
On Resistance Flatness, R
(ON) 0.1 Ω typ VDD = 4.5 V, VS = 0 V to V
FLAT
0.035 0.05 Ω max
0.13 0.15 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 5.5 V
Source Off Leakage, IS (OFF) ±0.2 nA typ VS = 0.6 V/4.5 V, VD = 4.5 V/0.6 V; Figure 19
Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 4.5 V; Figure 20
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
or I
INL
INH
INL
INH
2.0 V min
0.8 V max
0.005 µA typ VIN = V
±0.1 µA max
Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS
t
ON
IN
2
2 pF typ
42 ns typ RL = 50 Ω, CL = 35 pF
50 53 ns max VS = 3 V/0 V; Figure 21
t
15 ns typ RL = 50 Ω, CL = 35 pF
OFF
20 21 ns max VS = 3 V; Figure 21
Break-Before-Make Time Delay, t
BBM
16 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; Figure 22
Charge Injection 125 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Figure 23
Off Isolation −60 dB typ
Channel-to-Channel Crosstalk −120 dB typ
−60 dB typ
Total Harmonic Distortion, THD + N 0.017 %
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; Figure 25
−3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; Figure 25
CS (OFF) 103 pF typ
CD, CS (ON) 295 pF typ
POWER REQUIREMENTS VDD = 5.5 V
I
DD
0.003 µA typ Digital Inputs = 0 V or 5.5 V
1 µA max
1
Temperature range of the B version is −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
1
DD
V
or V
INL
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
DD
INH
Figure 24
S1A−S2A/S1B−S2B; R
= 50 Ω, CL = 5 pF,
L
f = 100 kHz; Figure 27
S1A−S1B/S2A−S2B; R
= 50 Ω, CL = 5 pF,
L
f = 100 kHz; Figure 26
= 32 Ω, f = 20 Hz to 20 kHz,
R
L
V
= 3.5 V p-p
S
Rev. 0 | Page 3 of 16
Page 4
ADG884
VDD = 3.4 V to 4.2 V; GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance, R
ON
0.33 Ω typ VDD = 3.4 V, VS = 0 V to VDD, IS = 100 mA
0.38 0.45 Ω max See Figure 18
On Resistance Match Between 0.013 Ω typ VDD = 3.4 V, VS = 2 V, IS = 100 mA
Channels, ∆R
ON
On Resistance Flatness, R
(ON) 0.13 Ω typ VDD = 3.4 V, VS = 0 V to V
FLAT
0.042 0.065 Ω max
0.155 0.175 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 4.2 V
Source Off Leakage, IS (OFF) ±0.2 nA typ VS = 0.6 V/3.9 V, VD = 3.9 V/0.6 V; Figure 19
Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.9 V; Figure 20
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
or I
INL
INH
INL
INH
2.0 V min
0.8 V max
0.005 µA typ VIN = V
±0.1 µA max
Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS
t
ON
IN
2
2 pF typ
42 ns typ RL = 50 Ω, CL = 35 pF
50 54 ns max VS = 1.5 V/0 V; Figure 21
t
15 ns typ RL = 50 Ω, CL = 35 pF
OFF
21 24 ns max VS = 1.5 V; Figure 21
Break-Before-Make Time Delay, t
BBM
17 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; Figure 22
Charge Injection 100 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Figure 23
Off Isolation −60 dB typ
Channel-to-Channel Crosstalk −120 dB typ
−60 dB typ
Total Harmonic Distortion, THD + N 0.01 %
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; Figure 25
−3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; Figure 25
CS (OFF) 110 pF typ
CD, CS (ON) 300 pF typ
POWER REQUIREMENTS VDD = 4.2 V
I
DD
0.003 µA typ Digital Inputs = 0 V or 4.2 V
1 µA max
1
Temperature range of the B version is −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
1
DD
V
or V
INL
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
DD
INH
Figure 24
S1A−S2A/S1B−S2B; R
= 50 Ω, CL = 5 pF,
L
f = 100 kHz; Figure 27
S1A−S1B/S2A−S2B; R
= 50 Ω, CL = 5 pF,
L
f = 100 kHz; Figure 26
= 32 Ω, f = 20 Hz to 20 kHz,
R
L
V
= 2 V p-p
S
Rev. 0 | Page 4 of 16
Page 5
ADG884
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance, R
ON
0.4 Ω typ VDD = 2.7 V, VS = 0 V to V
0.5 0.6 Ω max IS = 100 mA; Figure 18
On Resistance Match Between 0.02 Ω typ VDD = 2.7 V, VS = 0.6 V
Channels, ∆R
ON
On Resistance Flatness, R
(ON) 0.18 Ω typ VDD = 2.7 V, VS = 0 V to V
FLAT
0.07 0.1 Ω max IS = 100 mA
0.25 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 3.6 V
Source Off Leakage, IS (OFF) ±0.2 nA typ VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V, Figure 19
Channel On Leakage, ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.3 V; Figure 20
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
or I
INL
INH
INL
INH
1.3 V min
0.8 V max
0.005 µA typ VIN = V
±0.1 µA max
Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS
t
ON
IN
2
2 pF typ
42 ns typ RL = 50 Ω, CL = 35 pF
56 62 ns max VS = 1.5 V/0 V; Figure 21
t
14 ns typ RL = 50 Ω, CL = 35 pF
OFF
19 21 ns max VS = 1.5 V; Figure 21
Break-Before-Make Time Delay, t
BBM
24 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; Figure 22
Charge Injection 85 pC typ VS = 1.25 V, RS = 0 Ω, CL = 1 nF; Figure 23
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; Figure 24
Channel-to-Channel Crosstalk −120 dB typ
−60 dB typ
Total Harmonic Distortion, THD + N 0.03 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; Figure 25
–3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; Figure 25
CS (OFF) 110 pF typ
CD, CS (ON) 300 pF typ
POWER REQUIREMENTS VDD = 3.6 V
I
DD
0.003 µA typ Digital Inputs = 0 V or 3.6 V
1 µA max
1
Temperature range of the B version is −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
1
DD
V
or V
INL
INH
S1A−S2A/S1B−S2B; R
DD
DD
= 50 V, CL = 5 pF,
L
f = 100 kHz; Figure 27
S1A−S1B/S2A−S2B; R
= 50 Ω, CL = 5 pF,
L
f = 100 kHz; Figure 25
Rev. 0 | Page 5 of 16
Page 6
ADG884
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +6 V
Analog Inputs
Digital Inputs1
Peak Current, S or D
5 V Operation
Continuous Current, S or D
5 V Operation 400 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
10-Lead MSOP Package
θJC Thermal Impedance 13.5 °C/W
IR Reflow, Peak Temperature <20 s 235°C
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
1
−0.3 V to VDD + 0.3 V
−0.3 V to 6 V or 10 mA
(whichever occurs first)
600 mA mA (pulsed at
1 ms, 10% duty cycle max)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
Page 7
ADG884
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG884
TOP VIEW
(Not to Scale)
S1B GND
1
IN1
10
D1
1
V
S1
IN1
S1B
DD
D1
2
ADG884
3
TOP VIEW
(Not to Scale)
4
5
S2A
10
D2
9
IN2
8
7
S2B
6
GND
05028-002
Figure 2. LFCSP and MSOP Pin Configuration
9
S1A
8
(SOLDER BUMPS ON
OPPOSITE SIDE)
Figure 3. WLCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP, MSOP WLCSP Mnemonic Description
1 7 V
DD
Most Positive Power Supply Potential.
2, 5, 10, 7 6, 3, 8, 1 S1A, S1B, S2A, S2B Source Terminal. May be an input or output.
3, 9 5, 9 D1, D2 Drain Terminal. May be an input or output.
4, 8 4, 10 IN1, IN2 Logic Control Input.
6 2 GND Ground (0 V) Reference.
S2B
3
2
IN2
4
D2
5
V
S2A
DD
7
6
05028-003
Rev. 0 | Page 7 of 16
Page 8
ADG884
TYPICAL PERFORMANCE CHARACTERISTICS
0.30
0.25
0.20
0.15
ON RESISTANCE
0.10
0.05
0
012345
4.2V
5.5V
Figure 4. On Resistance vs. V
4.5V
SIGNAL RANGE
(VS), VDD = 4.2 V to 5.5 V
D
0.45
0.40
0.35
0.30
0.25
0.20
ON RESISTANCE
0.15
0.10
0.05
0
00.51.01.52.03.02.5
Figure 5. On Resistance vs. V
2.7V
3V
3.3V
SIGNAL RANGE
D
(VS), VDD = 2.7 V to 3.3 V
0.35
0.30
5V
TA = 25°C
= 100mA
I
DS
TA = 25°C
= 100mA
I
DS
VDD = 5V
= 100mA
I
DS
05028-004
05028-005
0.45
0.40
0.35
0.30
0.25
0.20
ON RESISTANCE
0.15
0.10
0.05
0
00.51.01.52.02.53.0
Figure 7. On Resistance vs. V
+85°C
+25°C
–40°C
SIGNAL RANGE
(VS) for Different Temperature, VDD = 3.3 V
D
5
4
3
2
1
0
–1
–2
LEAKAGE CURRENT (nA)
–3
–4
–5
01020304050806070
TEMPERATURE
Figure 8. Leakage Current vs. Temperature, V
5
4
VDD = 3.3V
I
DS
ID, IS (ON)
IS (OFF)
DD
VDD = 4.2V
= 100mA
05028-007
VDD = 5V
05028-008
= 5 V
0.25
0.20
0.15
ON RESISTANCE
0.10
0.05
0
01234
Figure 6. On Resistance vs. V
+85°C
+25°C
–40°C
SIGNAL RANGE
(VS) for Different Temperature, VDD = 5 V
D
05028-006
5
Rev. 0 | Page 8 of 16
3
2
1
LEAKAGE CURRENT (nA)
0
–1
01060504030208070
TEMPERATURE
Figure 9. Leakage Current vs. Temperature, V
ID, IS (ON)
IS (OFF)
= 4.2 V
DD
05028-009
Page 9
ADG884
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LEAKAGE CURRENT (nA)
0
–0.5
–1.0
01060504030208070
TEMPERATURE
VDD = 3.3V
ID, IS (ON)
IS (OFF)
05028-026
0
TA = 25°C
V
= 5V/4.2V/3V
DD
–1
–2
–3
–4
–5
ATTENUATION (dB)
–6
–7
–8
0.030.1010.001.00100.00
FREQUENCY (MHz)
05028-022
Figure 10. Leakage Current vs. Temperature, V
600
500
400
(pC)
300
INJ
Q
200
100
0
00.5 1.0 1.53.53.02.52.04.54.05.0
VDD = 3V
VS (V)
VDD = 5V
VDD = 4.2V
Figure 11. Charge Injection vs. Source Voltage
50
TA = 25°C
VDD = 5V
40
ON
OFF
Figure 12. t
VDD = 3V
TEMPERATURE (°C)
ON/tOFF
VDD = 5V
VDD = 3V
Times vs. Temperature
t
30
TIMES
20
t
10
0
–40–20040206080
= 3.3 V
DD
TA = 25°C
05028-010
05028-011
Figure 13. Bandwidth
0
TA = 25°C
V
= 5V/4.2V/3V
DD
–10
–20
–30
–40
–50
ATTENUATION (dB)
–60
–70
–80
101001M10M1k10k100k100M
FREQUENCY (MHz)
Figure 14. Off Isolation vs. Frequency
0
TA = 25°C
V
= 5V/4.2V/3V
DD
–10
–20
–30
–40
–50
ATTENUATION (dB)
–60
–70
–80
101001M10M1k10k100k100M
FREQUENCY (MHz)
Figure 15. Cross talk vs. Frequency
05028-023
05028-024
Rev. 0 | Page 9 of 16
Page 10
ADG884
0
–20
–40
–60
–80
–100
ATTENUATION (dB)
–120
–140
–160
101001M10M1k10k100k100M
TA = 25°C
V
= 5V/4.2V/3V
DD
FREQUENCY (MHz)
Figure 16. AC PSRR
05028-025
0.10
0.09
0.08
0.07
0.06
0.05
0.04
THD + N (%)
0.03
0.02
0.01
0
010k 20k 30k70k60k50k40k90k80k100k
3V, 1.5V p-p
5V, 3.5V p-p
4.2V, 2V p-p
FREQUENCY (kHz)
Figure 17. THD + N
05028-027
Rev. 0 | Page 10 of 16
Page 11
ADG884
TERMINOLOGY
IDD
Positive supply current.
, CS (ON)
C
D
On switch capacitance. Measured with reference to ground.
(VS)
V
D
Analog voltage on Terminals D, S.
R
ON
Ohmic resistance between D and S.
(ON)
R
FLAT
The difference between the maximum and minimum values of
on resistance as measured on the switch.
∆R
ON
On resistance match between any two channels.
(OFF)
I
S
Source leakage current with the switch off.
(OFF)
I
D
Drain leakage current with the switch off.
, IS (ON)
I
D
Channel leakage current with the switch on.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
(I
INL
INH
)
I
Input current of the digital input.
(OFF)
C
S
Off switch source capacitance. Measured with reference to
ground.
(OFF)
C
D
Off switch drain capacitance. Measured with reference to
ground.
C
IN
Digital input capacitance.
t
ON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
t
OFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
t
BBM
On or off time measured between the 80% points of both
switches when switching from one to another.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on-off switching.
Off Isolation
Measure of unwanted signal coupling through an off switch.
Crosstalk
Measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
On Response
Frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Rev. 0 | Page 11 of 16
Page 12
ADG884
V
TEST CIRCUITS
I
DS
V1
SD
V
S
RON = V1/I
Figure 18. On Resistance
IS (OFF)ID (OFF)
SD
AA
V
DS
05028-012
S
V
D
05028-013
NC
Figure 19. Off Leakage
V
DD
0.1µF
V
DD
S1B
V
S
S1A
IN
GND
D
R
L
50Ω
V
C
L
35pF
OUT
V
IN
V
OUT
Figure 21. Switching Times, t
50%50%
90%90%
t
ON
, t
ON
OFF
SD
Figure 20. On Leakage
t
OFF
05028-015
ID (ON)
A
V
D
05028-014
V
DD
0.1µF
V
DD
S1B
S
S1A
IN
GND
D
R
L
50Ω
V
C
L
35pF
OUT
0V
V
IN
V
OUT
Figure 22. Break-Before-Make Time Delay, t
50%50%
80%
t
BBM
BBM
80%
t
BBM
05028-016
V
DD
Q
INJ
SW OFF
= CL ×∆V
OUT
05028-017
SW ON
V
OUT
IN
V
OUT
∆V
OUT
S1B
V
S
D
S1A
IN
GND
NC
V
1nF
Figure 23. Charge Injection
Rev. 0 | Page 12 of 16
Page 13
ADG884
0.1µF
NC
S1B
OFF ISOLATION = 20 LOG
0.1µF
INSERTION LOSS = 20 LOG
V
DD
V
DD
S1A
D
GND
Figure 24. Off Isolation
V
DD
V
DD
S1AS1B
D
GND
50Ω
V
OUT
VS
WITH SWITCH
V
OUT
V
WITHOUT SWITCH
OUT
NETWORK
ANALYZER
50Ω
V
OUT
R
L
50Ω
NETWORK
ANALYZER
50Ω
V
V
OUT
R
L
50Ω
V
OUT
V
S
05028-018
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
R
50Ω
50Ω
S
L
Figure 26. Bandwidth
NETWORK
ANALYZER
V
OUT
50Ω
S
05028-019
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
50Ω
V
S
S2A
S2B
S1A
S1B
S1A
S1B
0.1µF
V
DD
V
DD
D
R
L
50Ω
GND
V
OUT
VS
D2
D1
V
OUT
VS
NC
05028-020
NC
50Ω
05028-021
Figure 25. Channel-to-Channel Crosstalk (S1A–S1B)
Figure 27. Channel-to-Channel Crosstalk (S1A–S2A)
Rev. 0 | Page 13 of 16
Page 14
ADG884
OUTLINE DIMENSIONS
INDEX
AREA
1.50
BCS SQ
0.80
0.75
0.70
SEATING
PLANE
Figure 28. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3.00
BSC SQ
0.50
TOP VIEW
0.80 MAX
0.55 TYP
SIDE VIEW
0.30
0.23
0.18
BSC
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
3 mm × 3 mm Body
(CP-10-9)
Dimensions shown in millimeters
BUMP 1
IDENTIFIER
10
EXPOSED
PAD
(BOTTOM VIEW)
6
1.74
1.64
1.49
1.66
1.60
1.54
TOP VIEW
(BALL SIDE DOWN)
PIN 1
INDICATOR
1
5
2.48
2.38
2.23
2.06
2.00
1.94
3.00 BSC
6
10
5
4.90 BSC
1.10 MAX
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
3.00 BSC
1
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
0.27
0.17
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 29. 10-Lead Mini Small Outline Package [MSOP]