Datasheet ADG791A Datasheet (ANALOG DEVICES)

I2C-Compatible, Wide Bandwidth,

www.BDTIC.com/ADI

FEATURES

Bandwidth: 325 MHz
Low insertion loss and on resistance: 2.6 Ω typical
On resistance flatness: 0.3 Ω typical
Single 3 V/5 V supply operation

3.3 V analog signal range (5 V supply, 75 Ω load)
Low quiescent supply current:
Fast switching times: t

2

C®-compatible interface

I

ON

Compact 24-lead LFCSP
ESD protection

4 kV human body model (HBM)
200 V machine model (MM)
1 kV field-induced charged device model (FICDM)

APPLICATIONS

S-video RGB/YPbPr video switches
HDTVs
Projection TVs
DVD-R/RW
AV receivers

GENERAL DESCRIPTION

1 nA typical

= 186 ns, t

= 177 ns

OFF

S1A

S1B

S2A

S2B

S3A

S3B

S4A

S4B

Quad, 2:1 Multiplexer

ADG791A/ADG791G

FUNCTIONAL BLOCK DIAGRAM

V

DD

GND

ADG791A

I2C SERIAL

INTERFACE

S1A

D1

S1B

S2A

D2

S2B

S3A

D3

S3B

S4A

D4

S4B

SCLSDAA2A1A0

Figure 1.

V

DD

ADG791G

I2C SERIAL

INTERFACE

GND

D1

D2

D3

D4

GPO1

SCLSDAA2A1A0

06033-001

The ADG791A/ADG791G are monolithic CMOS devices
comprising four 2:1 multiplexers/demultiplexers controllable
via a standard I

2

C serial interface. The CMOS process provides
ultralow power dissipation yet gives high switching speed and
low on resistance.

The on-resistance profile is very flat over the full analog input
r

ange and wide bandwidth ensures excellent linearity and low
distortion. These features, combined with a wide input signal
range make the ADG791A/ADG791G the ideal switching
solution for a wide range of TV applications including S-video,
RGB, and YPbPr video switches.

The switches conduct equally well in both

directions when on.
In the off condition, signal levels up to the supplies are blocked.
The ADG791A/ADG791G switches exhibit break-before-make
switching action. The ADG791G has one general-purpose logic
output pin controlled by the I
to control other non-I
The integrated I

2

2

C interface provides a large degree of flexibility

in the system design. It has three configurable I

2

C interface that can also be used

C-compatible devices such as video filters.

2

C address pins

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

that allow up to eight devices on the same bus. This allows the

er to expand the capability of the device by increasing the size

us
of the switching array.

The ADG791A/ADG791G operate from a single 3 V or 5 V

upply voltage and is available in a compact 4 mm × 4 mm

s
body, 24-lead LFCSP.

PRODUCT HIGHLIGHTS

1. Wide bandwidth: 325 MHz.

2. Ultralow power dissipation.

3. Extended input signal range.

4. Integrated I

5. Compact 4 mm × 4 mm, 24-lead, Pb-free LFCSP.

6. ESD protection tested as per ESD association standards:
4 kV HBM (ANS
200 V MM (ANSI/ESD STM5.2-1999)
1 kV FICDM (ANSI/ESDSTM5.3.1-1999)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

2

C serial interface.

I/ESD STM5.1-2001)

ADG791A/ADG791G

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Te r mi n ol o g y .................................................................................... 16

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

2

I

C Timing Specifications............................................................ 7

Timing Diagram ........................................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions .........................10

Typical Performance Characteristics ........................................... 11

Test Cir c ui t s .....................................................................................14

REVISION HISTORY

Theory of Operation ...................................................................... 17

2

I

C Serial Interface ..................................................................... 17

2

I

C Address.................................................................................. 17

Write Operation.......................................................................... 17

LDSW Bit..................................................................................... 19

Power On/Software Reset.......................................................... 19

Read Operation........................................................................... 19

Evaluation Board ............................................................................ 20

Using the ADG791G Evaluation Board .................................. 20

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

7/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADG791A/ADG791G

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SPECIFICATIONS

VDD = 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ1 Max Unit

ANALOG SWITCH

Analog Signal Range
V
On Resistance, R
V
On-Resistance Matching Between

Channels, ∆R
V
On-Resistance Flatness, R

LEAKAGE CURRENTS

Source OFF Leakage (IS
Drain OFF Leakage (ID
Channel ON Leakage (ID

DYNAMIC CHARACTERISTICS3

tON, t
t

OFF

CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 186 250 ns

ENABLE

, t

CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 177 240 ns

DISABLE

Break-Before-Make Time Delay, t
I2C to GPO Propagation Delay, tH, tL (ADG791G only) 130 ns
Off Isolation f = 10 MHz, RL = 50 Ω, see Figure 26 −60 dB
Channel-to-Channel Crosstalk f = 10 MHz, RL = 50 Ω, see Figure 27

Same Multiplexer
Different Multiplexer

−3 dB Bandwidth RL = 50 Ω, see Figure 25 325 MHz
THD + N RL = 100 Ω 0.14 %
Charge Injection CL = 1 nF, VS = 0 V, see Figure 30 5 pC
CS

(OFF)

CD

(OFF)

CD

, CS

(ON)

(ON)

Power Supply Rejection Ratio, PSRR f = 20 kHz 70 dB
Differential Gain Error CCIR330 test signal 0.32 %
Differential Phase Error CCIR330 test signal 0.44 Degrees

LOGIC INPUTS3

A0, A1, A2

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, CIN 3 pF

SCL, SDA

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, IIN VIN = 0 V to VDD 0.005 ±1 μA
Input Hysteresis 0.05 × VDD V
Input Capacitance, CIN 3 pF

2

ON

ON

VD = 0 V to 1 V, IDS = −10 mA 0.3 0.55 Ω

FLAT (ON)

) VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 ±0.25 nA

(OFF)

) VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 ±0.25 nA

(OFF)

, IS

(ON)

) VD = VS = 4 V/1 V, see Figure 24 ±0.25 nA

(ON)

D

VS = VDD, RL = 1 MΩ 0 4 V

= VDD, RL = 75 Ω 0 3.3 V

S

VD = 0 V, IDS = −10 mA, see Figure 22 2.6 3.5 Ω

= 0 V to 1 V, IDS = −10 mA, see Figure 22 4 Ω

D

V

= 0 V, IDS = −10 mA

D

= 1 V, IDS = −10 mA 0.6 Ω

D

0.15

0.5

Ω

CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 29 1 3 ns

−55 dB

−70 dB

10 pF
13 pF
27 pF

2.0 V

INH

0.8 V

INL

or I

VIN = 0 V to VDD 0.005 ±1 μA

INL

INH

0.7 × V

INH

−0.3 +0.3 × V

INL

V

DD

+ 0.3 V

DD

DD

V

Rev. 0 | Page 3 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

Parameter Conditions Min Typ1 Max Unit

LOGIC OUTPUTS

SDA Pin

Output Low Voltage, V

I

Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 10 pF

GPO1 Pin and GPO2 Pin

Output Low Voltage, V
Output High Voltage, V

POWER REQUIREMENTS

IDD Digital inputs = 0 V or VDD, I2C interface inactive 0.001 1 μA
I
I

1

All typical values are at TA = 25°C, unless otherwise stated.

2

Guaranteed by initial characterization, not subject to production test.

3

Guaranteed by design, not subject to production test.

3

OL

OL

OH

I

= 3 mA 0.4 V

SINK

= 6 mA 0.6 V

SINK

I

= +2 mA 0.4 V

LOAD

I

= −2 mA 2.0 V

LOAD

2

C interface active, f

2

C interface active, f

= 400 kHz 0.2 mA

SCL

= 3.4 MHz 0.7 mA

SCL

Rev. 0 | Page 4 of 24

ADG791A/ADG791G

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VDD = 3 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ1 Max Unit

ANALOG SWITCH

Analog Signal Range
V
On Resistance, R
V
On-Resistance Matching Between

Channels, ∆R

ON

V
On-Resistance Flatness, R

LEAKAGE CURRENTS

Source Off Leakage (IS
Drain Off Leakage (ID
Channel On Leakage (ID

DYNAMIC CHARACTERISTICS3

tON, t
t

OFF

CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 198 270 ns

ENABLE

, t

CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 195 260 ns

DISABLE

Break-Before-Make Time Delay, t
I2C to GPO Propagation Delay, tH, tL

(ADG791G only)
Off Isolation f = 10 MHz, RL = 50 Ω, see Figure 26 −60 dB
Channel-to-Channel Crosstalk f = 10 MHz, RL = 50 Ω, see Figure 27

Same Multiplexer

Different Multiplexer

−3 dB Bandwidth RL = 50 Ω, see Figure 25 310 MHz
THD + N RL = 100 Ω 0.14 %
Charge Injection CL = 1 nF, VS = 0 V, see Figure 30 2.5 pC
CS

(OFF)

CD

(OFF)

CD

, CS

(ON)

(ON)

Power Supply Rejection Ratio, PSRR f = 20 kHz 70 dB
Differential Gain Error CCIR330 test signal 0.28 %
Differential Phase Error CCIR330 test signal 0.28 Degrees

LOGIC INPUTS

3

A0, A1, A2

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, CIN 3 pF

SCL, SDA

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, IIN VIN = 0 V to VDD 0.005 ±1 μA
Input Hysteresis 0.05 × VDD V
Input Capacitance, CIN 3 pF

2

ON

VD = 0 V to 1 V, IDS = −10 mA 0.8 2.8 Ω

FLAT (ON)

) VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23 ±0.25 nA

(OFF)

) VD = 2 V/1 V, VS = 1 V/2 V, see Figure 23 ±0.25 nA

(OFF)

, IS

(ON)

) VD = VS = 2 V/1 V, see Figure 24 ±0.25 nA

(ON)

D

VS = VDD, RL = 1 MΩ 0 2.2 V

= VDD, RL = 75 Ω 0 1.7 V

S

VD = 0 V, IDS = −10 mA, see Figure 22 3 4 Ω

= 0 V to 1 V, IDS = −10 mA, see Figure 22 6 Ω

D

V

= 0 V, IDS = −10 mA

D

= 1 V, IDS = −10 mA 1.1 Ω

D

0.15

CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 29 1 3 ns
121 ns

−55 dB

−70 dB

10 pF
13 pF
27 pF

2.0 V

INH

0.8 V

INL

or I

VIN = 0 V to VDD 0.005 ±1 μA

INL

INH

0.7 × VDD V

INH

−0.3 +0.3 × V

INL

0.6

+ 0.3 V

DD

Ω

V

DD

Rev. 0 | Page 5 of 24

ADG791A/ADG791G

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Parameter Conditions Min Typ1 Max Unit

LOGIC OUTPUTS

SDA Pin

Output Low Voltage, V

Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 3 pF

GPO1 Pin and GPO2 Pin

Output Low Voltage, V
Output High Voltage, V

POWER REQUIREMENTS

IDD Digital inputs = 0 V or VDD, I2C interface inactive 0.001 1 μA
I
I

1

All typical values are at TA = 25°C, unless otherwise stated.

2

Guaranteed by initial characterization, not subject to production test.

3

Guaranteed by design, not subject to production test.

3

OL

OL

OH

I

= 3 mA 0.4 V

SINK

I

= 6 mA 0.6 V

SINK

I

= +2 mA 0.4 V

LOAD

I

= −2 mA 2.0 V

LOAD

2

C interface active, f

2

C interface active, f

= 400 kHz 0.1 mA

SCL

= 3.4 MHz 0.2 mA

SCL

Rev. 0 | Page 6 of 24

ADG791A/ADG791G

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I2C TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for timing diagram.

Table 3.

Parameter1Conditions Min Max Unit Description

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz
High speed mode
C
C
t1 Standard mode 4 μs t
Fast mode 0.6 μs
High speed mode
C
C
t2 Standard mode 4.7 μs t
Fast mode 1.3 μs
High speed mode
C
C
t

3

Fast mode 100 ns
High speed mode 10 ns

2

t

4

Fast mode 0 0.9 μs
High speed mode
C
C
t5 Standard mode 4.7 μs t
Fast mode 0.6 μs
High speed mode 160 ns
t6 Standard mode 4 μs t
Fast mode 0.6 μs
High speed mode 160 ns
t7 Standard mode 4.7 μs t
Fast mode 1.3 μs
t8 Standard mode 4 μs t
Fast mode 0.6 μs
High speed mode 160 ns
t9 Standard mode 1000 ns t
Fast mode 20 + 0.1 C
High speed mode
C
C
t10 Standard mode 300 ns t
Fast mode 20 + 0.1 C
High speed mode
C
C
t11 Standard mode 1000 ns t
Fast mode 20 + 0.1 C
High speed mode
C
C

= 100 pF max 3.4 MHz

B

= 400 pF max 1.7 MHz

B

= 100 pF max 60 ns

B

= 400 pF max 120 ns

B

= 100 pF max 160 ns

B

= 400 pF max 320 ns

B

Standard mode 250 ns t

Standard mode 0 3.45 μs t

= 100 pF max 0 703 ns

B

= 400 pF max 0 150 ns

B

B 300 ns

B

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

B 300 ns

B

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

B 300 ns

B

= 100 pF max 10 40 ns

B

= 400 pF max 20 80 ns

B

Rev. 0 | Page 7 of 24

, SCL high time

HIGH

, SCL low time

LOW

, data setup time

SU;DAT

, data hold time

HD;DAT

, setup time for a repeated start condition

SU;STA

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, setup time for stop condition

SU;STO

, rise time of SDA signal

RDA

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

ADG791A/ADG791G

S

www.BDTIC.com/ADI

Parameter1Conditions Min Max Unit Description

t

11A

Fast mode 20 + 0.1 C
High speed mode
C
C
t12 Standard mode 300 ns t
Fast mode 20 + 0.1 C
High speed mode
C
C
tSP Fast mode 0 50 ns Pulse width of suppressed spike
High speed mode 0 10 ns

1

Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD.

2

A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.

TIMING DIAGRAM

Standard mode 1000 ns

B 300 ns

B

= 100 pF max 10 80 ns

B

= 400 pF max 20 160 ns

B

B 300 ns

B

= 100 pF max 10 40 ns

B

= 400 pF max 20 80 ns

B

t

t

SCL

DA

t

7

PS S P

2

t

6

11

t

4

Figure 2. Timing Diagram for 2-Wire Serial Interface

t

12

t

1

t

3

, rise time of SCL signal after a repeated start condition

t

RCL1

and after an acknowledge bit.

, fall time of SCL signal

FCL

t

6

t

5

t

10

t

8

t

9

6033-002

Rev. 0 | Page 8 of 24

ADG791A/ADG791G

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Ratings

VDD to GND −0.3 V to +6 V
Analog, Digital Inputs

Continuous Current, S or D 100 mA
Peak Current, S or D

Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

24-Lead LFCSP 30°C/W
Lead Temperature, Soldering

(10 sec)

IR Reflow, Peak Temperature

(<20 sec)

−0.3 V to V
30 mA, whichever occurs first

300 mA (pulsed at 1 ms,
10% duty c

300°C

260°C

+ 0.3 V or

DD

ycle max)

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating may be applied at any one

e.

tim

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 9 of 24

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

GND

A0

A1

SCL

SDA

V

20

24

PIN 1
INDICATO R

1S1A
2S1B

ADG791A

3D1

TOP VIEW

4D2

(Not to Scale)

5S2B
6S2A

7

S3A

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD MUST BE TIED TO GND.

19

21

22

23

18 A2
17 NC
16 NC
15 NC
14 NC
13 NC

9

8

11

12

10

D3

D4

S3B

S4B

S4A

06033-004

Figure 3. ADG791G Pin Configuration Figure 4. ADG791A Pin Configuration

Table 5. ADG791A/ADG791G Pin Function

Descriptions

Pin No. Mnemonic Description

1 S1A A-Side Source Terminal for Mux 1. Can be an input or output.
2 S1B B-Side Source Terminal for Mux 1. Can be an input or output.
3 D1
4 D2
5 S2B
6 S2A
7 S3A
8 S3B
9 D3
10 D4
11 S4B
12 S4A
13 NC
14 NC
15 NC
16 NC/GPO1
17 NC
18 A2
19 A1
20 A0
21 SCL

Drain Terminal for Mux 1. Can be an input or output.
Drain Terminal for Mux 2. Can be an input or output.
B-Side Source Terminal for Mux 2. Can be an input or output.
A-Side Source Terminal for Mux 2. Can be an input or output.
A-Side Source Terminal for Mux 3. Can be an input or output.
B-Side Source Terminal for Mux 3. Can be an input or output.
Drain Terminal for Mux 3. Can be an input or output.
Drain Terminal for Mux 4. Can be an input or output.
B-Side Source Terminal for Mux 4. Can be an input or output.
A-Side Source Terminal for Mux 4. Can be an input or output.
Not Internally Connected.
Not Internally Connected.
Not Internally Connected.
Not Internally Connected for ADG791A/General-Purpose Logic Output 1 for ADG791G.
Not Internally Connected.
Logic Input. Sets Bit A2 from the least significant bit of the 7-bit slave address.
Logic Input. Sets Bit A1 from the least significant bit of the 7-bit slave address.
Logic Input. Sets Bit A0 from the least significant bit of the 7-bit slave address.
Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into

the device. External pull-up resistor required.
22 SDA
23 V

DD

Digital I/O. Bidirectional, open-drain data line. External pull-up resistor required.

Positive Power Supply Input.
24 GND Ground (0 V) Reference.

DD

GND

A0

A1

SCL

SDA

V

20

24

PIN 1
INDICATO R

1S1A
2S1B

ADG791G

3D1

TOP VIEW

4D2

(Not to Scale)

5S2B
6S2A

7

S3A

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD MUST BE TIED TO GND.

19

21

22

23

18 A2
17 NC
16 GPO1
15 NC
14 NC
13 NC

9

8

11

12

10

D3

D4

S3B

S4B

S4A

06033-003

Rev. 0 | Page 10 of 24

ADG791A/ADG791G

(

(

(

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TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT SIGNAL (V)

3.0

2.5

2.0

1.5

1.0

0.5

TA=25°C
1 CHANNEL

VDD=2.7V,RL=1MΩ

VDD=3.3V,RL=75Ω

VDD=3.3V,RL=1MΩ

VDD=3V,RL=1MΩ

VDD=3V,RL=75Ω

VDD=2.7V,RL=75Ω

Ω)

ON

R

4.0

3.5

3.

2.5

2.0

1.5

1.0

0.5

0

TA= 25°C
1 CHANNEL

V

=4.5V

DD

VDD=5.0V

VDD=5.5V

0

03

0.5 1.0 1.5 2. 0 2.5 3.0

INPUT SI GNAL (V)

.5

06033-005

Figure 5. Analog Signal Range, 3 V Supply

5.0

4.5

4.0

3.5

3.0

2.5

2.0

OUTPUT SIGNAL (V)

1.5

1.0

0.5

0

06

VDD=5V,RL=1MΩ

VDD=5.5V,RL=75Ω

VDD=4.5V,RL=1MΩ

12345

INPUT SI GNAL (V)

VDD=5.5V,RL=1MΩ

VDD=5V,RL=75Ω

VDD=4.5V,RL=75Ω

TA=25°C
1CHANNEL

06033-006

Figure 6. Analog Signal Range, 5 V Supply

6

TA= 25°C
1 CHANNEL

5

4

Ω)

3

ON

R

2

1

0

01

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Figure 7. On Resistance vs. V

VDD=2.7V

V

D(VS

)(V)

(VS), 3 V Supply

D

VDD=3.0V

VDD=3.3V

.8

06033-007

0

03.0

0.5 1.0 1.5 2.0 2.5

Figure 8. On Resistance vs. V

7

TA= 25°C
1 CHANNEL
V

=3V

6

DD

5

4

Ω)

ON

R

3

2

1

0

01

0.20.40.60.81.01.21.4

Figure 9. On Resistance vs. V

4.5
TA=+25°C

1 CHANNEL

4.0
V

=5V

DD

3.5

3.0

2.5

Ω)

ON

2.0

R

1.5

1.0

0.5

0

03.0

0.51.01.52.02.5

Figure 10. On Resistance vs. V

V

)(V)

D(VS

(VS), 5 V Supply

D

TA=+85°C

TA=–40°C

TA= +25°C

.6

V

)(V)

D(VS

(VS) for Various Temperatures, 3 V Supply

D

TA= +85°C

TA= +25°C

TA= –40°C

V

)(V)

D(VS

(VS) for Various Temperatures, 5 V Supply

D

06033-008

6033-009

06033-010

Rev. 0 | Page 11 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

0

TA=25°C

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

CHARGE INJECTIO N (pC)

–4.0

–4.5

–5.0

04

VDD=3V

VDD=5V

0.5 1. 0 1.5 2.0 2. 5 3.0 3.5

SOURCE VOL TAGE ( V)

.0

06033-011

Figure 11. Charge Injection vs. Source Voltage

220

210

t

(3V)

ON

200

(ns)

190

OFF

t

/

ON

t

180

t

(5V)

ON

170

t

OFF

(5V)

t

OFF

(3V)

0

TA=25°C

=3V/5V

V

DD

–20

–40

–60

CROSSTALK (dB)

–80

–100

–120

0.01 1000

0.1 1 10 100

FREQUENCY ( MHz)

SAME

MULTIPLEXER

DIFFERENT

ULTIPLEXER

M

Figure 14. Cross talk vs. Frequency

–1

TA=25°C
V

=5V

–3

DD

–5

–7

–9

ATTENUATIO N (dB)

–11

–13

06033-014

160

–40–200 20406080

TEMPERATURE (°C)

Figure 12. t

0

TA= 25°C

=3V/5V

V

DD

–20

–40

–60

–80

OFF ISO LATIO N (dB)

–100

–120

0.01 1000

0.1 1 10 100

vs. Temperature

ON/tOFF

FREQUENCY (MHz)

Figure 13. Off Isolation vs. Frequency

–15

0.01 1000

06033-012

0.1 1 10 100

FREQUENCY ( MHz)

06033-015

Figure 15. Bandwidth

0

TA= 25°C
1 CHANNEL

–10

V

=3V/5V

DD

NO DECOUPLING CAPACITORS USED

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

06033-013

0.001 0.01 0.1 1 10 100

0.0001 1000

FREQUENCY (MHz)

6033-016

Figure 16. PSRR v s. Frequency

Rev. 0 | Page 12 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

0.40
TA= 25°C

0.35

0.30

0.25

0.20

(mA)

DD

I

0.15

0.10

0.05

0

0.6 1.1 1.6 2.1 2. 6

0.1 3.1

f

CLK

Figure 17. I

1.4
TA= 25°C

1.2

1.0

0.8

0.6

(mA)

DD

I

0.4

0.2

0

VDD=3V

VDD=5V

FREQUENCY (MHz)

vs. f

Frequency

DD

CLK

VDD=5V

VDD=3V

06033-017

6

TA= 25°C

5

VDD=5V

4

3

2

GPO VOLTAGE (V)

1

0

–20 0

–18 –16 –14 –12 –10 –8 –6 –4 –2

LOAD CURRENT (mA)

Figure 20. GPO V

2.5
TA= 25°C

2.0

1.5

1.0

GPO VOLTAGE (V)

0.5

VDD=3V

vs. Load Current

OH

VDD=3V VDD=5V

06033-020

–0.2

06

12345

2

I

C LOGIC INPUT VOLTAGE (V)

Figure 18. I

vs. I2C Logic Input Voltage (SDA, SCL)

DD

06033-018

0

03

5 1015202530

LOAD CURRENT (mA)

Figure 21. GPO V

vs. Load Current

OL

5

06033-021

120

115

t

110

105

PROPAGATI ON DELAY (n s)

100

95

–40–200 20406080

Figure 19. I

(5V)

PHL

t

(5V)

PLH

2

C to GPO Propagation Delay vs. Temperature

TEMPERATURE (°C)

t

(3V)

PHL

t

(3V)

PLH

06033-019

(ADG791G Only)

Rev. 0 | Page 13 of 24

ADG791A/ADG791G

V

V

V

V

V

www.BDTIC.com/ADI

TEST CIRCUITS

SD

S

RON=V1/I

DD

0.1µF

I

DS

SA

V1

SB

DS

06033-022

D

GND

50Ω

50Ω

NETWORK
ANALYZER

50Ω

V

S

V

OUT

50Ω

06033-027

Figure 22. On Resistance

(OFF)

I

S

SD

A A

S

Figure 23. Off Leakage

NC

SD

NC = NO CO NNECT

ID(OFF)

V

D

ID(ON)

A

V

D

Figure 25. Bandwidth

DD

0.1µF

NETWORK

ANALYZER

S

6033-023

D

GND

50Ω

50Ω

50Ω

50Ω

50Ω

V

S

V

OUT

06033-028

Figure 26. Off Isolation

DD

0.1µF

SX

SY

06033-024

DY

DX

GND

50Ω

50Ω

50Ω 50Ω

NETWORK

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

Figure 24. On Leakage

Rev. 0 | Page 14 of 24

Figure 27. Channel-to-Channel Crosstalk

06033-029

ADG791A/ADG791G

V

V

V

www.BDTIC.com/ADI

CLOCK PULSES

CORRESPONDING TO THE

LDSW BITS

5V

0.1µF

V

DD

SD

C

R

V

S

I2C

INTERFACE

SCL

SDA

GND

50Ω

L

35pF

SCL

V

OUT

V

OUT

L

SCL

V

GPO

50%

90%

t

ON

CLOCK PULSES

CORRESPONDING TO THE

LDSW BITS

50%

90%

t

H

50%

50%

t

L

10%

10%

t

OFF

6033-025

Figure 28. Switching Time

5

CLOCK PULSE

0.1µF

V

SA

SB

S

DD

I2C

INTERFACE

D

R
50Ω

V

C

L

L

35pF

OUT

V

SCL

OUT

CORRESPONDING

TO THE LDSW BIT

V

S

80%

t

D

SCL

SDA

GND

06033-026

Figure 29. Break-Before-Make Time Delay

5

V

DD

R

S

SD

C

V

S

GND

1nF

L

V

OUT

SWITCH OFF

Figure 30. Charge Injection

SWITCH ON

Q

INJ=CL

× ΔV

OUT

ΔV

OUT

06033-030

Rev. 0 | Page 15 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

TERMINOLOGY

On Resistance (RON)

The series on-channel resistance measured between the S and

ins.

D p

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitudes plus noise of a signal to

he fundamental.

t

On Resistance Match (ΔR

ON

)

The channel-to-channel matching of on resistance when

nnels are operated under identical conditions.

cha

On Resistance Flatness (R

FLAT(ON)

)

The variation of on resistance over the specified range produced
b

y the specified analog input voltage change with a constant

load current.

Channel Off Leakage (I

OFF

)

The sum of leakage currents into or out of an off channel input.

Channel On Leakage (I

ON

)

The current loss/gain through an on-channel resistance,

eating a voltage offset across the device.

cr

, I

, I

Input Leakage Current (I

IN

INL

INH

)

The current flowing into a digital input when a specified low

el or high level voltage is applied to that input.

lev

Input/Output Off Capacitance (C

OFF

)

The capacitance between an analog input and ground when the

witch channel is off.

s

Input/Output On Capacitance (C

ON

)

The capacitance between the inputs or outputs and ground

hen the switch channel is on.

w

Digital Input Capacitance (C

)

IN

The capacitance between a digital input and ground.

Output On Switching Time (t

ON

)

The time required for the switch channel to close. The time is

asured from 50% of the falling edge of the LDSW bit to the

me
time the output reaches 90% of the final value.

Output Off Switching Time (t

OFF

)

The time required for the switch to open. The time is measured

rom 50% of the falling edge of the LDSW bit to the time the

f
output reaches 10% of the final value.

2

I

C to GPO Propagation Delay (tH, tL)

The time required for the logic value at the GPO pin to settle

fter loading a GPO command. The time is measured from 50%

a
of the falling edge of the LDSW bit to the time the output
reaches 90% of the final value for high and 10% for low.

−3 dB Bandwidth

The frequency at which the output is attenuated by 3 dB.

Off Isolation

The measure of unwanted signal coupling through an off switch.

Crosstalk

The measure of unwanted signal that is coupled through from
one

channel to another as a result of parasitic capacitance.

Charge Injection

The measure of the glitch impulse transferred from the digital

nput to the analog output during on/off switching.

i

Differential Gain Error

The measure of how much color saturation shift occurs when
t

he luminance level changes. Both attenuation and amplifica­tion can occur; therefore, the largest amplitude change between
any two levels is specified and expressed in %.

Differential Phase Error

The measure of how much hue shift occurs when the luminance
l

evel changes. It can be a negative or positive value and is expressed

in degrees of subcarrier phase.

Input High Voltage (V

INH

)

The minimum input voltage for Logic 1.

Input Low Voltage (V

INL

)

The maximum input voltage for Logic 0.

Output High Voltage (V

OH

)

The minimum output voltage for Logic 1.

Output Low Voltage (V

)

OL

The maximum output voltage for Logic 0.

I

DD

Positive supply current.

Rev. 0 | Page 16 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADG791A/ADG791G are monolithic CMOS devices
comprising four 2:1 multiplexers controllable via a standard I
serial interface. The CMOS process provides ultralow power
dissipation, yet offers high switching speed and low on resistance.

The on resistance profile is very flat over the full analog input
r

ange, and wide bandwidth ensures excellent linearity and low
distortion. These features, combined with a wide input signal
range, make the ADG791A/ADG791G an ideal switching
solution for a wide range of TV applications.

The switches conduct equally well in both
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I
switches (ADG791A/ADG791G) and general-purpose logic
pins (ADG791G only).

The ADG791A/ADG791G have many attractive features, such
a

s the ability to individually control each multiplexer, the option
of reading back the status of any switch. The ADG791G has one
general-purpose logic output pin controllable through the I
interface. The following sections describe these features in detail.

2

C interface controls the operation of the

directions when on.

2

C

2

C

I2C SERIAL INTERFACE

The ADG791A/ADG791G are controlled via an I2C-compatible
serial bus interface (refer to the I
from Philips Semiconductor) that allows the part to operate as a
slave device (no clock is generated by the ADG791A/ADG791G).
The communication protocol between the I
device operates as follows:

1. The mast

condition (defined as a high-to-low transition on the SDA
line while SCL is high). This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus an R/
bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.

2. The sla

transmitted address responds by pulling the SDA line
low during the ninth clock pulse (this is known as the
acknowledge bit).

er initiates data transfer by establishing a start

ve device whose address corresponds to the

2

C-Bus Specification available

2

C master and the

W

ata transmits over the serial bus in sequences of nine

3. D

clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of the clock signal, SCL, and remain stable
during the high period of SCL. Otherwise, a low-to-high
transition when the clock signal is high can be interpreted
as a stop event that ends the communication between the
master and the addressed slave device.

4. Af

ter transferring all data bytes, the master establishes a
stop condition, defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (the SDA line
remains high). The master then brings the SDA line low
before the 10
clock pulse to establish a stop condition.

th

clock pulse, and then high during the 10th

th

clock pulse to establish a

I2C ADDRESS

The ADG791A/ADG791G has a 7-bit I2C address. The four
most significant bits are internally hardwired while the last
three bits (A0, A1, and A2) are user-adjustable. This allows the
user to connect up to eight ADG791As/ADG791Gs to the same
bus. The I

2

C bit map shows the configuration of the address.

7-Bit I2C Address Configuration

MSB LSB

1 0 1 0 A2 A1 A0

WRITE OPERATION

When writing to the ADG791A/ADG791G, the user must

W

begin with an address byte and R/
switch acknowledges that it is prepared to receive data by
pulling SDA low. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL.
il

lustrates the entire write sequence for the ADG791A/
ADG791G. The first data byte (AX7 to AX0) controls the status
of the switches while the LDSW and RESETB bits from the
second byte control the operation mode of the device.

Tabl e 6 shows a list of all commands supported by the

G791A/ADG791G with the corresponding byte that needs

AD
to be loaded during a write operation.

bit, after which time the

Figure 31

At this stage, all other devices on the bus remain idle while
t

he selected device waits for data to be written to, or read
from, its serial register. If the R/
master reads from the slave device. However, if the R/
is set low, the master writes to the slave device.

W

bit is set high, the

W

bit

Rev. 0 | Page 17 of 24

To achieve the desired configuration, one or more commands

n be loaded into the device. Any combination of the

ca
commands listed in Tabl e 6 can be used with these restrictions:

• Onl

• W

y one switch from a given multiplexer can be ON at any

given time

hen a sequence of successive commands affect the same
element (that is, the switch or GPO pin), only the last
command is executed.

ADG791A/ADG791G

www.BDTIC.com/ADI

SCL

SDA

CONDITI ON
BY MASTE R

START

ADDRESS BYT E

A2 A1 A0 AX6AX7R/W

ACKNOWLEDG E

BY SWITCH

AX5 AX4 AX3 AX2 AX1 AX0 X X X X X X

ACKNOWLEDG E

BY SWIT CH

Figure 31. Write Operation

RESETB

LDSW

Table 6. ADG791A/ADG791G Command List

AX7 AX6 AX5 AX4 AX3 AX2 AX1 AX0 Addressed Switch

0 0 0 0 0 0 0 0 S1A/D1, S2A/D2, S3A/D3, S4A/D4 off
1 0 0 0 0 0 0 0 S1A/D1, S2A/D2, S3A/D3, S4A/D4 on
0 0 0 0 0 0 0 1 S1B/D1, S2B/D2, S3B/D3, S4B/D4 off
1 0 0 0 0 0 0 1 S1B/D1, S2B/D2, S3B/D3, S4B/D4 on
0 0 0 0 0 0 1 0 S1A/D1 off
1 0 0 0 0 0 1 0 S1A/D1 on
0 0 0 0 0 0 1 1 S1B/D1 off
1 0 0 0 0 0 1 1 S1B/D1 on
0 0 0 0 0 1 0 0 S2A/D2 off
1 0 0 0 0 1 0 0 S2A/D2 on
0 0 0 0 0 1 0 1 S2B/D2 off
1 0 0 0 0 1 0 1 S2B/D2 on
0 0 0 0 0 1 1 0 S3A/D3 off
1 0 0 0 0 1 1 0 S3A/D3 on
0 0 0 0 0 1 1 1 S3B/D3 off
1 0 0 0 0 1 1 1 S3B/D3 on
0 0 0 0 1 0 0 0 S4A/D4 off
1 0 0 0 1 0 0 0 S4A/D4 on
0 0 0 0 1 0 0 1 S4B/D4 off
1 0 0 0 1 0 0 1 S4B/D4 on

1

X
X
X
X
X
X
X
X
X
X

0 0 0 1 0 1 0 Reserved

1

0 0 0 1 0 1 1 Reserved

1

0 0 0 1 1 0 0 Reserved

1

0 0 0 1 1 0 1 Reserved

1

0 0 0 1 1 1 0 Mux 1 disabled (all switches connected to D1 are off )

1

0 0 0 1 1 1 1 Mux 2 disabled (all switches connected to D2 are off )

1

0 0 1 0 0 0 0 Mux 3 disabled (all switches connected to D3 are off )

1

0 0 1 0 0 0 1 Mux 4 disabled (all switches connected to D4 are off )

1

0 0 1 0 0 1 0 Reserved

1

0 0 1 0 0 1 1 Reserved
1 0 0 1 0 1 0 0 GPO1 high for ADG791G/reserved for ADG791A
0 0 0 1 0 1 0 0 GPO1 low for ADG791G/reserved for ADG791A
0 0 0 1 1 1 1 1 All muxes disabled
1 0 0 1 1 1 1 1 Reserved

1

X = Logic state does not matter.

CONDITION
BY MASTER

ACKNOWLEDG E

BY SWIT CH

STOP

06033-031

Rev. 0 | Page 18 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

LDSW BIT

The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG791A/ADG791G executes all the commands loaded
between two successive write operations that have set the
LDSW bit high.

Setting the LDSW high for every write cycle ensures that the

vice executes the command right after the LDSW bit was

de
loaded into the device. This setting can be used when the
desired configuration can be achieved by sending a single
command or when the switches and/or GPO pin are not
required to be updated at the same time. When the desired
configuration requires multiple commands with simultaneous
update, the LDSW bit should be set low while loading the
commands except the last one when the LDSW bit should be set
high. Once the last command with LDSW = high is loaded, the
device executes all commands received since the last update
simultaneously.

POWER ON/SOFTWARE RESET

The ADG791A/ADG791G has a software reset function
implemented by the RESETB bit from the second data byte
written to the device. For normal operation of the multiplexers
and GPO pin, this bit should be set high. When RESETB = low or
after power-up, the switches from all multiplexers are turned off
(open) and the GPO pin is set low.

READ OPERATION

When reading data back from the ADG791A/ADG791G, the

W

user must begin with an address byte and R/
then acknowledges that it is prepared to transmit data by
pulling SDA low. Following this acknowledgement, the
ADG791A/ADG791G transmits two bytes on the next clock
edges. These bytes contain the status of the switches, and each
byte is followed by an acknowledge bit. A logic high bit
represents a switch in the on (close) state while a low represents
a switch in the off (open) state. For the GPO pin (ADG791G
only), the bit represents the logic value of the pin.

llustrates the entire read sequence.

i

The bit maps accompanying Fi

gure 32 show the relationship
between the elements of the ADG791A and ADG791G (that it,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.

bit. The switch

Figure 32

ADG791A Bit Map

RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

S1A/D1 S1B/D1 S2A/D2 S2B/D2 S3A/D3 S3B/D3 S4A/D4 S4B/D4 - - - - - - - -

ADG791G Bit Map

RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

S1A/D1 S1B/D1 S2A/D2 S2B/D2 S3A/D3 S3B/D3 S4A/D4 S4B/D4 - - - - GPO1 - - -

SCL

SDA

CONDITION
BY MASTER

START

ADDRESS BYT E

A2 A1 A0 RB14RB15R/W

ACKNOWLEDG E

BY SWITCH

RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB 2 RB1 RB0

ACKNOWLEDG E

BY SWIT CH

Figure 32. ADG791A/ADG791G Read Operation

CONDITION
BY MASTER

ACKNOWLEDG E

BY SWIT CH

STOP

06033-032

Rev. 0 | Page 19 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

EVALUATION BOARD

The ADG791G evaluation kit allows designers to evaluate the
high performance of the device with a minimum of effort.

The evaluation kit includes a printed circuit board populated
w

ith the ADG791G. The evaluation board can be used to
evaluate the performance of both the ADG791A and
ADG791G. It interfaces to the USB port of a PC, or it can be
used as a standalone evaluation board. Software is available with
the evaluation board that allows the user to easily program the
ADG791G through the USB port. Schematics of the evaluation
board are shown in Figure 33 and Figure 34. The software runs
on any PC that has Microsoft® Windows® 2000 or Windows XP
installed.

USING THE ADG791G EVALUATION BOARD

The ADG791G evaluation kit is a test system designed to
simplify the evaluation of the device. Each input/output of the
part comes with a socket specifically chosen for easy
audio/video evaluation. A data sheet is also available and gives
full information on operating the evaluation board.

Rev. 0 | Page 20 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

G

R32

10kΩ

R31

10kΩ

47

PD2/FD1048PD3/FD1149PD4/FD1250PD5/FD1351PD6/FD14

U3

CY7C68013-CS P

CLKOUTD–D+

9

8

12345

D–

VBUS

USB-MINI-B

SDA

SD

D+

VDD

R9

2.2kΩ

R12

2.2kΩ

3.3V

R2

2.2kΩ

R1

3.3V

C22

3.3V

2.2kΩ

876

5

WP

SCL

VCC

24LC64

A0A1A2

123

3.3V

C23

C18

R6

75Ω

R5

75Ω

SDA

U2

VSS

4

55
43
32
27
17
11
7

3

2.2µF

0.1µF

C9

0.1µF

C4

10µF

T4

0.1µF

3.3V

R7

0Ω

3.3V 3.3V

T1

SCL_EN

18

PB0/FD019PB1/FD120PB2/FD221PB3/FD322PB4/FD423PB5/FD524PB6/FD625PB7/FD745PD0/FD846PD1/FD9

VCC
VCC
VCC
VCC
VCC
VCC
VCC

AVCC

*WAKEUP

RESET

424454

J1

SCL

Q2

G

SD

Q1

T27 T28

5229303116154

PD7/FD15

CTL0/*FLAGA

CTL1/*FLAGB

PA0/INT0

PA1/INT1

PA2 /*S LO E

PA3 /*W U2

PA4/FIFOADR0

PA5/FIFOADR1

33343536373839

*DENOTES

IO

GND

C2

0.1µF

SCL_EN

3.3V

876

5

S2

D2

IN1

VDD

U4

ADG821

S1D1IN2

123

SCL

SDA

CTL2/*FLAGC

PA6 /*P KT END

PA7 /*F LD /SL CS

RDY0/*SLRD

1

2

40

PROGRAMMABLE

POLARITY.

3.3V

GND

4

C10

22pF

XTAL1

24MHz

5

XTALOUT

RDY1/*SLWR

IFCLK

RSVD

13

14

C21

C19

C7

C5

C17

22pF

XTALIN

GND

56

GND

53

GND

41

GND

28

GND

26

GND

12

GND

10

6

AGND

R10

10kΩ

0.1µF

C20

0.1µF

0.1µF

C8

0.1µF

0.1µF

C6

0.1µF

3.3V

T26

ADP3303-3.3

0.1µF

126

OUT1

IN1

875

R11

1kΩ

D4

C15

0.1µF

C14

10µF

C16

0.1µF

3

U5

NR

OUT2

ERROR

4

GND

IN2

SD

06033-033

3.3V

SHIELD

J2-1 J2-2

Figure 33. EVAL-ADG791GEB Schematic, USB Controller Section

Rev. 0 | Page 21 of 24

J5

AB

VDD

C3

C13

0.1µF

10µF

ADG791A/ADG791G

www.BDTIC.com/ADI

SCL

VDD

C1

0.1µF

SCL

J6-1

J6-2

J6-3

SDA

SDA

J4-1

J4-3

J4-2

SCL

SDA

06033-034

T5 T6

GPO1

GPO2

J8

J7

J3

10kΩ

R8

10kΩ

R4

10kΩ

R3

R18

K1

GND

1

4

5

1

4

5

1

4

5

BOTTOM

2

CASE

TOP

3

CASE

PHONO_DUAL

K2

GND

BOTTOM

2

CASE

TOP

3

CASE

PHONO_DUAL

K3

GND

BOTTOM

2

CASE

TOP

3

CASE

PHONO_DUAL

R17

R16

R15

R14

R13

T24

A

T22 T23

T10

0Ω

R35

T2 T3

T25

T7 T8 T9

R30

0Ω

GPO1

0Ω

R34

R36

A

18
17
16
15
14
13

19

ADG791G

12

10

11

2324222120

U1

1
2
3

25

4

PADDLE

5
6

789

T21

R29

3

2

R28

T19 T20

R27

3

2

T18

PHONO_DUAL

CASE

5

TOP

CASE

4

BOTTOM

GND

1

K9

PHONO_DUAL

CASE

5

TOP

CASE

4

BOTTOM

GND

1

K8

R26

PHONO_DUAL

CASE

5

TOP

T11

T12

T13

T14

T15

T16 T17

R25

3

2

CASE

4

BOTTOM

GND

1

K7

R19

K4

2

GND

154

R20

3

TOP

BOTTOM

CASE

CASE

R21

R22

R23

2

3

TOP

K5

BOTTOM

GND

CASE

CASE

154

PHONO_DUAL

PHONO_DUAL

K6

154

2

BOTTOM

GND

Figure 34. EVAL-ADG791GEB Schematic, Chip Section

Rev. 0 | Page 22 of 24

R24

3

GPO2

TOP

CASE

CASE

PHONO_DUAL

ADG791A/ADG791G

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm x 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range I2C Speed Package Description Package Option

ADG791ABCPZ-REEL
ADG791ABCPZ-500RL7
ADG791ACCPZ-REEL
ADG791ACCPZ-500RL7
ADG791GBCPZ-REEL
ADG791GBCPZ-500RL7
ADG791GCCPZ-REEL
ADG791GCCPZ-500RL7
EVAL-ADG791GEB

1

Z = Pb-free part.

2

Evaluation board is RoHS compliant.

1

1

1

1

1

1

1

1

2

−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2

−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2
Evaluation Board

Rev. 0 | Page 23 of 24

ADG791A/ADG791G

www.BDTIC.com/ADI

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06033-0-7/06(0)

Rev. 0 | Page 24 of 24