Datasheet ADG787 Datasheet (Analog Devices)

Page 1
2.5 Ω CMOS Low Power
A
A

FEATURES

USB 1.1 signal switching compliant
−3 dB bandwidth 150 MHz Tiny 10-lead LFCSP, WLCSP, MSOP packages Single-supply 1.8 V to 5.5 V operation Low on resistance
2.5 Ω typ
3.35 max at 85°C
Typical power consumption: <0.1 µW

APPLICATIONS

USB 1.1 signal switching circuits Cellular phones PDAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems
Dual 2:1 Mux/Demux USB 1.1 Switch
ADG787

FUNCTIONAL BLOCK DIAGRAM

S1
S1B
S2
S2B
ADG787
IN1
IN2
SWITCHES SHOWN
FOR A LOGIC 0 INPUT
Figure 1.
D1
D2
05250-001

GENERAL DESCRIPTION

The ADG787 is a low voltage, CMOS device that contains two independently selectable, single-pole, double-throw (SPDT) switches. It is designed as a general analog/digital switch and can also be used for routing USB 1.1 signals.
This device offers low on resistance of typically 2.5 Ω, making the part an attractive solution for applications that require low distortion through the switch.
The ADG787 comes in a tiny 3 × 4 bump, 1.50 mm × 2.00 mm WLCSP, a tiny 10-lead LFCSP, and a 10-lead MSOP. These packages make the ADG787 the ideal solution for space­constrained applications.
Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG787 exhibits break-before-make switching action.
MASK: FS (12Mbps)
1
= 25°C
05250-032
Figure 2. Eye Pattern; 12 Mbps, V
V
= 4.2 V, PRBS 31
DD
20.0ns/DIV = 3V p-p
IN
T
A
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
ADG787

TABLE OF CONTENTS

Specifications..................................................................................... 3
Te r m in o l o g y .......................................................................................7
Absolute Maximum Ratings............................................................ 5
Truth Tab l e .................................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
1/05—Revision 0: Initial Version
Typical Perfor m a n c e Charac t e r ist i c s ..............................................8
Tes t Ci rc ui ts ..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Rev. 0 | Page 2 of 16
Page 3
ADG787

SPECIFICATIONS

VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V On Resistance (RON) 2.5 typ VDD = 4.2 V, VS = 0 V to VDD, IS = 10 mA
2.9 3.35 Ω max See Figure 28 On Resistance Match Between Channels (∆RON) 0.02 Ω typ VDD = 4.2 V, VS = 3.5 V, IS = 10 mA
0.1 max
On Resistance Flatness (R
) 0.65 typ VDD = 4.2 V, VS = 0 V to V
FLAT (ON)
0.8 0.95 max IS = 10 mA LEAKAGE CURRENTS VDD = 5.5 V
Source Off Leakage IS(OFF) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 29 Channel On Leakage ID, IS(ON) ±0.05 nA typ VS = VD = 1 V or 4.5 V; see Figure 30
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V
INH
INL
Input Current
I
or I
INL
INH
±0.1 µA max CIN, Digital Input Capacitance 2.5 pF typ
DYNAMIC CHARACTERISTICS
t
ON
2
19 22 ns max VS = 3 V; See Figure 31 t
3 ns typ RL = 50 Ω, CL = 35 pF
OFF
5 6 ns max VS = 3 V; See Figure 31 Propagation Delay Skew, t
SKEW
0.15 ns max Break-Before-Make Time Delay (t
) 10 ns typ RL = 50 Ω, CL = 35 pF
BBM
5 ns min VS1 = VS2 = 3 V; See Figure 32 Charge Injection 14 pC typ VD = 1 V, RS = 0 Ω, CL = 1 nF; See Figure 33 Off Isolation −63 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; See Figure 34 Channel-to-Channel Crosstalk −110 dB typ
−63 dB typ
Total Harmonic Distortion (THD + N) 0.03 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p Insertion Loss −0.2 dB typ RL = 50 Ω, CL = 5 pF; see Figure 35
−3 dB Bandwidth 145 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 35 CS (OFF) 16 pF typ CD, CS (ON) 40 pF typ
POWER REQUIREMENTS VDD = 5.5 V
I
DD
1 µA max
1
Temperature range for B version: −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
1
DD
V
DD
2.0 V min
0.8 V max
0.005 µA typ VIN = V
INL
or V
INH
13 ns typ RL = 50 Ω, CL = 35 pF
0.06 ns typ CL = 50 pF; VS = 3 V
S1A to S2A/S1B to S2B; R
= 50 Ω, CL = 5 pF,
L
f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; R
= 50 Ω, CL = 5 pF,
L
f = 1 MHz; see Figure 36
0.005 µA typ Digital inputs = 0 V or 5.5 V
Rev. 0 | Page 3 of 16
Page 4
ADG787
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V On Resistance (RON) 4 typ VDD = 2.7 V, VS = 0 V to VDD
5.2 5.5 max IS = 10 mA; see Figure 28 On Resistance Match Between Channels (∆RON) 0.07 typ VDD = 2.7 V, VS = 1.5 V
0.3 0.35 max IS = 10 mA On Resistance Flatness (R
) 1.6 typ VDD = 2.7 V, VS = 0 V to V
FLAT (ON)
2.2 2.5 max IS = 10 mA LEAKAGE CURRENTS VDD = 3.6 V
Source Off Leakage IS(OFF) ±0.01 nA typ VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 29 Channel On Leakage ID, IS(ON) ±0.01 nA typ VS = VD = 0.6 V or 3.3 V; see Figure 30
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V
INH
INL
Input Current
I
or I
INL
INH
±0.1 µA max CIN, Digital Input Capacitance 2 pF typ
DYNAMIC CHARACTERISTICS
t
ON
2
30 35 ns max VS = 1.5 V; see Figure 31 t
4 ns typ RL = 50 Ω, CL = 35 pF
OFF
6 7 ns max VS = 1.5 V; see Figure 31 Propagation Delay Skew, t
SKEW
0.12 ns max Break-Before-Make Time Delay (t
) 15 ns typ RL = 50 Ω, CL = 35 pF
BBM
5 ns min VS1 = VS2 = 1.5 V; see Figure 32 Charge Injection 10 pC typ VD = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation −63 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Channel-to-Channel Crosstalk −110 dB typ
−63 dB typ
Total Harmonic Distortion (THD + N) 0.07 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p Insertion Loss −0.24 dB typ RL = 50 Ω, CL = 5 pF; see Figure 35
−3 dB Bandwidth 145 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 35 CS (OFF) 16 pF typ CD, CS (ON) 40 pF typ
POWER REQUIREMENTS VDD = 3.6 V
I
DD
1 µA max
1
Temperature range for B version: −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
1
DD
1.3 V min
0.8 V max
0.005 µA typ VIN = V
INL
or V
INH
18 ns typ RL = 50 Ω, CL = 35 pF
0.04 ns typ CL = 50 pF; VS = 1.5 V
S1A to S2A/S1B to S2B; R
= 50 Ω, CL = 5 pF,
L
f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; R
= 50 Ω, CL = 5 pF,
L
f = 1 MHz; see Figure 35
0.005 µA typ Digital Inputs = 0 V or 3.6 V
Rev. 0 | Page 4 of 16
Page 5
ADG787

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +6 V Analog Inputs Digital Inputs1
Peak Current, S or D
5 V Operation 300 mA
3.3 V Operation
Continuous Current, S or D
5 V Operation 100 mA
3.3 V Operation 80 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C WLCSP Package (4-Layer Board)
θJA Thermal Impedance 120°C/W LFCSP Package (4-Layer Board)
θJA Thermal Impedance 61°C/W MSOP Package (4-Layer Board)
θJA Thermal Impedance 142°C/W
θJC Thermal Impedance 43.7°C/W Lead-Free Temperature Soldering
IR Reflow, Peak Temperature 260°C ± 5°C
1
−0.3 V to VDD + 0.3 V
−0.3 V to +6 V or 10 mA, whichever occurs first
200 mA (pulsed at 1 ms, 10% duty cycle max)
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

TRUTH TABLE

Table 4.
Logic (IN1/IN2) Switch 1A/2A Switch 1B/2B
0 Off On 1 On Off

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
Page 6
ADG787
A
2
3
4

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V
1
DD
S1
2
ADG787
D1
3
TOP VIEW
(Not to Scale)
IN1
4
S1B
5
Figure 3. 10-Lead LFCSP (CP-10)/MSOP (RM-10)
S2A
10
9
D2
8
IN2
7
S2B
6
GND
05250-002
abc
1
S1A
S2BGNDS1B
IN2IN1
D2D1
S2A
V
DD
05250-003
Figure 4. 10-Ball WLCSP (CB-10)
Top Vie w
(Bumps at the Bottom)
Table 5. 10-Lead LFCSP/MSOP Pin Function Descriptions
Pin No.
1 V 2 S1A
Mnemonic Description
DD
Most Positive Power Supply Potential. Source Terminal. May be an
input or output.
3 D1
Drain Terminal. May be an
input or output. 4 IN1 Logic Control Input. 5 S1B
Source Terminal. May be an
input or output. 6 GND Ground (0 V) Reference. 7 S2B
Source Terminal. May be an
input or output. 8 IN2 Logic Control Input. 9 D2
Drain Terminal. May be an
input or output. 10 S2A
Source Terminal. May be an
input or output.
Table 6. 10-Lead WLCSP Pin Function Descriptions
Ball
Mnemonic Description
Location
1a S1B
Source Terminal. May be an
input or output. 1b GND Ground (0 V) Reference. 1c S2B
Source Terminal. May be an
input or output. 2a IN1
Source Terminal. May be an
input or output. 2c IN2 Logic Control Input. 3a D1
Drain Terminal. May be an
input or output. 3c D2
Drain Terminal. May be an
input or output. 4a S1A Logic Control Input. 4b V
DD
4c S2A
Most Positive Power Supply Potential.
Source Terminal. May be an
input or output.
Rev. 0 | Page 6 of 16
Page 7
ADG787

TERMINOLOGY

I
DD
Positive supply current.
(VS)
V
D
Analog voltage on terminals D and S.
R
ON
Ohmic resistance between D and S.
FLAT (ON)
R
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
ΔR
ON
On resistance match between any two channels.
(OFF)
I
S
Source leakage current with the switch off.
(OFF)
I
D
Drain leakage current with the switch off.
, IS (ON)
I
D
Channel leakage current with the switch on.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
(I
INL
INH
)
I
Input current of the digital input.
(OFF)
C
S
Off switch source capacitance. Measured with reference to ground.
(OFF)
C
D
Off switch drain capacitance. Measured with reference to ground.
, CS (ON)
C
D
On switch capacitance. Measured with reference to ground.
C
IN
Digital input capacitance.
t
ON
Delay time between the 50% and the 90% points of the digital input and switch on condition.
t
BBM
On or off time measured between the 80% points of both switches when switching from one to another.
Charge Injection
A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.
Off Isolation A measure of unwanted signal coupling through an off switch.
Crosstalk A measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance.
−3 dB Bandwidth The frequency at which the output is attenuated by 3 dB.
On Response The frequency response of the on switch.
Insertion Loss The loss due to the on resistance of the switch.
THD + N The ratio of the harmonic amplitudes plus noise of a signal, to the fundamental.
T
SKEW
The measure of the variation in propagation delay between each channel.
Rise Time Delay The rise time of a signal is a measure of the time for the signal to rise from 10% of the ON level to 90% of the ON level. Rise time delay is the difference between the rise time, measured at the input, and the rise time, measured at the output.
Fall Time Delay The fall time of a signal is a measure of the time for the signal to fall from 90% of the ON level to 10% of the ON level. Fall time delay is the difference between the fall time, measured at the input, and the fall time, measured at the output.
Rise-Time-to-Fall-Time Mismatch
This is the absolute value between the variation in the fall time and the rise time, measured at the output.
t
OFF
Delay time between the 50% and the 90% points of the digital input and switch off condition.
Rev. 0 | Page 7 of 16
Page 8
ADG787

TYPICAL PERFORMANCE CHARACTERISTICS

3.0
2.5
2.0
1.5
1.0
ON RESISTANCE (Ω)
= 4.5V
V
DD
= 4.2V
V
DD
V
= 5V
DD
TA = 25°C
= 10mA
I
DS
= 5.5V
V
DD
3.5
3.0
2.5
2.0
1.5
ON RESISTANCE (Ω)
1.0
TA = +85°C
T
= +25°C
A
T
= –40°C
A
VDD = 4.2V
= 10mA
I
DS
0.5
0
013524
Figure 5. On Resistance vs. V
5.0 TA = 25°C
= 10mA
I
4.5
DS
4.0
3.5
3.0
ON RESISTANCE (Ω)
2.5
2.0
1.5
1.0
0.5
0
0 4.03.53.02.52.01.51.00.5
V
DD
Figure 6. On Resistance vs. V
3.0
2.5
2.0
1.5
1.0
ON RESISTANCE (Ω)
0.5
0
0 5.04.0 4.53.53.02.52.01.51.00.5
Figure 7. On Resistance vs. V
SIGNAL RANGE
(VS), VDD = 4.2 V to 5.5 V
D
= 2.7V
V
DD
V
= 3V
DD
= 3.3V
SIGNAL RANGE
SIGNAL RANGE
(VS) for Different Temperatures, VDD = 5 V
D
VDD = 3.6V
(VS), VDD = 2.7 V to 3.6 V
D
= +85°C
T
A
T
= +25°C
A
T
= –40°C
A
VDD = 5V
= 10mA
I
DS
05250-004
05250-005
05250-006
0.5
0
0 4.03.53.02.52.01.51.00.5
Figure 8. On Resistance vs. V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
ON RESISTANCE (Ω)
1.0
0.5
0
0 3.02.52.01.51.00.5
Figure 9. On Resistance vs. V
2.0
1.5
1.0
0.5
0
–0.5
CURRENT (nA)
–1.0
–1.5
–2.0
0870605040302010
SIGNAL RANGE
(VS) for Different Temperatures, VDD = 4.2 V
D
T
= +85°C
A
T
= +25°C
A
SIGNAL RANGE
(VS) for Different Temperatures, VDD = 3 V
D
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperatures, V
= –40°C
T
A
IS, ID (ON)
I
S
(OFF)
DD
05250-007
VDD = 3V
= 10mA
I
DS
05250-008
05250-040
0
= 5.5 V
Rev. 0 | Page 8 of 16
Page 9
ADG787
2.0
1.5
1.0
0.5
0
–0.5
CURRENT (nA)
–1.0
–1.5
–2.0
0870605040302010
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, V
IS (OFF)
I
, ID (ON)
S
DD
05250-041
0
= 3.3 V
30
25
20
15
TIME (ns)
10
5
0 –40 806040200–20
TA = 25°C
= 3V
V
DD
T
ON
VDD = 5V
T
OFF
Figure 14. t
VDD = 3V
V
= 5V
DD
TEMPERATURE (°C)
Times vs. Temperature
ON/tOFF
05250-013
2.0
1.8
1.6
1.4
LOGIC THRESHOLD POINT (V)
1.2
1.0
0.8
0.6
0.4
0.2
0
1.5 5.55.04.54.03.53.02.52.0
VIN RISING VIN FALLING
SUPPLY VOLTAGE VDD (V)
05250-011
Figure 12. Threshold Voltage vs. Supply
25
TA = 25°C
20
15
V
= 3V
Q-INJ (pC)
10
5
DD
VDD = 5V
0
–1
VDD = 3V/4.2V/5V T
= 25°C
A
–2
–3
–4
–5
ATTENUATION (dB)
–6
–7
–8
100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 15. Bandwidth
0
VDD = 3V/4.2V/5V
= 25°C
T
A
–20
–40
–60
–80
ATTENUATION (dB)
–100
05250-014
0
0 5.03.0 3.5 4.0 4.52.52.01.51.00.5
VD (V)
Figure 13. Charge Injection vs. Source Voltage
05250-012
Rev. 0 | Page 9 of 16
–120
100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency
05250-015
Page 10
ADG787
0
VDD = 3V/4.2V/5V T
–20
= 25°C
A
3.0 INPUT RISE/FALL TIME = 15ns
= 25°C
T
A
2.5
–40
–60
–80
ATTENUATION (dB)
–100
–120
100 1k 10k 100k 1M 10M 100M 1G
S1A–S1B
S1A–S2A
FREQUENCY (Hz)
Figure 17. Cross talk vs. Frequency
0
VDD = 3V/4.2V/5V
= 25°C
T
A
NO SUPPLY DECOUPLING
–20
–40
–60
PSRR (dB)
–80
–100
–120
100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 18. AC Power Supply Rejection Ratio (PSRR)
05250-030
05250-031
2.0
1.5
DELAY (ns)
1.0
0.5
0
2.7 5.24.74.23.2 3.7
RISE DELAY
SUPPLY VOLTAGE (V)
Figure 20. Rise/Fall Time Delay vs. Supply Voltage
2.0 INPUT RISE/FALL TIME = 15ns
= 4.2V
V
DD
1.8
1.6
1.4
1.2
1.0
0.8
DELAY (ns)
0.6
0.4
0.2
0 –40 856035–15 10
TEMPERATURE (°C)
Figure 21. Rise/Fall Time Delay vs. Temperature
FALL DELAY
RISE DELAY
FALL DELAY
05250-044
05250-045
0.10
0.09
0.08
0.07
0.06
0.05
0.04
THD+N (%)
0.03
0.02
0.01
0
10 100k10k100 1k
VDD = 3V, VS = 2V p-p
V
Figure 19. Total Harmonic Distortion + Noise
= 5V, VS = 2V p-p
DD
FREQUENCY (Hz)
05250-043
Rev. 0 | Page 10 of 16
2.0
INPUT RISE/FALL TIME = 15ns
= 25°C
T
A
1.5
1.0
MISMATCH (ns)
0.5
0
2.5 3.0 5.55.04.53.5 4.0 SUPPLY (V)
Figure 22. Rise-Time-to-Fall-Time Mismatch vs. Supply Voltage
05250-046
Page 11
ADG787
1.2 INPUT RISE/FALL TIME = 15ns
= 4.2V
V
DD
1.0
0.8
0.6
MISMATCH (ns)
0.4
0.2
MASK: FS (12Mbps)
1
0 –40 –15 10 35 60 85
TEMPERATURE (°C)
Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature
300
INPUT RISE/FALL TIME = 15ns
= 25°C
T
A
250
200
(ps)
150
PROP SKEW
T
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Figure 24. Propagation Delay Skew (t
200
INPUT RISE/FALL TIME = 15ns
= 4.2V
V
180
DD
160
140
120
(ps)
100
SKEW
80
T
60
40
20
0 –40 –15 10 35 60 85
Figure 25. Propagation Delay Skew (t
SUPPLY (V)
SKEW
TEMPERATURE (°C)
SKEW
) vs. Supply Voltage
) vs. Temperature
05250-047
05250-048
05250-049
Figure 26. Eye Pattern, 12 Mbps, V
MASK: FS (12Mbps)
1
Figure 27. Eye Pattern, 12 Mbps, V
20.0ns/DIV
2.5GS/s 400ps/pt
= 4.2 V, TA = 85°C, PRBS 31
DD
20.0ns/DIV
2.5GS/s 400ps/pt
= 4.2 V, TA = −40°C, PRBS 31
DD
05250-033
05250-034
Rev. 0 | Page 11 of 16
Page 12
ADG787
V
V
V
V

TEST CIRCUITS

I
DS
V1
SD
S
RON = V1/I
Figure 28. On Resistance
IS (OFF) ID (OFF)
SD
A A
S
V
D
05250-017
Figure 29. Off Leakage
DS
05250-016
V
DD
0.1µF
V
DD
S1B
V
S
S1A
IN
GND
D
R
L
50
V
C
L
35pF
OUT
V
IN
V
OUT
Figure 31. Switching Times, t
50% 50%
90% 90%
t
ON
, t
ON
OFF
NC
SD
Figure 30. On Leakage
t
OFF
05250-019
ID (ON)
A
V
D
05250-018
V
DD
0.1µF
V
IN
V
DD
V
S1B
S
S1A
IN
GND
D
R
L
50
V
C
L
35pF
OUT
0V
V
OUT
Figure 32. Break-Before-Make Time Delay, t
50% 50%
80%
t
BBM
BBM
80%
t
BBM
05250-020
DD
SW ON
V
OUT
IN
V
OUT
V
OUT
S1B
S
D
S1A
IN
GND
NC V
1nF
Q
INJ
SW OFF
= CL ×∆V
OUT
05250-021
Figure 33. Charge Injection
Rev. 0 | Page 12 of 16
Page 13
ADG787
C
G
V
G
0.1µF
V
DD
0.1µF
DD
V
DD
NC
S1B
OFF ISOLATION = 20 LOG
GND
S1A
D
50
V
OUT
VS
Figure 34. Off Isolation
0.1µF
V
OUT
HANNEL-TO-CHANNEL CROSSTALK = 20 LO
R 50
V
L
50
S
S1A
S1B
Figure 35. Channel-to-Channel Crosstalk (S1A to S1B)
V
V
GND
V
VS
DD
DD
OUT
NETWORK ANALYZER
50
V
V
OUT
R
L
50
D
V
DD
GND
S1AS1B
D
V
OUT
V
WITHOUT SWITCH
OUT
S
05250-022
INSERTION LOSS = 20 LOG
NETWORK
ANALYZER
50
R
L
50
WITH SWITCH
V
S
V
OUT
05250-024
Figure 36. Bandwidth
NETWORK
ANALYZER
V
R 50
OUT
50
L
CHANNEL-TO-CHANNEL CROSSTALK = 20 LO
50 V
S
S2A S2B
S1A S1B
D2
D1
V
OUT
VS
NC
NC
50
05250-025
Figure 37. Channel-to-Channel Crosstalk (S1A to S2A)
05250-023
Rev. 0 | Page 13 of 16
Page 14
ADG787

OUTLINE DIMENSIONS

INDEX
1.50
BCS SQ
0.80
0.75
0.70
SEATING
PLANE
AREA
3.00
BSC SQ
TOP VIEW
SIDE VIEW
0.30
0.23
0.18
0.80 MAX
0.55 TYP
0.50
BSC
0.50
0.40
0.30
0.20 REF
10
0.05 MAX
0.02 NOM
EXPOSED
(BOTTOM VIEW)
6
1.74
1.64
1.49
PIN 1 INDICATOR
PAD
Figure 38. 10-Lead Lead Frame Chip Scale Package [WD_LFCSP]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
3.00 BSC
1
2.48
2.38
2.23
5
BUMP 1
IDENTIFIER
6
10
5
4.90 BSC
1.10 MAX
SEATING PLANE
0.23
0.08
3.00 BSC
PIN 1
0.95
0.85
0.75
0.15
0.00
1
0.50 BSC
0.27
0.17
COPLANARITY
0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 39. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.63
1.56
1.50
1.44
TOP VIEW
(BALL SIDE DOWN)
2.06
2.00
1.94
0.57
0.51 SEATING
PLANE
0.50 BSC BALL PITCH
8° 0°
0.80
0.60
0.40
ABC
0.36
0.32
0.28 BOTTOM
VIEW
1
2
3
0.26
0.22
0.18
0.11
0.09
0.07
Figure 40. 10-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-10)
Dimensions shown in millimeters
Rev. 0 | Page 14 of 16
4
Page 15
ADG787

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding
ADG787BRMZ ADG787BRMZ-500RL72 –40°C to +85°C 10-Lead Mini Small Outline Package (MSOP) RM-10 S04 ADG787BRMZ-REEL2 –40°C to +85°C 10-Lead Mini Small Outline Package (MSOP) RM-10 S04 ADG787BCBZ-500RL7 ADG787BCBZ-REEL ADG787BCPZ-500RL72 –40°C to +85°C 10-Lead Lead Frame Chip Scale Package (WD_LFCSP) CP-10-9 S04 ADG787BCPZ-REEL2 –40°C to +85°C 10-Lead Lead Frame Chip Scale Package (WD_LFCSP) CP-10-9 S04
1
Due to space constraints, branding on this package is limited to three characters.
2
Z = Pb-free part.
3
Contact sales for availability.
2
–40°C to +85°C 10-Lead Mini Small Outline Package (MSOP) RM-10 S04
2, 3
–40°C to +85°C 10-Ball Wafer Level Chip Scale Package (WLCSP) CB-10 S04
2,.3
–40°C to +85°C 10-Ball Wafer Level Chip Scale Package (WLCSP) CB-10 S04
1
Rev. 0 | Page 15 of 16
Page 16
ADG787
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D05250–0–1/05(0)
Rev. 0 | Page 16 of 16
Loading...