Page 1
2.5 Quad SPST Switches
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG781
SWITCHES SHOWN FOR A LOGIC “1” INPUT
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG782
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG783
a
FEATURES
1.8 V to 5.5 V Single Supply
Low On Resistance (2.5 Typ)
Low On-Resistance Flatness (0.5 )
–3 dB Bandwidth > 200 MHz
Rail-to-Rail Operation
20-Lead 4 mm 4 mm Chip Scale Package
Fast Switching Times
= 16 ns
t
ON
t
= 10 ns
OFF
Typical Power Consumption (< 0.01 W)
TTL/CMOS Compatible
For Functionally Equivalent Devices in 16-Lead TSSOP
and SOIC Packages, See ADG711/ADG712/ADG713
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
in Chip Scale Package
ADG781/ADG782/ADG783
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG781, ADG782, and ADG783 are monolithic CMOS
devices containing four independently selectable switches. These
switches are designed on an advanced submicron process that
provides low power dissipation and high switching speed, low on
resistance, low leakage currents and high bandwidth.
They are designed to operate from a single 1.8 V to 5.5 V supply, making them ideal for use in battery powered instruments
and with the new generation of DACs and ADCs from Analog
Devices. Fast switching times and high bandwidth make the
part suitable for video signal switching.
The ADG781, ADG782, and ADG783 contain four independent
single-pole/single throw (SPST) switches. The ADG781 and
ADG782 differ only in that the digital control logic is inverted.
The ADG781 switches are turned on with a logic low on the
appropriate control input, while a logic high is required to turn
on the switches of the ADG782. The ADG783 contains two
switches whose digital control logic is similar to the ADG781,
while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON.
The ADG783 exhibits break-before-make switching action.
The ADG781/ADG782/ADG783 are available in 20-lead chip
scale packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. 20-Lead 4 mm ⫻ 4 mm Chip Scale Package (CSP).
2. 1.8 V to 5.5 V Single Supply Operation. The ADG781,
ADG782, and ADG783 offer high performance and are
fully specified and guaranteed with 3 V and 5 V supply
rails.
3. Very Low R
voltage of 1.8 V, R
(4.5 Ω max at 5 V, 8 Ω max at 3 V). At supply
ON
is typically 35 Ω over the temperature
ON
range.
4. Low On-Resistance Flatness.
5. –3 dB Bandwidth >200 MHz.
6. Low Power Dissipation. CMOS construction ensures low
power dissipation.
7. Fast t
ON/tOFF.
8. Break-Before-Make Switching. This prevents channel shorting
when the switches are configured as a multiplexer (ADG783
only).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Page 2
(VDD = 5 V 10%, GND = 0 V. All specifications
ADG781/ADG782/ADG783–SPECIFICATIONS
–40C to +85C unless otherwise noted.)
B Version
–40C to
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance (R
) 2.5 Ω typ VS = 0 V to VDD, IS = –10 mA;
ON
DD
V
4 4.5 Ω max Test Circuit 1
On-Resistance Match Between 0.05 Ω typ V
Channels (∆R
On-Resistance Flatness (R
) 0.4 Ω max
ON
FLAT(ON)
) 0.5 Ω typ VS = 0 V to VDD, IS = –10 mA
= 0 V to VDD, IS = –10 mA
S
1.0 Ω max
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ± 0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V;
S
= 5.5 V;
DD
± 0.1 ± 0.2 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ± 0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V;
D
± 0.1 ± 0.2 nA max Test Circuit 2
Channel ON Leakage I
, IS (ON) ± 0.01 nA typ VS = VD = 1 V, or 4.5 V;
D
± 0.1 ± 0.2 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time Delay, t
(ADG783 Only) 1 ns min V
Charge Injection 3 pC typ V
2
11 ns typ RL = 300 Ω, CL = 35 pF,
16 ns max V
= 3 V; Test Circuit 4
S
6 ns typ RL = 300 Ω, CL = 35 pF,
10 ns max V
D
6 ns typ RL = 300 Ω, CL = 35 pF,
= 3 V; Test Circuit 4
S
= VS2 = 3 V; Test Circuit 5
S1
= 2 V; RS = 0 Ω, CL = 1 nF;
S
Test Circuit 6
Off Isolation –58 dB typ R
–78 dB typ R
= 50 Ω, CL = 5 pF, f = 10 MHz
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 7
Channel-to-Channel Crosstalk –90 dB typ R
= 50 Ω, CL = 5 pF, f = 10 MHz;
L
Test Circuit 8
Bandwidth –3 dB 200 MHz typ R
(OFF) 10 pF typ f = 1 MHz
C
S
C
(OFF) 10 pF typ f = 1 MHz
D
= 50 Ω, CL = 5 pF; Test Circuit 9
L
CD, CS (ON) 22 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
0.001 µA typ Digital Inputs = 0 V or 5.5 V
= 5.5 V
DD
1.0 µA max
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
Page 3
ADG781/ADG782/ADG783
SPECIFICATIONS
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance (R
On-Resistance Match Between 0.1 Ω typ V
Channels (∆R
On-Resistance Flatness (R
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
INH
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time Delay, t
(ADG783 Only) 1 ns min V
Charge Injection 3 pC typ V
Off Isolation –58 dB typ R
Channel-to-Channel Crosstalk –90 dB typ R
Bandwidth –3 dB 200 MHz typ R
C
(OFF) 10 pF typ f = 1 MHz
S
C
(OFF) 10 pF typ f = 1 MHz
D
CD, CS (ON) 22 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
) 5 5.5 Ω typ VS = 0 V to VDD, IS = –10 mA;
ON
) 0.5 Ω max
ON
S
(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;
D
INH
INL
1
(VDD = 3 V 10%, GND = 0 V. All specifications –40C to +85C unless otherwise noted.)
B Version
–40C to
V
DD
10 Ω max Test Circuit 1
= 0 V to VDD, IS = –10 mA
S
FLAT(ON)
(OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;
, IS (ON) ±0.01 nA typ VS = VD = 1 V, or 3 V;
D
) 2.5 Ω typ VS = 0 V to VDD, IS = –10 mA
= 3.3 V;
DD
± 0.1 ± 0.2 nA max Test Circuit 2
± 0.1 ± 0.2 nA max Test Circuit 2
± 0.1 ± 0.2 nA max Test Circuit 3
2.0 V min
0.8 V max
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
2
13 ns typ RL = 300 Ω, CL = 35 pF,
20 ns max V
= 2 V; Test Circuit 4
S
7 ns typ RL = 300 Ω, CL = 35 pF,
12 ns max V
D
7 ns typ RL = 300 Ω, CL = 35 pF,
= 2 V; Test Circuit 4
S
= VS2 = 2 V; Test Circuit 5
S1
= 1.5 V; RS = 0 Ω, CL = 1 nF;
S
Test Circuit 6
= 50 Ω, CL = 5 pF, f = 10 MHz
–78 dB typ R
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 7
= 50 Ω, CL = 5 pF, f = 10 MHz;
L
Test Circuit 8
= 50 Ω, CL = 5 pF; Test Circuit 9
L
= 3.3 V
DD
0.001 µA typ Digital Inputs = 0 V or 3.3 V
1.0 µA max
REV. A
–3–
Page 4
ADG781/ADG782/ADG783
,
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs
2
. . . . . . . . . . –0.3 V to VDD + 0.3 V or
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
1
30 mA, Whichever Occurs First
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow (<20 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Chip Scale Package
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 32°C/W
θ
JA
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG781BCP –40°C to +85°C 20-Lead Chip Scale (CSP) CP-20
ADG782BCP –40°C to +85°C 20-Lead Chip Scale (CSP) CP-20
ADG783BCP –40°C to +85°C 20-Lead Chip Scale (CSP) CP-20
Table I. Truth Table (ADG781/ADG782)
ADG781 In ADG782 In Switch Condition
01ON
1 0 OFF
Table II. Truth Table (ADG783)
Logic Switch 1, 4 Switch 2, 3
0 OFF ON
1 ON OFF
PIN CONFIGURATION
(CSP)
NC
IN1NCIN2
PIN 1
D1
S1
GND
S4
D4
NC = NO CONNECT
EXPOSED PAD TIED TO SUBSTRATE
IDENTIFIER
1
2
ADG781/ADG782/
3
ADG783
TOP VIEW
4
(Not to Scale)
5
6
78
NC
IN4NCIN3
NC
1617181920
910
NC
15
D2
14
S2
13
V
DD
12
S3
11
D3
GND
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG781/ADG782/ADG783 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Page 5
TERMINOLOGY
VDD = 5V
4 SW
1 SW
FREQUENCY – Hz
10m
1m
1n
100 10M1k
I
SUPPLY
– Amps
10k 100k 1M
100
10
1
100n
10n
ADG781/ADG782/ADG783
V
DD
Most positive power supply potential.
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
∆R
ON
R
FLAT(ON)
Ohmic resistance between D and S.
On-resistance match between any two chan-
nels (i.e., R
max and R
ON
ON
min).
Flatness is defined as the difference between
the maximum and minimum value of on
resistance as measured over the specified
analog signal range.
(OFF) Source leakage current with the switch “OFF.”
I
S
I
(OFF) Drain leakage current with the switch “OFF.”
D
I
, IS (ON) Channel leakage current with the switch “ON.”
D
V
) Analog voltage on terminals D, S.
D (VS
C
(OFF) “OFF” switch source capacitance.
S
CD (OFF) “OFF” switch drain capacitance.
Typical Performance Characteristics
6
TA = 25C
VDD = 4.5V
VDD = 5V
5
–
ON
R
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VDD = 2.7V
VDD = 3V
0 0.5
1 1.5 2 2.5 3 3.5 4 4.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
CD, CS (ON) “ON” switch capacitance.
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
D
“OFF” time or “ON” time measured
between the 90% points of both switches,
when switching from one address state to
another (ADG783 only).
Crosstalk A measure of unwanted signal that is coupled
through from one channel to another as a
result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” switch.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
On Response The frequency response of the “ON” switch.
On Loss The loss due to the on resistance of the switch.
6
5.5
5
4.5
4
3.5
–
3
ON
R
2.5
2
1.5
1
0.5
0
0 0.5
+85C
+25C
–40 C
1 1.5 2 2.5 3 3.5 4 4.5 5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
VDD = 5V
TPC 1. On Resistance as a Function of VD (VS)
6
5.5
5
4.5
4
3.5
–
3
ON
R
2.5
2
1.5
1
0.5
0
0
+85C
–40 C
0.5 1.5 2 2.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
13
VDD = 3V
TPC 2. On Resistance as a Function of VD (VS) for
Different Temperatures V
DD
= 3 V
REV. A
+25C
TPC 3. On Resistance as a Function of VD (VS) for
Different Temperatures V
DD
= 5 V
TPC 4. Supply Current vs. Input Switching Frequency
–5–
Page 6
ADG781/ADG782/ADG783
–30
–40
–50
–60
–70
–80
–90
–100
OFF ISOLATION – dB
–110
–120
–130
10k 100k 1M 10M 100M
TPC 5. Off Isolation vs. Frequency
–30
–40
–50
–60
–70
–80
–90
CROSSTALK – dB
–100
–110
–120
–130
10k 100k 1M 10M
FREQUENCY – Hz
TPC 6. Crosstalk vs. Frequency
VDD = 5V, 3V
FREQUENCY – Hz
VDD = 5V, 3V
100M
0
VDD = 5V
–2
–4
ON RESPONSE – dB
–6
10k 100k 1M 10M
FREQUENCY – Hz
TPC 7. On Response vs. Frequency
25
TA = 25C
20
15
VDD = 5V
– pC
Q
–10
INJ
10
5
0
–5
0 0.5
VDD = 3V
1 1.5 2 2.5 3 3.5 4 4.5 5
SOURCE VOLTAGE – V
TPC 8. Charge Injection vs. Source Voltage
100M
APPLICATIONS
Figure 1 illustrates a photodetector circuit with programmable
gain. An AD820 is used as the output operational amplifier.
With the resistor values shown in the circuit, and using different
combinations of the switches, gain in the range of 2 to 16 can
be achieved.
–6–
C1
R1
33k
5V
AD820
D1
(LSB) IN1
IN2
IN3
(MSB) IN4
2.5V
5V
S1 D1
S2
S3 D3
S4
GND
R4
240kR5240k
R6
120kR7120k
D2
R8
120k
R9
D4
120k
R10
120k
GAIN RANGE 2 TO 16
R2
510k
R3
510k
V
2.5V
OUT
Figure 1. Photodetector Circuit with Programmable Gain
REV. A
Page 7
ADG781/ADG782/ADG783
ID (ON)
SD
A
V
D
NC
NC = NO CONNECT
Test Circuits
I
DS
V1
SD
V
S
RON = V1/ I
DS
Test Circuit 1. On Resistance
V
0.1F
V
S1
V
S2
IN1, IN2
V
IN
S
S1 D1
S2
IN
V
DD
V
DD
D2
ADG783
GND
0.1F
S
V
V
DD
GND
R
300
IS (OFF)
SD
A A
V
S
Test Circuit 2. Off Leakage
DD
D
R
L
300
C
L
35pF
V
OUT
Test Circuit 4. Switching Times
R
L1
V
OUT2
C
L2
L2
35pF
300
C
L1
35pF
I
D
V
(OFF)
V
IN
V
IN
OUT
V
OUT1
V
D
ADG781
ADG782
V
V
50% 50%
50% 50%
V
S
90%
t
ON
V
IN
0V
OUT1
0V
OUT2
0V
Test Circuit 3. On Leakage
90%
t
OFF
50% 50%
t
90%
90%
D
90%
90%
t
D
REV. A
V
Test Circuit 5. Break-Before-Make Time Delay, t
V
DD
V
R
S
V
S
IN
DD
S
D
C
1nF
V
OUT
L
GND
SW ON
V
IN
V
OUT
Q
INJ
D
SW OFF
= CL V
OUT
V
OUT
Test Circuit 6. Charge Injection
V
V
DD
0.1F
V
DD
IN
S
50
D
IN
GND
OFF ISOLATION = 20 LOG
NETWORK
ANALYZER
50
V
V
OUT
R
L
50
S
V
OUT
VS
Test Circuit 7. Off Isolation
–7–
NETWORK
ANALYZER
V
OUT
R
50
L
50
V
S
IN
CHANNEL-TO-CHANNEL
CROSSTALK = 20 LOG
Test Circuit 8. Channel-to-Channel Crosstalk
0.1F
D1
S2
DD
V
DD
S1
NC
D2
R
L
50
GND
V
OUT
V
S
Page 8
ADG781/ADG782/ADG783
0.1F
V
DD
INDICATOR
0.035 (0.90) MAX
0.033 (0.85) NOM
SEATING
PIN 1
PLANE
V
DD
IN
V
IN
S
D
GND
INSERTION LOSS = 20 LOG
Test Circuit 9. Bandwidth
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead CSP
(CP-20)
0.157 (4.0)
BSC SQ
TOP
VIEW
12 MAX
0.020 (0.50)
BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
0.148 (3.75)
BSC SQ
0.028 (0.70) MAX
0.026 (0.65) NOM
0.008 (0.20)
REF
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
NETWORK
ANALYZER
50
V
R
L
50
V
WITH SWITCH
OUT
V
WITHOUT SWITCH
OUT
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
16
15
11
10
0.080 (2.00)
V
S
OUT
0.010 (0.25)
BOTTOM
VIEW
REF
MIN
20
6
1
5
C02372–0–3/02(A)
0.089 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Edits to Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Changes to OUTLINE DIMENSIONS drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. A
PRINTED IN U.S.A.
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