Datasheet ADG733 Datasheet (Analog Devices)

Page 1
CMOS, 2.5  Low Voltage,
a

FEATURES

1.8 V to 5.5 V Single Supply 2.5 V Dual Supply
2.5 On Resistance
0.5 On Resistance Flatness 100 pA Leakage Currents 19 ns Switching Times Triple SPDT: ADG733 Quad SPDT: ADG734 Small TSSOP and QSOP Packages Low Power Consumption TTL/CMOS Compatible Inputs
APPLICATIONS Data Acquisition Systems Communication Systems Relay Replacement Audio and Video Switching Battery Powered Systems
S1B
S1A
S2A
S2B
Triple/Quad SPDT Switches
ADG733/ADG734

FUNCTIONAL BLOCK DIAGRAMS

ADG733
D1
D2
LOGIC
A2
A0
A1
EN
SWITCHES SHOWN FOR A “1” INPUT LOGIC
S3A
D3
S3B
S1A
S1B
IN1
IN2
S2B
S2A
S4A
D1
ADG734
D2
D2
S4B
IN4
IN3
S3B
D3
S3A

GENERAL DESCRIPTION

The ADG733 and ADG734 are low voltage, CMOS devices comprising three independently selectable SPDT (single pole, double throw) switches and four independently selectable SPDT switches respectively.
Low power consumption and operating supply range of 1.8 V to
5.5 V and dual ±2.5 V make the ADG733 and ADG734 ideal for battery powered, portable instruments. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. An EN input on the ADG733 is used to enable or disable the device. When disabled, all channels are switched OFF.
These 2–1 multiplexers/SPDT switches are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, high signal bandwidths, and low leakage currents. On resistance is in the region of a few ohms, is closely matched between switches, and is very flat over the full signal range. These parts can operate equally well in either direction and have an input signal range that extends to the supplies.
The ADG733 is available in small TSSOP and QSOP packages, while the ADG734 is available in a small TSSOP package.

PRODUCT HIGHLIGHTS

1. Single/Dual Supply Operation. The ADG733 and ADG734 are fully specified and guaranteed with 3 V and 5 V single supply rails and ±2.5 V dual supply rails.
2. Low On Resistance (2.5 Ω typical)
3. Low Power Consumption (<0.01 µW)
4. Guaranteed Break-Before-Make Switching Action
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
Page 2
1
ADG733/ADG734–SPECIFICATIONS
(VDD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40C
Parameter +25C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V On Resistance (R
) 2.5 typ VS = 0 V to VDD, IDS = 10 mA;
ON
DD
V
4.5 5.0 Ω max Test Circuit 1
On Resistance Match between 0.1 Ω typ V
Channels (∆R
On Resistance Flatness (R
) 0.4 max
ON
FLAT(ON)
) 0.5 typ VS = 0 V to VDD, IDS = 10 mA
= 0 V to VDD, IDS = 10 mA
S
1.2 Ω max
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;
S
= 5.5 V
DD
± 0.1 ± 0.3 nA max Test Circuit 2
Channel ON Leakage I
, IS (ON) ±0.01 nA typ VD = VS = 1 V, or 4.5 V;
D
± 0.1 ± 0.5 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
ADG733 t
(EN)20 ns typ RL = 300 , CL = 35 pF;
ON
t
(EN)7 ns typ RL = 300 , CL = 35 pF;
OFF
Break-Before-Make Time Delay, t
Charge Injection ± 3pC typ V
2
19 ns typ RL = 300 , CL = 35 pF;
34 ns max V
= 3 V, Test Circuit 4
S
7 ns typ RL = 300 , CL = 35 pF;
12 ns max V
40 ns max V
12 ns max V
D
13 ns typ RL = 300 , CL = 35 pF;
1 ns min V
= 3 V, Test Circuit 4
S
= 3 V, Test Circuit 5
S
= 3 V, Test Circuit 5
S
= 3 V, Test Circuit 6
S
= 2 V, RS = 0 , CL = 1 nF;
S
Test Circuit 7
Off Isolation –72 dB typ R
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 8
Channel-to-Channel Crosstalk –67 dB typ R
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 9
–3 dB Bandwidth 160 MHz typ R
(OFF) 11 pF typ f = 1 MHz
C
S
= 50 , CL = 5 pF, Test Circuit 10
L
CD, CS (ON) 34 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
0.001 µA typ Digital Inputs = 0 V or 5.5 V
= 5.5 V
DD
1.0 µA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
Page 3
1
ADG733/ADG734
SPECIFICATIONS
Parameter +25C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V On Resistance (R
On Resistance Match between 0.1 Ω typ V
Channels (∆R
On Resistance Flatness (R
LEAKAGE CURRENTS V
Source OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current
or I
I
INL
INH
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
ADG733 t
t
ON
OFF
Break-Before-Make Time Delay, t
Charge Injection ± 3pC typ V
Off Isolation –72 dB typ R
Channel-to-Channel Crosstalk –67 dB typ R
–3 dB Bandwidth 160 MHz typ R
(OFF) 11 pF typ f = 1 MHz
C
S
CD, CS (ON) 34 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
)6 Ω typ VS = 0 V to VDD, IDS = 10 mA;
ON
) 0.4 max
ON
(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;
S
, IS (ON) ±0.01 nA typ VS = VD = 1 V or 3 V;
D
INH
INL
(EN)29 ns typ RL = 300 , CL = 35 pF;
(EN)9 ns typ RL = 300 , CL = 35 pF;
(VDD = 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40C
V
DD
11 12 Ω max Test Circuit 1
FLAT(ON)
)3Ω typ VS = 0 V to VDD, IDS = 10 mA
± 0.1 ± 0.3 nA max Test Circuit 2
± 0.1 ± 0.5 nA max Test Circuit 3
2.0 V min
0.8 V max
0.005 µA typ VIN = V ± 0.1 µA max
2
28 ns typ RL = 300 , CL = 35 pF;
55 ns max V
9 ns typ RL = 300 , CL = 35 pF;
16 ns max V
60 ns max V
16 ns max V
D
22 ns typ RL = 300 , CL = 35 pF;
1 ns min V
0.001 µA typ Digital Inputs = 0 V or 3.3 V
1.0 µA max
= 0 V to VDD, IDS = 10 mA
S
= 3.3 V
DD
or V
INL
= 2 V, Test Circuit 4
S
= 2 V, Test Circuit 4
S
= 2 V, Test Circuit 5
S
= 2 V, Test Circuit 5
S
= 2 V, Test Circuit 6
S
= 1 V, RS = 0 , CL = 1 nF;
S
INH
Test Circuit 7
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 8
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 9
= 50 , CL = 5 pF, Test Circuit 10
L
= 3.3 V
DD
REV. A
–3–
Page 4
ADG733/ADG734–SPECIFICATIONS
1
DUAL SUPPLY
(VDD = +2.5 V 10%, VSS = –2.5 V 10%, GND = 0 V, unless otherwise noted.)
B Version
–40C
Parameter +25C to +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V On Resistance (R
) 2.5 typ VS = VSS to VDD, IDS = 10 mA;
ON
SS
to V
DD
V
4.5 5.0 Ω max Test Circuit 1
On Resistance Match between 0.1 Ω typ V
Channels (∆R
On Resistance Flatness (R
) 0.4 max
ON
FLAT(ON)
) 0.5 typ VS = VSS to VDD, IDS = 10 mA
= VSS to VDD, IDS = 10 mA
S
1.2 Ω max
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ± 0.01 nA typ
S
= +2.75 V, VSS = –2.75 V
DD
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
± 0.1 ± 0.3 nA max Test Circuit 2
Channel ON Leakage I
, IS (ON) ±0.01 nA typ
D
VS = VD = +2.25 V/–1.25 V, Test Circuit 3
± 0.1 ± 0.5 nA max
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V
INL
INH
1.7 V min
0.7 V max
Input Current
I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
ADG733 t
(EN)21 ns typ RL = 300 , CL = 35 pF;
ON
t
(EN)10 ns typ RL = 300 , CL = 35 pF;
OFF
Break-Before-Make Time Delay, t
Charge Injection ± 5pC typ V
2
21 ns typ RL = 300 , CL = 35 pF;
35 ns max V
= 1.5 V, Test Circuit 4
S
10 ns typ RL = 300 , CL = 35 pF;
16 ns max V
40 ns max V
16 ns max V
D
13 ns typ RL = 300 , CL = 35 pF;
1 ns min V
= 1.5 V, Test Circuit 4
S
= 1.5 V, Test Circuit 5
S
= 1.5 V, Test Circuit 5
S
= 1.5 V, Test Circuit 6
S
= 0 V, RS = 0 , CL = 1 nF;
S
Test Circuit 7
Off Isolation –72 dB typ R
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 8
Channel-to-Channel Crosstalk –67 dB typ R
= 50 , CL = 5 pF, f = 1 MHz;
L
Test Circuit 9
–3 dB Bandwidth 200 MHz typ R
(OFF) 11 pF typ f = 1 MHz
C
S
= 50 , CL = 5 pF, Test Circuit 10
L
CD, CS (ON) 34 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
0.001 µA typ Digital Inputs = 0 V or 2.75 V
= 2.75 V
DD
1.0 µA max
I
SS
0.001 µA typ VSS = –2.75 V
1.0 µA max Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. A
Page 5
ADG733/ADG734

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
V
SS
Analog Inputs
Digital Inputs
2
. . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
2
. . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
1
30 mA, Whichever Occurs First
30 mA, Whichever Occurs First
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
16-Lead TSSOP, θ 20-Lead TSSOP, θ 16-Lead QSOP, θ
Thermal Impedance . . . . . . . 150.4°C/W
JA
Thermal Impedance . . . . . . . . . 143°C/W
JA
Thermal Impedance . . . . . . . 149.97°C/W
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
2
Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

ORDERING GUIDE

Model Temperature Range Package Description Package Option
ADG733BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-16 ADG733BRQ –40°C to +85°CQuarter Size Outline Package (QSOP) RQ-16 ADG734BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG733/ADG734 feature proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

TSSOP/QSOP TSSOP
IN1
1
S2B
S2A
S3B
S3A
V
GND
D3
EN
SS
1
2
3
ADG733
TOP VIEW
4
(Not to Scale)
5
6
7
8
16
V
DD
15
D2
D1
14
13
S1B
S1A
12
11
A0
10
A1
A2
9
2
S1A
3
D1
4
S1B
V
5
SS
6
GND
7
S2B
D2
8
9
S2A
IN2
10
NC = NO CONNECT
ADG734
TOP VIEW
(Not to Scale)
IN4
20
19
S4A
D4
18
17
S4B
V
16
DD
15
NC
14
S3B
13
D3
12
S3A
11
IN3
REV. A
–5–
Page 6
ADG733/ADG734
Table I. ADG733 Truth Table
A2 A1 A0 EN ON Switch
XXX1 None 0000D1-S1A, D2-S2A, D3-S3A
Table II. ADG734 Truth Table
Logic Switch A Switch B
0 OFF ON
1ONOFF 0010D1-S1B, D2-S2A, D3-S3A 0100D1-S1A, D2-S2B, D3-S3A 0110D1-S1B, D2-S2B, D3-S3A 1000D1-S1A, D2-S2A, D3-S3B 1010D1-S1B, D2-S2A, D3-S3B 1100D1-S1A, D2-S2B, D3-S3B 1110D1-S1B, D2-S2B, D3-S3B
X = Don’t Care.

TERMINOLOGY

V
DD
V
SS
Most Positive Power Supply Potential Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
I
DD
I
SS
Positive Supply Current
Negative Supply Current GND Ground (0 V) Reference S Source Terminal. May be an input or output. DDrain Terminal. May be an input or output. A
X
Logic Control Input EN Active low device enable V
(VS)Analog Voltage on Terminals D and S
D
R
ON
R
ON
R
FLAT(ON)
Ohmic Resistance between D and S
On Resistance Match between any Two Channels (i.e., RONmax and RONmin)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over
the specified analog signal range. I
(OFF) Source Leakage Current with the Switch “OFF”
S
I
, IS (ON) Channel Leakage Current with the Switch “ON”
D
V
INL
V
INH
I
INL(IINH
C C C t
ON
t
OFF
t
ON
t
OFF
t
OPEN
) Input Current of the Digital Input
(OFF) “OFF” Switch Source Capacitance. Measured with reference to ground.
S
, CS(ON) “ON” Switch Capacitance. Measured with reference to ground.
D
IN
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Digital Input Capacitance
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition
Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition
“OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to
Another Charge A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching Off Isolation A Measure of Unwanted Signal Coupling through an “OFF” Switch. Crosstalk A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para-
sitic Capacitance On Response The Frequency Response of the “ON” Switch Insertion Loss The Loss Due to the On Resistance of the switch
–6–
REV. A
Page 7
Typical Performance Characteristics–ADG733/ADG734
TEMPERATURE – C
0.25
5
CURRENT – nA
V
DD
= +2.5V
V
SS
= –2.5V
V
D
= +2.25V/–1.25V
V
S
= –1.25V/+2.25V
V
DD
= 5V
V
SS
= GND
V
D
= 4.5V/1.0V
V
S
= 1.0V/4.5V
IS, ID (ON)
IS (OFF)
0.20
0.15
0.10
0.05
0
–0.05
20 35 50 65 80
–0.10
8
7
6
5
4
3
ON RESISTANCE –
2
1
0
01234
VD, VS, DRAIN OR SOURCE VOLTAGE – V
VDD = 2.7V
VDD = 3.3V
TA = 25C V
VDD = 4.5V
VDD = 5.5V
= 0V
SS
5
TPC 1. On Resistance as a Function of VD (VS) for Single Supply
8
7
6
5
4
3
ON RESISTANCE –
2
1
0
0 0.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
–40C
1.0 1.5 2.0 2.5 3.0
+85C
+25C
VDD = 3V
= 0V
V
SS
TPC 4. On Resistance as a Function of
(VS) for Different Temperatures,
V
D
Single Supply
8
7
6
5
4
3
ON RESISTANCE –
2
1
0
–3 –2 –1 0 2
VD, VS, DRAIN OR SOURCE VOLTAGE – V
VDD = +2.5V
= –2.5V
V
SS
1
TA = 25C
3
TPC 2. On Resistance as a Function of VD (VS) for Dual Supply
8
7
6
5
4
+85C
3
ON RESISTANCE –
2
–40C
1
0
–3 –2 –1 0 2
VD, VS, DRAIN OR SOURCE VOLTAGE – V
VDD = +2.5V
= –2.5V
V
SS
+25C
1
3
TPC 5. On Resistance as a Function of
(VS) for Different Temperatures,
V
D
Dual Supply
8
7
6
5
4
+85C
3
ON RESISTANCE –
2
–40C
1
0
1
02
VD, OR VS DRAIN OR SOURCE VOLTAGE – V
+25C
3
VDD = 5V
= 0V
V
SS
45
TPC 3. On Resistance as a Function of
(VS) for Different Temperatures,
V
D
Single Supply
0.1
0.05
IS, ID (ON)
0
–0.05
CURRENT – nA
–0.1
–0.15
0123 5
V
S
IS (OFF)
,
(V
D
=
V
DD
VS) – V
VDD = 5V
= GND
V
SS
= 25C
T
A
4
TPC 6. Leakage Currents as a Function of V
(VS)
D
0.10
0.08
0.06
0.04
0 0.5
IS, ID (ON)
IS (OFF)
1.0 1.5 2.0 2.5 3.0
,
V
(V
S
D
0.02
0
–0.02
CURRENT – nA
–0.04
–0.06
–0.08
–0.10
TPC 7. Leakage Currents as a Function of VD (VS)
REV. A
VDD = 3V
= GND
V
SS
= 25C
T
A
=
V
VS) – V
DD
0.15
0.10
0.05
0
CURRENT – nA
–0.05
–0.10
–0.15
–3 –2
IS, ID (ON), VD = V
IS (OFF)
–1 0123
VS, (VD = VDD –VS) – V
TPC 8. Leakage Currents as a Function of V
(VS)
D
VDD = +2.5V
= –2.5V
V
SS
= 25C
T
A
S
TPC 9. Leakage Currents as a Function of Temperature
–7–
Page 8
ADG733/ADG734
0.25
0.20
0.15
0.10
0.05
CURRENT – nA
–0.05
–0.10
IS, ID (ON)
0
5
IS (OFF)
20 35 50 65 80
TEMPERATURE – C
VDD = 3V
= GND
V
SS
= 2.7V/1V
V
D
= 1V/2.7V
V
S
TPC 10. Leakage Currents as a Function of Temperature
10m
1m
100
10
CURRENT – A
1
100n
VDD = +2.5V
= –2.5V
V
SS
VSS = 3V V
VDD = 5V
= GND
V
SS
= GND
DD
TA = 25C
40
35
30
25
20
TIME – ns
15
10
5
0
–20
TPC 11. tON/t Temperature
0
–20
–40
–60
–80
ATTENUATION – dB
–100
VSS = GND
tON, VDD = 3V
tON, VDD = 5V
t
, VDD = 3V
OFF
t
, VDD = 5V
OFF
020406080
TEMPERATURE – C
Times vs.
OFF
VDD = 5V
= 25C
T
A
0
–2
VDD = 5V
–4
T
= 25C
A
–6
–8
–10
ON RESPONSE dB
–12
–14
–16
100k 1M 100M
FREQUENCY HZ
10M10k
TPC 12. On Response vs. Frequency
0
–20
–40
–60
–80
ATTENUATION – dB
–100
VDD = 5V
= 25C
T
A
10n
0.1
110100 1000 10000
FREQUENCY – kHz
TPC 13. Input Current, IDD vs. Switching Frequency
30
20
– pC
10
INJ
Q
–10
0
–3 –2
VDD = +2.5V
= –2.5V
V
SS
VDD = 3V
= GND
V
SS
–1 0 1 2 3
VOLTAGE – V
TA = 25C
VDD = 5V
= GND
V
SS
45
TPC 16. Charge Injection vs. Source Voltage
–120
30k
100k 1M 10M 100M
FREQUENCY – kHz
TPC 14. Off Isolation vs. Frequency
–120
30k
100k 1M 10M 100M
FREQUENCY – kHz
TPC 15. Crosstalk vs. Frequency
–8–
REV. A
Page 9

Test Circuits

ADG733/ADG734
I
DS
V1
SD
V
S
RON = V1/ I
DS
Test Circuit 1. On Resistance
0.1F
VS1B
VS1A
IN/EN
V
DD
0.1F
V
DD
A2
A1
A0
ADG733
EN
V
50
IN
GND
IS (OFF)
SD
A
V
S
Test Circuit 2. IS (OFF)
V
DD
V
DD
S1B
S1A
GND
0.1F
D1
R
L
300
V
SS
V
SS
C
L
35pF
V
OUT
Test Circuit 4. Switching Times, tON, t
V
SS
V
SS
S1A
S1B
V
S
D1
R
L
300
C
L
35pF
V
O
ENABLE
DRIVE (V
OUTPUT
Test Circuit 5. Enable Delay, tON (EN), t
ADDRESS DRIVE
VS1A
V
OUT
VS1B
3V
)
IN
0V
V
O
0V
V
D
50% 50%
t
ON
OFF
50%
(EN)
OFF
90%
SD
NC
Test Circuit 3. ID (ON)
90%
t
OFF
50%
0.9V
0
(EN)
t
ON
0.9V
ID (ON)
A
V
D
t
(EN)
OFF
0
REV. A
V
DD
0.1F
V
DD
0.1F
SA
SB
D1
R
V
SS
300
V
SS
V
IN
ADDRESS*
50
ADG733/ ADG734
GND
*A0, A1, A2 FOR ADG733, IN1-4 FOR ADG734
V
S
V
OUT
C
L
L
35pF
Test Circuit 6. Break-Before-Make Delay, t
ADDRESS
V
OUT
3V
0V
V
S
80%
t
80%
OPEN
OPEN
–9–
Page 10
ADG733/ADG734
R
S
V
S
V
IN
*
IN1–4 FOR ADG734
S
EN
V
DD
V
DD
*
ADG733/
ADG734
GND
V
SS
V
SS
INPUT (V
D
C 1nF
V
OUT
L
Test Circuit 7. Charge Injection
LOGIC
V
IN
OUT
3V
)
0V
V
Q
INJ
= CL V
OUT
OUT
V
NETWORK
ANALYZER
V
OUT
IN
0.1F
IN
50
V
V
DD
SS
0.1F
V
V
SS
DD
S
50
D
GND
Test Circuit 8. Off Isolation
0.1F
R
L
50
V
S
IN
NETWORK
ANALYZER
50
V
V
OUT
R
L
50
OFF ISOLATION = 20 LOG
V
V
DD
SS
0.1F
V
V
SS
DD
SA
SB
D
GND
CHANNEL-TO-CHANNEL
CROSSTALK = 20
S
R 50
V
V
DD
0.1F
IN
V
IN
V
OUT
V
S
SS
0.1F
V
V
DD
SS
S
D
GND
INSERTION LOSS = 20 LOG
NETWORK
ANALYZER
50
V
OUT
R
L
50
V
WITH SWITCH
OUT
WITHOUT SWITCH
V
OUT
V
S
Test Circuit 10. Bandwidth
V
OUT
LOG
V
S
Test Circuit 9. Channel-to-Channel Crosstalk
–10–
REV. A
Page 11

OUTLINE DIMENSIONS

ADG733/ADG734
16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
0.15
0.05
4.50
4.40
4.30
PIN 1
16
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AB
0.10
0.30
0.19
9
81
1.20 MAX
6.40 BSC
SEATING
PLANE
0.20
0.09
0.75
8 0
0.60
0.45
16-Lead SOIC, 0.025 Lead Pitch [QSOP]
Dimensions shown in inches
COPLANARITY
(RQ-16)
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
0.15
0.05
PIN 1
0.10
20
1
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AC
0.65 BSC
11
10
1.20
MAX
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8
0
0.75
0.60
0.45
0.154 BSC
0.065
0.049
0.010
0.004 COPLANARITY
0.004
0.197
0.189
0.012
0.008
9
8
0.236 BSC
0.069
0.053
SEATING PLANE
0.010
0.006
16
1
PIN 1
0.025 BSC
COMPLIANT TO JEDEC STANDARDS MO-137AB
8 0
0.050
0.016
REV. A
–11–
Page 12
ADG733/ADG734

Revision History

Location Page
11/02—Data Sheet changed from REV. 0 to REV. A.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS Note 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TERMINOLOGY table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Replaced TPCs 2, 5, 8, and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to TPCs 6 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Replaced TPC 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to TPCs 13 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Replaced Test Circuits 8 and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Added Test Circuit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C01602–0–11/02(A)
–12–
PRINTED IN U.S.A.
REV. A
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