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ADG732BSU
Datasheet (Analog Devices)
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Datasheet ADG732BSU, ADG732BCP, ADG726BSU, ADG726BCP Datasheet (Analog Devices)

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PRELIMINARY TECHNICAL DA T A
=
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
Preliminary Technical Data

FEATURES

1.8 V to 5.5 V Single Supply ±2.5 V Dual Supply Operation
ΩΩ
3.5
Ω On Resistance
ΩΩ ΩΩ
0.5
Ω On Resistance Flatness
ΩΩ
Rail to Rail Operation 30ns Switching Times Single 32 to 1 Channel Multiplexer Dual/Differential 16 to 1 Channel Multiplexer TTL/CMOS Compatible Inputs For Functionally Equivalent devices with Serial Interface
See ADG725/ADG731
APPLICATIONS Optical Applications Data Acquisition Systems Communication Systems Relay replacement Audio and Video Switching Battery Powered Systems Medical Instrumentation Automatic Test Equipment
S32
WR
CS
16-/32- Channel, 3.5
ΩΩ
Ω
ΩΩ
ADG726/ADG732
FUNCTIONAL BLOCK DIAGRAMS
ADG732
S1
1 OF 32
DECODER
EN
A2 A4
A0
A3
A1
S1A
S16A
D
S1B
S16B
WR
CSA
CSB
ADG726
A1
A0
1 OF 16
DECODER
A2
DA
DB
A3
EN
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic CMOS 32 channel/dual 16 channel analog multiplexers. The ADG732 switches one of thirty-two inputs (S1-S32) to a common output, D, as determined by the 5-bit binary address lines A0, A1, A2, A3 and A4. The ADG726 switches one of sixteen inputs as determined by the four bit binary address lines, A0, A1, A2 and A3.
On chip latches facilitate microprocessor interfacing. The ADG726 device may also be configured for differential operation by tying CSA and CSB together. An EN input is used to enable or disable the devices. When disabled, all channels are switched OFF.
These multiplexers are designed on an enhanced submi­cron process that provides low power dissipation yet gives high switching speed, very low on resistance and leakage currents. They operate from single supply of 1.8V to 5.5V and ±2.5 V dual supply, making them ideally suited to a variety of applications. On resistance is in the region of a few Ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either Multiplexers or De-Multiplexers
and have an input signal range which extends to the sup­plies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break before make switching action preventing momentary shorting when switching channels.
They are available in either 48 lead LFCSP or TQFP package.

PRODUCT HIGHLIGHTS

1. +1.8 V to +5.5 V Single or ±2.5 V Dual Supply operation. These parts are specified and guaranteed with +5 V ±10%, +3 V ±10% single supply and ±2.5 V ±10% dual supply rails.
2. On Resistance of 3.5 Ω.
3. Guaranteed Break-Before-Make Switching Action.
4. 7mm x 7mm 48 lead LF Chip Scale Package (CSP) or 48 lead TQFP package.
REV. PrD 2001
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DA T A
1
ADG726/ADG732–SPECIFICATIONS
B Version
–40°C
Parameter +25oC to +85°C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V On-Resistance (R
On-Resistance Match Between 0.3 Ω typ V Channels (∆R On-Resistance Flatness (R
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current
or I
I
INL
INH
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
t
TRANSITION
Break-Before-Make Time Delay, t
t
(EN, WR) 32 ns typ R
ON
(EN) 10 ns typ R
t
OFF
Charge Injection ±5 pC typ V
Off Isolation -60 dB typ R
Channel to Channel Crosstalk -60 dB typ R
-3 dB Bandwidth 10 MHz typ R (OFF) 13 pF typ f = 1 MHz
C
S
C
(OFF)
D
ADG726 180 pF typ f = 1 MHz ADG732 360 pF typ f = 1 MHz
, CS (ON)
C
D
ADG726 200 pF typ f = 1 MHz ADG732 400 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
) 3.5 Ω typ V
ON
5.5 6 Ω max Test Circuit 1
) 0.8 Ω max
ON
FLAT(ON)
) 0.5 Ω typ V
1.2 Ω max
(OFF) ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;
S
±0.5 ±5 nA max Test Circuit 2
(OFF) ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;
D
±0.5 ±5 nA max Test Circuit 3
, IS (ON) ±0.01 nA typ VD = VS = 1 V, or 4.5V;
D
±1 ±10 nA max Test Circuit 4
INH
INL
2.4 V min
0.8 V max
0.005 µA typ VIN = V ±0.1 µA max
2
40 ns typ R
60 ns max V
30 ns typ R
D
1 ns min V
50 ns max V
14 ns max V
10 µA typ Digital Inputs = 0 V or +5.5 V
20 µA max
(VDD = 5V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
V
DD
= 0 V to VDD, IDS = 10 mA;
S
= 0 V to V
S
= 0 V to VDD, IDS = 10 mA
S
= 5.5 V
DD
INL
= 300 Ω, C
L
= 3 V/0 V, V
S1
= 300 Ω, C
L
= 3 V, Test Circuit 6
S
= 300 Ω, C
L
= 3 V, Test Circuit 7
S
= 300 Ω, C
L
= 3 V, Test Circuit 8
S
= 0 V, R
S
, IDS = 10 mA
DD
or V
INH
= 35 pF,Test Circuit 5;
L
= 0 V/3V
S32
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 1 nF;
L
Test Circuit 9
= 50 Ω, C
L
= 5 pF, f = 100 kHz;
L
Test Circuit 10
= 50 Ω, C
L
= 5 pF, f = 100 kHz;
L
Test Circuit 11
= 50 Ω, C
L
= +5.5 V
DD
= 5 pF, Test Circuit 10
L
–2– REV. PrD
PRELIMINARY TECHNICAL DA T A
ADG726/ADG732
1
SPECIFICATIONS
Parameter +25oC to +85°C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V On-Resistance (R
On-Resistance Match Between 0.4 Ω typ V Channels (∆R On-Resistance Flatness (R
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current
or I
I
INL
INH
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
t
TRANSITION
Break-Before-Make Time Delay, t
t
(EN, WR) 40 ns typ R
ON
t
(EN) 20 ns typ R
OFF
Charge Injection ±5 pC typ V
Off Isolation -60 dB typ R
Channel to Channel Crosstalk -60 dB typ R
-3 dB Bandwidth 10 MHz typ R C
(OFF) 13 pF typ f = 1 MHz
S
C
(OFF)
D
ADG726 180 pF typ f = 1 MHz ADG732 360 pF typ f = 1 MHz
, CS (ON)
C
D
ADG726 200 pF typ f = 1 MHz ADG732 400 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
)6 Ω typ V
ON
) 1.2 Ω max
ON
D
D
INH
INL
(VDD = 3V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
B Version
–40°C
V
DD
= 0 V to VDD, IDS = 10 mA;
S
11 12 Ω max Test Circuit 1
= 0 V to V
S
FLAT(ON)
(OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;
S
)3Ω max V
= 0 V to VDD, IDS = 10 mA
S
= 3.3 V
DD
, IDS = 10 mA
DD
±1 ±5 nA max Test Circuit 2
(OFF) ±0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V;
±1 ±5 nA max Test Circuit 3
, IS (ON) ±0.01 nA typ VS = VD = +1 V or +3 V;
±1 ±10 nA max Test Circuit 4
2.0 V min
0.8 V max
0.005 µA typ VIN = V
INL
or V
INH
±0.1 µA max
2
45 ns typ R
75 ns max V
30 ns typ R
D
1 ns min V
70 ns max V
28 ns max V
= 300 Ω, C
L
= 2 V/0 V, V
S1
= 300 Ω, C
L
= 2 V, Test Circuit 6
S
= 300 Ω, C
L
= 2 V, Test Circuit 7
S
= 300 Ω, C
L
= 2 V, Test Circuit 8
S
= 0 V, R
S
= 35 pF Test Circuit 5
L
= 0 V/2 V
S32
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 1 nF;
L
Test Circuit 9
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 10
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 11
= 50 Ω, C
L
= +3.3 V
DD
= 5 pF, Test Circuit 10
L
10 µA typ Digital Inputs = 0 V or +3.3 V
20 µA max
–3–REV. PrD
PRELIMINARY TECHNICAL DA T A
1
ADG726/ADG732–SPECIFICATIONS
(VDD = +2.5 V ±10%, VSS = -2.5 V ±10%, GND = 0 V, unless otherwise noted)
B Version
–40°C
Parameter +25oC to +85°C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to V On-Resistance (R
On-Resistance Match Between 0.3 Ω typ V Channels (∆R On-Resistance Flatness (R
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V Input Low Voltage, V Input Current
or I
I
INL
INH
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
t
TRANSITION
Break-Before-Make Time Delay, t
t
(EN, WR) 32 ns typ R
ON
(EN) 16 ns typ R
t
OFF
Charge Injection ±8 pC typ V Off Isolation -60 dB typ R
Channel to Channel Crosstalk -60 dB typ R
-3 dB Bandwidth 10 MHz typ R C
(OFF) 13 pF typ
S
(OFF)
C
D
ADG726 180 pF typ f = 1 MHz ADG732 360 pF typ f = 1 MHz
, CS (ON)
C
D
ADG726 200 pF typ f = 1 MHz ADG732 400 pF typ f = 1 MHz
POWER REQUIREMENTS V
I
DD
I
SS
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
) 3.5 Ω typ V
ON
5.5 6 Ω max Test Circuit 1
) 0.8 Ω max
ON
FLAT(ON)
) 0.5 Ω typ V
1.2 Ω max
(OFF) ±0.01 nA typ
S
±1 ±5 nA max Test Circuit 2
(OFF) ±0.01 nA typ
D
±1 ±5 nA max Test Circuit 3
, IS (ON) ±0.01 nA typ
D
±1 ±10 nA max
INH
INL
1.7 V min
0.7 V max
0.005 µA typ VIN = V ±0.1 µA max
2
40 ns typ R
60 ns max V
15 ns typ R
D
1 ns min V
50 ns max V
26 ns max V
10 µA typ Digital Inputs = 0 V or +2.75 V
20 µA max
10 µA typ VSS = -2.75 V
20 µA max Digital Inputs = 0 V or +2.75 V
Dual Supply
DD
V
= VSS to VDD, IDS = 10 mA;
S
= VSS to VDD, IDS = 10 mA
S
= VSS to VDD, IDS = 10 mA
S
= +2.75 V, VSS = -2.75 V
DD
VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;
VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;
VS = VD = +2.25 V/-1.25 V, Test Circuit 4
or V
INL
= 300 Ω, C
L
= 1.5 V/0 V,V
S1
= 300 Ω, C
L
= 1.5 V, Test Circuit 6
S
= 300 Ω, C
L
= 1.5 V, Test Circuit 7
S
= 300 Ω, C
L
= 1.5 V, Test Circuit 8
S
= 0 V, R
S
= 50 Ω, C
L
INH
= 35 pF Test Circuit 5
L
= 0 V/1.5 V
S32
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 5 pF, f = 1 MHz;
L
= 1 nF; Test 9
L
Test Circuit 10
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 11
= 50 Ω, C
L
= +2.75 V
DD
= 5 pF, Test Circuit 10
L
–4– REV. PrD
PRELIMINARY TECHNICAL DA T A
ADG726/ADG732

TIMING CHARACTERISTICS

Parameter Limit at T
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
See Figure 1.
2
All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3
Guaranteed by design and characterisation, not production tested.
Specifications subject to change without notice.
0 ns min CS to WR Setup Time 0 ns min CS to WR Hold Time 20 ns min WR pulse width 10 ns min Time between WR cycles 5 ns min Address, Enable Setup Time 2 ns min Address, Enable Hold Time
MIN
1,2, 3
, T
MAX
CS
WR
A0, A1, A2, A3, (A4)
EN
Units Conditions/Comments
t
1
t
3
t
5
t
2
t
4
t
6
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. The ADG726 has two CS inputs. This enables the part to be used either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie CSA and CSB together.
–5–REV. PrD
ADG726/ADG732
PRELIMINARY TECHNICAL DA T A

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)
VDD to V V
DD
V
SS
Analog Inputs
Digital Inputs
SS
to GND –0.3 V to +7 V
to GND +0.3 V to -7 V
2
2
30 mA, Whichever Occurs First
30 mA, Whichever Occurs First
Peak Current, S or D 60mA
(Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, S or D 30mA Operating Temperature Range
Industrial (B Version) –40°C to +85°C
1
+7 V
VSS - 0.3 V to VDD +0.3 Vor
-0.3V to VDD +0.3 V or
Storage Temperature Range –65°C to +150°C Junction Temperature +150°C 48 lead CSP θ 48 lead TQFP θ
Thermal Impedance TBD°C/W
JA
Thermal Impedance TBD°C/W
JA
Lead Temperature, Soldering (10seconds) 300°C IR Reflow, Peak Temperature +220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
2
Overvoltages at A, WR, RS, S or D will be clamped by internal diodes. Current should
be limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option
ADG726BCP -40 ADG726BSU -40 ADG732BCP -40
o
C to +85 oC Chip Scale Package (CSP) CP-48
o
C to +85 oC Thin Quad Flatpack SU-48
o
C to +85 oC Chip Scale Package (CSP) CP-48
ADG732BSU -40 oC to +85 oC Thin Quad Flatpack SU-48
PIN CONFIGURATIONS
CSP & TQFP
40 S16B
39 S15B
38 S14B
41 DB
37 S13B
36 S12B 35 S11B 34 S10B 33 S9B 32 S8B 31 S7B 30 S6B 29 S5B 28 S4B 27 S3B 26 S2B 25 S1B
S12
S11
S10
48 S13A
47 S14A
46 S15A
45 S16A
44 NC
43 DA
40 S32
39 S31
38 S30
48 S13
47 S14
46 S15
45 S16
44 NC
43 D
42 NC
1 2 3
S9
4
S8
5
S7
6
S6
7
S5
8
S4
9
S3
10 11
S2 S1
12
PIN 1 INDICATOR
ADG732
TOP VIEW
41 NC
37 S29
36 S28 35 S27 34 S26 33 S25 32 S24 31 S23 30 S22 29 S21 28 S20 27 S19 26 S18 25 S17
S12A S11A S10A
S9A S8A S7A S6A S5A S4A S3A S2A S1A
1 2 3 4 5 6 7 8
9 10 11 12
PIN 1 INDICATOR
42 NC
ADG726
TOP VIEW
NC = NO CONNECT
13
DD
V
14 V
DD
A0 15
A1 16
A3 18
A2 17
A4 19
CS 20
EN 22
WR 21
24
SS
V
GND 23
NC = NO CONNECT
13 V
DD
14 V
DD
A0 15
A1 16
A3 18
A2 17
CSA 19
CSB 20
EN 22
WR 21
24
SS
V
GND 23
–6– REV. PrD
PRELIMINARY TECHNICAL DA T A
Table 1. ADG726 Truth Table
A3 A2 A1 A0 E N CSA CSB W R ON Switch
X X X X X 1 1 L->H Retains previous switch condition X X X X X 1 1 X No Change in Switch condition X X X X 1 0 0 0 NONE 0 0 0 0 0 0 0 0 S1A - DA, S1B - DB 0 0 0 1 0 0 0 0 S2A - DA, S2B - DB 0 0 1 0 0 0 0 0 S3A - DA, S3B - DB 0 0 1 1 0 0 0 0 S4A - DA, S4B - DB 0 1 0 0 0 0 0 0 S5A - DA, S5B - DB 0 1 0 1 0 0 0 0 S6A - DA, S6B - DB 0 1 1 0 0 0 0 0 S7A - DA, S7B - DB 0 1 1 1 0 0 0 0 S8A - DA, S8B - DB 1 0 0 0 0 0 0 0 S9A - DA, S9B - DB 1 0 0 1 0 0 0 0 S10A - DA, S10B - DB 1 0 1 0 0 0 0 0 S11A - DA, S11B - DB 1 0 1 1 0 0 0 0 S12A - DA, S12B - DB 1 1 0 0 0 0 0 0 S13A - DA, S13B - DB 1 1 0 1 0 0 0 0 S14A - DA, S14B - DB 1 1 1 0 0 0 0 0 S15A - DA, S15B - DB 1 1 1 1 0 0 0 0 S16A - DA, S16B - DB
ADG726/ADG732
Table 2. ADG732 Truth Table
A4 A3 A2 A1 A0 EN CS WR Switch Condition
X X XXXX1 L->H Retains previous switch condition X X XXXX1 X No Change in Switch Condition X X X X X 1 0 0 NONE 0 0 000000 1 0 0 001000 2 0 0 010000 3 0 0 011000 4 0 0 100000 5 0 0 101000 6 0 0 110000 7 0 0 111000 8 0 1 000000 9 0 1 001000 10 0 1 010000 11 0 1 011000 12 0 1 100000 13 0 1 101000 14 0 1 110000 15 0 1 111000 16 1 0 000000 17 1 0 001000 18 1 0 010000 19 1 0 011000 20 1 0 100000 21 1 0 101000 22 1 0 110000 23 1 0 111000 24 1 1 000000 25 1 1 001000 26 1 1 010000 27 1 1 011000 28 1 1 100000 29 1 1 101000 30 1 1 110000 31 1 1 111000 32
X = Don’t Care
–7–REV. PrD
PRELIMINARY TECHNICAL DA T A
ADG726/ADG732

TERMINOLOGY

V
DD
V
SS
I
DD
I
SS
GN D Ground (0 V) reference. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. IN Logic control input.
) Analog voltage on terminals D, S
V
D (VS
R
ON
∆R
ON
R
FLAT(ON)
I
(OFF) Source leakage current with the switch “OFF.”
S
I
(OFF) Drain leakage current with the switch “OFF.”
D
, IS (ON) Channel leakage current with the switch “ON.”
I
D
V
INL
V
INH
I
INL(IINH
(OFF) “OFF” switch source capacitance. Measured with reference to ground.
C
S
(OFF) “OFF” switch drain capacitance. Measured with reference to ground.
C
D
(ON) “ON” switch capacitance. Measured with reference to ground.
C
D,CS
C
IN
t
TRANSITION
t
(EN) Delay time between the 50% and 90% points of the EN digital input and the switch “ON” condition.
ON
(EN) Delay time between the 50% and 90% points of the EN digital input and the switch “OFF” condition.
t
OFF
t
OPEN
Charge A measure of the glitch impulse transferred from the digital input to the analog output during switching. Injection
Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal is coupled through from one channel to another as a result of parasitic
On Response The Frequency response of the “ON” switch. Insertion The loss due to the ON resistance of the switch.
Loss
Most positive power supply potential. Most Negative power supply in a dual supply application. In single supply applications, connect to GND. Positive supply current. Negative supply current.
Ohmic resistance between D and S. On resistance match between any two channels, i.e. RONmax - RONmin Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea
sured over the specified analog signal range.
Maximum input voltage for logic “0”. Minimum input voltage for logic “1”.
) Input current of the digital input.
Digital input capacitance. Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condi
tion when switching from one address state to another.
“OFF” time measured between the 80% points of both switches when switching from one address state to another.
capacitance.
–8– REV. PrD
PRELIMINARY TECHNICAL DA T A
TYPICAL PERFORMANCE CHARACTERISTICS
ADG726/ADG732
TBD
TPC 1. On Resistance as a Function of
V
) for for Single Supply
D(VS
TBD
TPC 2. On Resistance as a Function of
VD(VS) for Dual Supply
TBD
TPC 4. On Resistance as a Function of
V
) for Different Temperatures,
D(VS
Single Supply
TBD
TPC 5. On Resistance as a Function of
VD(VS) for Different Temperatures,
Dual Supply
TBD
TPC 7. Leakage Currents as a function
of VD(VS)
TBD
TPC 8. Leakage Currents as a function
of VD(VS)
TBD
TPC 3. On Resistance as a Function of
VD(VS) for Different Temperatures,
Single Supply
TBD
TPC 6. Leakage Currents as a function
of VD(VS)
–9–REV. PrD
TBD
TPC 9. Leakage Currents as a function
of Temperature
ADG726/ADG732
PRELIMINARY TECHNICAL DA T A
TBD
TPC 10. Leakage Currents as a
Function of Temperature
TBD
TPC 11. Supply Currents vs. Input
Switching Frequency
TBD
TPC 13. TON/T
Temperature
Times vs.
OFF
TBD
TPC 14. Off Isolation vs. Frequency
TBD
TPC 16. On Response vs. Frequency
TBD
TPC 12. Charge Injection vs. Source
Voltage
TBD
TPC 15. Crosstalk vs. Frequency
–10– REV. PrD
Test Circuits
D

Test Circuit 1. On Resistance.

IS(OFF)
V
S
PRELIMINARY TECHNICAL DA T A
ADG726/ADG732
I
DS
V
V
V1
S
V
S
RON = V1/I
D
V
S
DS
V
S1 S2 S32
Test Circuit 3. I
V
S1
S32
DD
V
DD
V
V
DD
SS
V
V
DD
GND
SS
D
+0.8V
EN
V
S
S1 S2 S32
V
D
SS
DD
V
SS
DD
I
(OFF)
D
D
A
V
V
D
GND
GND
+0.8V
EN
(OFF)
D
V
SS
V
SS
EN
D
+2.4V
ID(ON)
A

Test Circuit 2. IS (OFF).

V
IN
V
IN
Ω
50
* SIMILAR CONNECTION FOR ADG726
50
Ω
*SIMILAR CONNECTION FOR ADG726
V
DD
V
DD
A4
S2 THRU S31
A0
ADG732*
EN
CS
V
DD
V
DD
A4
S2 THRU S31
ADG732*
A0
EN GND
CS
V
GND
SS
V
SS
S1
S32
WR
V
S1
V
S32
D
R
L
300
C
L
35pF
Ω
V
DRIVE (VIN)
OUT
ADDRESS
V
OUT
3V
0V
V
S1
V
S32
Test Circuit 5. Switching Time of Multiplexer, t
V
SS
V
SS
S1
S32
D
WR
R 300
V
S
V
OUT
C
L
L
35pF
Ω
ADDRESS
DRIVE (V
3V
)
IN
0V
V
S
V
OUT
Test Circuit 4. I
50%
90%
t
TRANSITION
TRANSITION
80%
t
OPEN
.
80%
(ON)
D
50%
t
TRANSITION
90%
Test Circuit 6. Break Before Make Delay, t
OPEN
.
–11–REV. PrD
ADG726/ADG732
V
V
EN
PRELIMINARY TECHNICAL DA T A
V
V
DD
SS
V
V
DD
A4
A0 CS
WR
CS
V
WR
*SIMILAR CONNECTION FOR ADG726
SS
S1
S2 THRU S32
ADG732*
D
EN GND
Test Circuit 7. Write Turn-On and Turn Off Time, t
V
V
DD
SS
V
V
DD
S2 THRU S32
ADG732*
GND
CS
SS
WR
S1
V
D
R
L
300
A4
A0
EN
R
300
S
V
S
V
OUT
C
L
L
35pF
Ω
V
OUT
C
L
35pF
Ω
SWITCH
OUTPUT
WR
SWITCH
OUTPUT
(WR).
3V
EN
0V
V
0V
3V
0V
V
O
0V
O
90%
t
ON
50%
50%
(EN)
ON
t
ON
t
OFF
(WR)
(WR)
, t
OFF
t
OFF
20%
80%
50%
(EN)
10%
*SIMILAR CONNECTION FOR ADG726
R
S
V
S
V
IN
*SIMILAR CONNECTION FOR ADG726
V
V
DD
SS
V
A4
V
SS
DD
GND
S1
S32
D
WR
A0
EN**
CS
ADG732*
Test Circuit 8. Enable Delay, tON(EN), t
V
V
DD
SS
V
V
DD
SS
A4
ADG732*
A0
S
EN
+2.4V
RS
D
C 1nF
V
OUT
L
LOGIC
INPUT (VIN)
V
OUT
3V
0V
OFF
(EN)
Q
INJ
= CL x ∆ V
OUT
V
∆
OUT

Test Circuit 9. Charge Injection.

V
V
DD
SS
S1
V
A4
V
A0
DD
ADG732*
GND
CS
SS
S2
S32
WR
50
Ω
D
NETWORK ANALYZER
50
Ω
V
OUT
R
L
50
Ω
V
S
NETWORK
ANALYZER
50
Ω
V
V
OUT
R
L
50
Ω
S
EN
*SIMILAR CONNECTION FOR ADG726 ** CONNECT TO 2.4V FOR CROSSTALK MEASUREMENTS
OFF ISOLATION = 20LOG10(V INSERTION LOSS = 20LOG
10
)
OUT/VS
V
WITH SWITCH
OUT
(
V
WITHOUT SWITCH
OUT
)

Test Circuit 10. OFF Isolation and Bandwidth.

*SIMILAR CONNECTION FOR ADG726 CH ANNEL TO CHA NNEL CRO SSTALK =
20LOG10(V
OUT/VS
)

Test Circuit 11. Channel-to-Channel Crosstalk.

–12– REV. PrD
PRELIMINARY TECHNICAL DA T A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead CSP
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
37 48
36
BOTTOM
VIEW
PIN 1
INDICATOR
0.276(7.0) BSC SQ
TOP
VIEW
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.266 (6.75) BSC SQ
ADG726/ADG732
0.010 (0.25) MIN
1
0.207 (5.25)
0.201 (5.10) SQ
0.195 (4.95)
0.035 (0.90) MAX
0.033 (0.85) NOM
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
o
MAX
12
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.020 (0.50) BSC
0.028 (0.70) MAX
0.026 (0.65) NOM
0.002 (0.05)
0.008(0.20)
0.0004 (0.01)
REF
0.0 (0.0)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
48-Lead TQFP
(SU-48)
0.030 (0.75)
0.018 (0.45)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0° – 7
0.047 (1.20) MAX
0.041 (1.05)
0.037 (0.95)
°
0.008 (0.20)
0.004 (0.09)
0° MIN
0.354 (9.00) BSC
48
1
12
13
0.019 (0.5) BSC
25
0.276 (7.0) BSC
TOP VIEW
(PINS DOWN)
0.011 (0.27)
0.006 (0.17)
24
0.217 (5.5) REF
37
36
25
24
12
13
0.276 (7.0) BSC
0.354 (9.00) BSC
–13–REV. PrD
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