Datasheet ADG729, ADG728 Datasheet (Analog Devices)

CMOS, Low-Voltage, 2-Wire

S1

S8

SDADSCL

ADG728

S1A

DA

S4A

S1B

S4B

DB

ADG729

RESET

INPUT SHIFT

REGISTER

INPUT SHIFT

REGISTER

A0 A1 SDA SCL A0 A1

a

FEATURES
2-Wire Serial Interface

2.7 V to 5.5 V Single Supply

2.5 ⍀ On Resistance

0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Matrix Switch ADG728
Dual 4-to-1 Matrix Switch ADG729
Power-On Reset
Small 16-Lead TSSOP Package

APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Automatic Test Equipment

GENERAL DESCRIPTION

The ADG728 and ADG729 are CMOS analog matrix switches
with a serially controlled 2-wire interface. The ADG728 is an
8-channel matrix switch, while the ADG729 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range. These parts can operate
equally well as either multiplexers, demultiplexers or switch
arrays and the input signal range extends to the supplies.

The ADG728 and ADG729 utilize a 2-wire serial interface that
is compatible with the I
external address pins (A0 and A1). This allows the 2 LSBs of
the 7-bit slave address to be set by the user. Four of each of the
devices can be connected to the one bus. The ADG728 also has
a RESET pin that should be tied high if not in use.

Each channel is controlled by one bit of an 8-bit word. This
means that these devices may be used in a number of different
configurations; all, any, or none of the channels may be on at
any one time.

On power-up of the device, all switches will be in the OFF con­dition and the internal shift register will contain all zeros.

All channels exhibit break-before-make switching action pre­venting momentary shorting when switching channels.

The ADG728 and ADG729 are available in 16-lead TSSOP
packages.

2

C™ interface standard. Both have two

Serially-Controlled, Matrix Switches

ADG728/ADG729

FUNCTIONAL BLOCK DIAGRAMS

PRODUCT HIGHLIGHTS

1. 2-Wire Serial Interface.

2. Single Supply Operation. The ADG728 and ADG729 are
fully specified and guaranteed with 3 V and 5 V supply rails.

3. Low On Resistance 2.5 Ω typical.

4. Any configuration of switches may be on at any one time.

5. Guaranteed Break-Before-Make Switching Action.

6. Small 16-Lead TSSOP Package.

I2C is a trademark of Philips Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADG728/ADG729–SPECIFICATIONS

1

(VDD = 5 V ⴞ 10%, GND = 0 V, unless otherwise noted.)

B Version

–40ⴗC

Parameter 25ⴗC to +85ⴗC Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

) 2.5 Ω typ VS = 0 V to VDD, IS = 10 mA;

ON

4.5 5 Ω max Test Circuit 1
On-Resistance Match Between 0.4 Ω typ V
Channels (∆R
On-Resistance Flatness (R

) 0.8 Ω max

ON

) 0.75 Ω typ VS = 0 V to VDD, IS = 10 mA

FLAT(ON)

1.2 Ω max

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

Channel ON Leakage I

LOGIC INPUTS (A0, A1)

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

INH

(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V, Test Circuit 2

S

(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VD = 1 V/4.5 V, Test Circuit 3

D

, IS (ON) ± 0.01 nA typ VD = VS = 4.5 V/1 V, Test Circuit 4

D

2

INH

INL

± 0.1 ± 0.3 nA max

± 0.1 ± 1 nA max

± 0.1 ± 1 nA max

2.4 V min

0.8 V max

0.005 µA typ

± 0.1 µA max

DD

V

= 0 V to VDD, IS = 10 mA

S

= 5.5 V

DD

CIN, Input Capacitance 6 pF typ

INH

INL

2

0.7 V

DD

V

+ 0.3 V max

DD

–0.3 V min

0.3 V

DD

± 1.0 µA max

DD

2

0.6 V max I

2

V min

V max

V min

SINK

SINK

DD

= 3 mA
= 6 mA

95 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;

85 ns typ VS1 = 3 V, RL = 300 Ω, CL = 35 pF;

140 ns max V

= 3 V

S1

130 ns max Test Circuit 5

D

8 ns typ RL = 300 Ω, CL = 35 pF;

1ns minV

= VS2 = 3 V, Test Circuit 5

S1

= 2.5 V, RS = 0 Ω, CL = 1 nF;

S

Test Circuit 6

LOGIC INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

I

, Input Leakage Current 0.005 µA typ VIN = 0 V to V

IN

, Input Hysteresis 0.05 V

V

HYST

CIN, Input Capacitance 6 pF typ

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V max I

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

Charge Injection ±3 pC typ V

Off Isolation –55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz;

–75 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

Channel-to-Channel Crosstalk –55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz;

–75 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

–3 dB Bandwidth

ADG728 65 MHz typ R
ADG729 100 MHz typ

= 50 Ω, CL = 5 pF, Test Circuit 8

L

CS (OFF) 13 pF typ

(OFF)

C

D

ADG728 85 pF typ
ADG729 42 pF typ
, CS (ON)

C

D

ADG728 96 pF typ
ADG729 48 pF typ

POWER REQUIREMENTS V

I

DD

N

OTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

10 µA typ Digital Inputs = 0 V or 5.5 V

20 µA max

= 5.5 V

DD

–2 – REV. 0

ADG728/ADG729

1

SPECIFICATIONS

Parameter 25ⴗC to +85ⴗC Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

On-Resistance Match Between 0.4 Ω typ V
Channels (∆R
On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

Channel ON Leakage I

LOGIC INPUTS (A0, A1)

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

INH

CIN, Input Capacitance 3 pF typ

LOGIC INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

I

, Input Leakage Current 0.005 µA typ VIN = 0 V to V

IN

V

, Input Hysteresis 0.05 V

HYST

CIN, Input Capacitance 3 pF typ

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V max I

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

Charge Injection ±3 pC typ V

Off Isolation –55 dB typ R

Crosstalk –55 dB typ R

–3 dB Bandwidth

ADG728 65 MHz typ R
ADG729 100 MHz typ

C

(OFF) 13 pF typ

S

C

(OFF)

D

ADG728 85 pF typ
ADG729 42 pF typ

C

, CS (ON)

D

ADG728 96 pF typ
ADG729 48 pF typ

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature ranges are as follows: B Versions: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)6 Ω typ VS = 0 V to VDD, IS = 10 mA;

ON

) 1.2 Ω max

ON

FLAT(ON)

(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V, Test Circuit 2

S

(OFF) ± 0.01 nA typ VD = 3 V/1 V, VD = 1 V/3 V, Test Circuit 3

D

, IS (ON) ± 0.01 nA typ VD = VS = 3 V/1 V, Test Circuit 4

D

2

INH

INL

2

INH

INL

2

(VDD = 3 V ⴞ 10%, GND = 0 V, unless otherwise noted.)

B Version

11 12 Ω max Test Circuit 1

) 3.5 Ω typ VS = 0 V to VDD, IS = 10 mA

± 0.1 ±0.3 nA max

± 0.1 ±1 nA max

± 0.1 ±1 nA max

0.005 µA typ

DD

2

130 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;

115 ns typ RL = 300 Ω, CL = 35 pF;

D

8 ns typ RL = 300 Ω, CL = 35 pF;

–75 dB typ R

–75 dB typ R

10 µA typ Digital Inputs = 0 V or 3.3 V

–40ⴗC

DD

V

= 0 V to VDD, IS = 10 mA

S

= 3.3 V

DD

2.0 V min

0.4 V max

± 0.1 µA max

0.7 V

DD

V

+ 0.3 V max

DD

–0.3 V min

0.3 V

DD

± 1.0 µA max

V min

V max

DD

V min

= 3 mA

0.6 V max I

200 ns max V

180 ns max V

1ns minV

SINK

= 6 mA

SINK

= 2 V

S1

= 2 V, Test Circuit 5

S

= VS8 = 2 V, Test Circuit 5

S1

= 1.5 V, RS = 0 Ω, CL = 1 nF;

S

Test Circuit 6

= 50 Ω, CL = 5 pF, f = 10 MHz;

L

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

= 50 Ω, CL = 5 pF, f = 10 MHz;

L

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

= 50 Ω, CL = 5 pF, Test Circuit 8

L

= 3.3 V

DD

20 µA max

–3–REV. 0

ADG728/ADG729

1

TIMING CHARACTERISTICS

(VDD = 2.7 V to 5.5 V. All specifications –40ⴗC to +85ⴗC, unless otherwise noted.)

Parameter Limit at T

f

SCL

t

1

t

2

t

3

t

4

t

5

t

6

2

400 kHz max SCL Clock Frequency

2.5 ms min SCL Cycle Time

0.6 ms min t

1.3 ms min t

0.6 ms min t

100 ns min t

0.9 ms max t

MIN

, T

MAX

Unit Conditions/Comments

, SCL High Time

HIGH

, SCL Low Time

LOW

, Start/Repeated Start Condition Hold Time

HD, STA

, Data Setup Time

SU, DAT

, Data Hold Time

HD, DAT

0ms min

t

7

t

8

t

9

0.6 ms min t

0.6 ms min t

1.3 ms min t

, Setup Time for Repeated Start

SU, STA

, Stop Condition Setup Time

SU, STO

, Bus Free Time Between a STOP Condition and

BUF

a Start Condition

t

10

t

11

C

b

4

t

SP

NOTES

1

See Figure 1.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
the falling edge of SCL.

3

Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

4

Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns.

Specifications subject to change without notice.

300 ns max tR, Rise Time of Both SCL and SDA when Receiving
20 + 0.1C

3

b

ns min

250 ns max tF, Fall Time of SDA when Receiving
300 ns max t
20 + 0.1C

3

b

ns min

, Fall Time of SDA when Transmitting

F

400 pF max Capacitive Load for Each Bus Line

50 ns max Pulsewidth of Spike Suppressed

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

t

START

CONDITION

t

11

2

t

5

Figure 1. 2-Wire Serial Interface Timing Diagram

–4 – REV. 0

t

7

REPEATED

START

CONDITION

t

4

t

1

t

8

STOP

CONDITION

ADG728/ADG729

PIN FUNCTION DESCRIPTIONS

ADG728 ADG729 Mnemonic Function

1 1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into

the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated
with this 2-wire serial interface.

2 RESET Active low control input that clears the input register and turns all switches to the

OFF condition.

3 3 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into

the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cycle. It is a bidirectional open-drain data line which should be

pulled to the supply with an external pull-up resistor.
4, 5, 6, 7 4, 5, 6, 7 Sxx Source. May be an input or output.
8 8, 9 Dx Drain. May be an input or output.
9, 10, 11, 12 10, 11, 12, 13
13 14 V
14 15 GND Ground Reference.
15 2 A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
16 16 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

Sxx Source. May be an input or output.

DD

Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.

PIN CONFIGURATIONS

ADG729

1

2

3

ADG729

4

TOP VIEW

5

(Not to Scale)

6

7

8

A0

16

15

14

V

DD

13

S1B

S2B

12

S3B

11

10

S4B

9

DB

SCL

RESET

SDA

S1

S2

S3

S4

D

ADG728

1

2

3

ADG728

4

TOP VIEW

5

(Not to Scale)

6

7

8

A0

16

A1

15

14

GND

V

13

DD

12

S5

S6

11

S7

10

S8

9

SCL

A1 GND

SDA

S1A

S2A

S3A

S4A

DA

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG728BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADG729BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16

–5–REV. 0

ADG728/ADG729

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog, Digital Inputs

2

. . . . . . . . . . –0.3 V to VDD + 0.3 V or

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)

Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA

Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA

Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

1

30 mA, Whichever Occurs First

TSSOP Package

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W

θ

JC

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

TERMINOLOGY

V

I

DD

DD

Most Positive Power Supply Potential.

Positive Supply Current.

GND Ground (0 V) Reference.

S Source Terminal. May be an input or output.

D Drain Terminal. May be an input or output.

V

(VS) Analog Voltage on Terminals D, S.

D

R

ON

∆R

ON

R

FLAT(ON)

Ohmic Resistance between D and S.

On Resistance Match Between any Two Chan­nels, i.e., R

max – RONmin.

ON

Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.

I

(OFF) Source Leakage Current with the Switch “OFF.”

S

I

(OFF) Drain Leakage Current with the Switch “OFF.”

D

I

, IS (ON) Channel Leakage Current with the Switch “ON.”

D

V

INL

V

INH

I

INL (IINH

C

(OFF) “OFF” Switch Source Capacitance. Measured

S

Maximum Input Voltage for Logic “0.”

Minimum Input Voltage for Logic “1.”

) Input Current of the Digital Input.

with reference to ground.

C

(OFF) “OFF” Switch Drain Capacitance. Measured

D

with reference to ground.

CD, CS (ON) “ON” Switch Capacitance. Measured with refer-

ence to ground.

C

IN

t

ON

Digital Input Capacitance.

Delay time between the 50% and 90% points
of the STOP condition and the switch “ON”
condition.

t

OFF

Delay time between the 50% and 90% points
of the STOP condition and the switch “OFF”
condition.

t

D

“OFF” time measured between the 80% points of
both switches when switching from one switch to
another.

Charge A measure of the glitch impulse transferred from
Injection the digital input to the analog output during

switching.

Off Isolation A measure of unwanted signal coupling through

an “OFF” switch.

Crosstalk A measure of unwanted signal which is coupled

through from one channel to another as a result
of parasitic capacitance.

Bandwidth The frequency at which the output is attenuated

by 3 dBs.

On Response The frequency response of the “ON” switch.

Insertion The loss due to the ON resistance of the switch.
Loss

–6 – REV. 0

Typical Performance Characteristics–ADG728/ADG729

8

7

6

5

4

3

ON RESISTANCE – ⍀

2

1

0

0

OR VS – DRAIN OR SOURCE VOLTAGE – V

V

D

VDD = 2.7V

VDD = 3.3V

12345

TA = 25ⴗC
V

VDD = 4.5V

VDD = 5.5V

= 0V

SS

Figure 2. On Resistance as a Function

(VS) for Single Supply

of V

D

0.12

VDD = 5V

= 0V

ID (ON)

IS (OFF)

V

SS

= 25ⴗC

T

A

ID (OFF)

CURRENT – nA

–0.04

–0.08

–0.12

0.08

0.04

0.00

0

1

2345

VD (VS) – Volts

Figure 5. Leakage Currents as a Func­tion of VD (VS)

8

+25ⴗC

VDD = 5V

= 0V

V

SS

7

6

5

4

3

ON RESISTANCE – ⍀

2

1

0

1

0

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

+85ⴗC

–40ⴗC

2345

Figure 3. On Resistance as a Function
of VD (VS) for Different Temperatures,
Single Supply

0.12

VDD = 3V

= 0V

V

SS

T

A

ID (ON)

ID (OFF)

= 25ⴗC

2.52.01.51.00.5

3.0

CURRENT – nA

–0.04

–0.08

–0.12

0.08

0.04

0.00

IS (OFF)

0

(VS) – Volts

V

D

Figure 6. Leakage Currents as a Func­tion of VD (VS)

8

+85

+25ⴗC

VDD = 3V

= 0V

V

SS

ⴗ

C

3.02.52.01.51.00.5

7

6

⍀

5

4

3

ON RESISTANCE –

2

1

0

0

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

–40ⴗC

Figure 4. On Resistance as a Function
of VD (VS) for Different Temperatures,
Single Supply

CURRENT – nA

–0.05

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

ID (OFF)

15

25

35 45 55 65 75 85

TEMPERATURE – ⴗC

IS (OFF)

VDD = 5V
V

= 0V

SS

ID (ON)

Figure 7. Leakage Currents as a
Function of Temperature

0.35

VDD = 3V
V

= 0V

SS

ID (ON)

CURRENT – nA

–0.05

0.30

0.25

0.20

0.15

0.10

0.05

0.00

ID (OFF)

IS (OFF)

15

25

35 45 55 65 75 85

TEMPERATURE – ⴗC

Figure 8. Leakage Currents as a Func­tion of Temperature

1m

TA = 25ⴗC

100␮

VDD = 5V

CURRENT – A

10␮

1␮

10k

FREQUENCY – Hz

VDD = 3V

100k 1M

Figure 9. Input Current vs. Switch­ing Frequency

–7–REV. 0

– pC

Q

20

10

0

VDD = 3V

–10

–20

–30

–40

VSS = 0V

0

1

2345

VOLTAGE – Volts

INJ

TA = 25ⴗC

VDD = 5V

VSS = 0V

Figure 10. Charge Injection vs. Source
Voltage

ADG728/ADG729

FREQUENCY – Hz

0

30k

ATTENUATION – dB

–20

–40

–60

–80

–100

–120

100k 1M 10M 100M

VDD = 5V
T

A

= 25ⴗC

160

140

T

= 3V

OFF, VDD

120

100

80

TON, VDD = 5V

TIME – ns

60

40

20

0

–40

–20 0 20 40 8060

TEMPERATURE – ⴗC

Figure 11. TON/T
Temperature

0

VDD = 5V

= 25ⴗC

T

A

–5

–10

TON, VDD = 3V

T

OFF, VDD

Times vs.

OFF

ADG728

ADG729

= 5V

0

VDD = 5V

= 25ⴗC

T

A

–20

–40

–60

–80

ATTENUATION – dB

–100

–120

100k 1M 10M 100M

30k

FREQUENCY – Hz

Figure 12. Off Isolation vs. Frequency

Figure 13. Crosstalk vs. Frequency

ATTENUATION – dB

–15

–20

30k

100k 1M 10M 100M

FREQUENCY – Hz

Figure 14. On Response vs.
Frequency

–8 – REV. 0

ADG728/ADG729

GENERAL DESCRIPTION

The ADG728 and ADG729 are serially controlled, 8-channel
and dual 4-channel matrix switches respectively. While provid­ing the normal multiplexing and demultiplexing functions, these
devices also provide the user with more flexibility as to where
their signal may be routed. Each bit of the serial word corre­sponds to one switch of the device. A Logic 1 in the particular
bit position turns on the switch, while a Logic 0 turns the switch
off. Because each switch is independently controlled by an indi­vidual bit, this provides the option of having any, all, or none of
the switches ON. This feature may be particularly useful in the
demultiplexing application where the user may wish to direct
one signal from the drain to a number of outputs (sources). Care
must be taken, however, in the multiplexing situation where a
number of inputs may be shorted together (separated only by
the small on resistance of the switch).

When changing the switch conditions, a new 8-bit word is writ­ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.

POWER-ON RESET

On power-up of the device, all switches will be in the OFF con­dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.

SERIAL INTERFACE
2-Wire Serial Bus

The ADG728/ADG729 are controlled via an I2C compatible
serial bus. These parts are connected to this bus as a slave device
(no clock is generated by the multiplexer).

The ADG728/ADG729 have different 7-bit slave addresses.
The five MSBs of the ADG728 are 10011, while the MSBs of
the ADG729 are 10001 and the two LSBs are determined by
the state of the A0 and A1 pins.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the
address byte, which consists of the 7-bit slave address fol­lowed by a R/W bit (this bit determines whether data will be
read from or written to the slave device).

The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W bit is high, the master will read
from the slave device. However, if the R/W bit is low, the
master will write to the slave device.

2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL.

3. When all data bits have been read or written, a STOP condition
is established by the master. A STOP condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In Write mode, the master will pull the SDA line high during
the 10th clock pulse to establish a STOP condition. In Read
mode, the master will issue a No Acknowledge for the ninth
clock pulse (i.e., the SDA line remains high). The master will
then bring the SDA line low before the tenth clock pulse and
then high during the tenth clock pulse to establish a STOP
condition.

See Figures 18 to 21 below for a graphical explanation of the
serial interface.

A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con­figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and receives one data byte,
the switches will update after the data byte, if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause an switch configuration
update. Repeat read of the matrix switch is also allowed.

INPUT SHIFT REGISTER

The input shift register is eight bits wide. Figure 15 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 1.
The 8-bit word consists of eight data bits each controlling one
switch. MSB (Bit 7) is loaded first.

DB7 (MSB)

S8 S7 S6 S5 S4 S3 S2 S1

DATA BITS

Figure 15. ADG728/ADG729 Input Shift Register Contents

DB0 (LSB)

–9–REV. 0

ADG728/ADG729

WRITE OPERATION

When writing to the ADG728/ADG729, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the figures below.

SCL

A1

ACK

BY

ADG728

START

COND

BY

MASTER

1

ADDRESS BYTE

SDA S8 S7 S6 S5 S4 S3 S2 S100 1 1 A0R/W

Figure 16. ADG728 Write Sequence

SCL

A1

ACK

BY

ADG729

START

COND

BY

MASTER

1

ADDRESS BYTE

SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W

0

Figure 17. ADG729 Write Sequence

READ OPERATION

When reading data back from the ADG728/ADG729, the user
must begin with an address byte and R/W bit, after which the
matrix switch will acknowledge that it is prepared to transmit data
by pulling SDA low. The readback operation is a single byte
that consists of the eight data bits in the input register. The read
operations for each part are shown in Figures 18 and 19.

SCL

A1

ACK

BY

ADG728

START

COND

BY

MASTER

1

ADDRESS BYTE

SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W

1

Figure 18. ADG728 Readback Sequence

DATA BYTE

DATA BYTE

DATA BYTE

ACK

BY

ADG728

ACK

BY

ADG729

NO ACK

BY

MASTER

STOP

COND

BY

MASTER

STOP

COND

BY

MASTER

STOP

COND

BY

MASTER

SCL

A1

START

COND

BY

MASTER

1

ADDRESS BYTE

SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W

0

Figure 19. ADG729 Readback Sequence

ACK

BY

ADG729

DATA BYTE

NO ACK

MASTER

BY

STOP

COND

BY

MASTER

–10– REV. 0

MULTIPLE DEVICES ON ONE BUS

Figure 20 shows four ADG728s devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each Matrix Switch to be writ­ten to or read from independently. Because the ADG729 has a
different address to the ADG728, it would be possible for four
of each of these devices to be connected to the same bus.

ADG728/ADG729

TEST CIRCUITS

Test Circuit 1. On Resistance

MASTER

S

V

S

SDA SCL

A1

A0

ADG728

I

DS

V

1

RON = V1/I

R

P

R

P

V

DD

+5V

SDA SCL

A1

A0

ADG728

V

DD

SDA SCL

A1

A0

ADG728

Figure 20. Multiple ADG728s on the Same Bus

D

DS

V

DD

SDA SCL

A1

A0

V

DD

V

S1

S2

S8

V

S

DD

GND

Test Circuit 3. IS (OFF)

ADG728

D

SDA

SCL

ID (OFF)

A

V

D

IS (OFF)

A

V

S

V

D

Test Circuit 2. ID (OFF)

V

DD

V

DD

ADG728*

S2 THRU S7

GND

* SIMILAR CONNECTION FOR ADG729

V

S1

S8

S1

V

S8

D

R

L

300⍀

V

DD

V

DD

S1

S2

S8

GND

D

S1

S8

V

S

Test Circuit 4. ID (ON)

C

L

35pF

SCL

V

S1

V

OUT

V

OUT

t

50%

90%

OFF

50%

90%

t

ON

Test Circuit 5. Switching Times and Break-Before-Make Times

V

DD

V

DD

GND

= V

V

S1

S8

V

OUT

80%

D

ID (ON)

A

V

D

t

OPEN

80%

–11–REV. 0

ADG728/ADG729

V

DD

V

DD

ADG728*

R

S

S

V

S

INPUT LOGIC

SDA

* SIMILAR CONNECTION FOR ADG729

D

GND

SCL

Test Circuit 6. Charge Injection

C
1nF

SWITCH ON

OUT

SWITCH OFF

Q

INJ

= CL x ⌬V

OUT

V

L

⌬V

OUT

V

DD

V

DD

ADG728*

50⍀

S1

S2

V

S

* SIMILAR CONNECTION FOR ADG729

CHANNEL-TO-CHANNEL CROSSTALK = 20LOG

S8

GND

D

R

L

50⍀

10(VOUT/VS

V

OUT

)

Test Circuit 7. Channel-to-Channel Crosstalk

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead TSSOP

(RU-16)

V

DD

V

DD

S1

S8

V

S

ADG728*

D

GND

*SIMILAR CONNECTION FOR ADG729

S1 IS SWITCHED OFF FOR OFF ISOLATION MEASURE­MENTS AND ON FOR BANDWIDTH MEASUREMENTS

OFF ISOLATION = 20LOG

INSERTION LOSS = 20LOG

10

10

R

L

50⍀

(V

)

OUT/VS

V

OUT

WITHOUT SWITCH

V

OUT

V

OUT

WITH SWITCH

Test Circuit 8. Off Isolation and Bandwidth

C3833–2.5–4/00 (rev. 0) 01002

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.201 (5.10)

0.193 (4.90)

16 9

BSC

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

0.177 (4.50)

0.169 (4.30)

81

0.0433 (1.10)
MAX

–12–

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

PRINTED IN U.S.A.

8ⴗ
0ⴗ

0.028 (0.70)

0.020 (0.50)

REV. 0