REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG721/ADG722/ADG723
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
CMOS
Low Voltage 4 V Dual SPST Switches
FUNCTIONAL BLOCK DIAGRAMS
ADG721
IN1
D2
S2
S1
D1
IN2
ADG722
IN1
D2
S2
S1
D1
IN2
ADG723
IN1
D2
S2
S1
D1
IN2
SWITCHES SHOWN FOR A LOGIC "0" INPUT
FEATURES
+1.8 V to +5.5 V Single Supply
4 V (Max) On Resistance
Low On-Resistance Flatness
–3 dB Bandwidth >200 MHz
Rail-to-Rail Operation
8-Lead mSOIC Package
Fast Switching Times
t
ON
20 ns
t
OFF
10 ns
Low Power Consumption (<0.1 mW)
TTL/CMOS Compatible
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
GENERAL DESCRIPTION
The ADG721, ADG722 and ADG723 are monolithic CMOS
SPST switches. These switches are designed on an advanced
submicron process that provides low power dissipation yet gives
high switching speed, low On resistance and low leakage currents.
The ADG721, ADG722 and ADG723 are designed to operate
from a single +1.8 V to +5.5 V supply, making them ideal for
use in battery powered instruments and with the new generation
of DACs and ADCs from Analog Devices.
The ADG721, ADG722 and ADG723 contain two independent
single-pole/single-throw (SPST) switches. The ADG721 and
ADG722 differ only in that both switches are normally open and
normally closed respectively. While in the ADG723, Switch 1 is
normally open and Switch 2 is normally closed.
Each switch of the ADG721, ADG722 and ADG723 conducts
equally well in both directions when on. The ADG723 exhibits
break-before-make switching action.
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V Single Supply Operation. The ADG721,
ADG722 and ADG723 offers high performance, including
low on resistance and fast switching times and is fully specified and guaranteed with +3 V and +5 V supply rails.
2. Very Low R
ON
(4 Ω max at 5 V, 10 Ω max at 3 V). At 1.8 V
operation, R
ON
is typically 40 Ω over the temperature range.
3. Low On-Resistance Flatness.
4. –3 dB Bandwidth >200 MHz.
5. Low Power Dissipation. CMOS construction ensures low
power dissipation.
6. Fast t
ON/tOFF.
7. 8-Lead µSOIC.
–2– REV. 0
ADG721/ADG722/ADG723–SPECIFICATIONS
1
B Version
–408C to
Parameter +258C +858C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
)45 Ω max V
S
= 0 V to VDD, IS = –10 mA,
Test Circuit 1
On Resistance Match Between
Channels (∆R
ON
) 0.3 Ω typ V
S
= 0 V to VDD, IS = –10 mA
1.0 Ω max
On-Resistance Flatness (R
FLAT(ON)
) 0.85 Ω typ V
S
= 0 V to VDD, IS = –10 mA
1.5 Ω max
LEAKAGE CURRENTS V
DD
= +5.5 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 4.5 V/1 V, VD = 1 V/4.5 V
±0.25 ±0.35 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.01 nA typ V
S
= 4.5 V/1 V, VD = 1 V/4.5 V
±0.25 ±0.35 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ V
S
= VD = 1 V, or VS = VD = 4.5 V
±0.25 ±0.35 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
14 ns typ R
L
= 300 Ω, C
L
= 35 pF
20 ns max V
S
= 3 V, Test Circuit 4
t
OFF
6 ns typ R
L
= 300 Ω, C
L
= 35 pF
10 ns max V
S
= 3 V, Test Circuit 4
Break-Before-Make Time Delay, t
D
7 ns typ R
L
= 300 Ω, C
L
= 35 pF,
(ADG723 Only) 1 ns min V
S1
= VS2 = 3 V, Test Circuit 5
Charge Injection 2 pC typ V
S
= 2 V; R
S
= 0 Ω, C
L
= 1 nF,
Test Circuit 6
Off Isolation –60 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–80 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
Test Circuit 7
Channel-to-Channel Crosstalk –77 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–97 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
Test Circuit 8
Bandwidth –3 dB 200 MHz typ R
L
= 50 Ω, C
L
= 5 pF, Test Circuit 9
C
S
(OFF) 7 pF typ
C
D
(OFF) 7 pF typ
CD, CS (ON) 18 pF typ
POWER REQUIREMENTS V
DD
= +5.5 V
Digital Inputs = 0 V or 5 V
I
DD
0.001 µA typ
1.0 µA max
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +5 V 6 10%, GND = 0 V. All specifications –408C to +858C, unless otherwise noted.)
–3–REV. 0
ADG721/ADG722/ADG723
(VDD = +3 V 6 10%, GND = 0 V. All specifications –408C to +858C, unless otherwise noted.)
SPECIFICATIONS
1
B Version
–408C to
Parameter +258C +858C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
) 6.5 Ω typ V
S
= 0 V to VDD, IS = –10 mA
10 Ω max Test Circuit 1
On Resistance Match Between
Channels (∆R
ON
) 0.3 Ω typ V
S
= 0 V to VDD, IS = –10 mA
1.0 Ω max
On-Resistance Flatness (R
FLAT(ON)
) 3.5 Ω typ V
S
= 0 V to VDD, IS = –10 mA
LEAKAGE CURRENTS V
DD
= +3.3 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, VD = 1 V/3 V
±0.25 ±0.35 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, VD = 1 V/3 V
±0.25 ±0.35 nA max Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ V
S
= VD = 1 V, or 3 V
±0.25 ±0.35 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.4 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
16 ns typ R
L
= 300 Ω, C
L
= 35 pF
24 ns max V
S
= 2 V, Test Circuit 4
t
OFF
7 ns typ R
L
= 300 Ω, C
L
= 35 pF
11 ns max V
S
= 2 V, Test Circuit 4
Break-Before-Make Time Delay, t
D
7 ns typ R
L
= 300 Ω, C
L
= 35 pF,
(ADG723 Only) 1 ns min V
S1
= VS2 = 2 V, Test Circuit 5
Charge Injection 2 pC typ V
S
= 1.5 V; R
S
= 0 Ω, C
L
= 1 nF,
Test Circuit 6
Off Isolation –60 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–80 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
Test Circuit 7
Channel-to-Channel Crosstalk –77 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
–97 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
Test Circuit 8
Bandwidth –3 dB 200 MHz typ R
L
= 50 Ω, C
L
= 5 pF,
Test Circuit 9
C
S
(OFF) 7 pF typ
C
D
(OFF) 7 pF typ
CD, CS (ON) 18 pF typ
POWER REQUIREMENTS V
DD
= +3.3 V
Digital Inputs = 0 V or 3 V
I
DD
0.001 µA typ
1.0 µA max
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG721/ADG722/ADG723
–4– REV. 0
ORDERING GUIDE
Model Temperature Range Brand* Package Description Package Option
ADG721BRM –40°C to +85°C S6B µSOIC RM-8
ADG722BRM –40°C to +85°C S7B µSOIC RM-8
ADG723BRM –40°C to +85°C S8B µSOIC RM-8
*Brand = Due to package size limitations, these three characters represent the part number.
PIN CONFIGURATION
8-Lead mSOIC (RM-8)
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
S1
D1
IN2
GND
V
DD
IN1
D2
S2
ADG721/
722/723
Table I. Truth Table (ADG721/ADG722)
ADG721 In ADG722 In Switch Condition
0 1 OFF
10ON
Table II. Truth Table (ADG723)
Logic Switch 1 Switch 2
0 OFF ON
1 ON OFF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG721/ADG722/ADG723 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs
2
. . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
µSOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
R
ON
Ohmic resistance between D and S.
∆R
ON
On resistance match between any two channels
i.e., R
ON
max – R
ON
min.
R
FLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance as
measured over the specified analog signal range.
I
S
(OFF) Source leakage current with the switch “OFF.”
I
D
(OFF) Drain leakage current with the switch “OFF.”
I
D
, IS (ON) Channel leakage current with the switch “ON.”
V
D (VS
) Analog voltage on terminals D, S.
C
S
(OFF) “OFF” Switch Source Capacitance.
C
D
(OFF) “OFF” Switch Drain Capacitance.
C
D
, CS (ON) “ON” Switch Capacitance.
t
ON
Delay between applying the digital control input
and the output switching on.
t
OFF
Delay between applying the digital control input
and the output switching off.
t
D
“OFF” time or “ON” time measured between the
90% points of both switches, When switching
from one address state to another. (ADG723 Only)
Crosstalk A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Charge A measure of the glitch impulse transferred
Injection during switching.
ADG721/ADG722/ADG723
–5–REV. 0
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
5.0
0 0.5
R
ON
– V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TA = +258C
VDD = +2.7V
VDD = +3.0V
VDD = +4.5V
VDD = +5.0V
5.5
6.0
Figure 1. On Resistance as a Function of VD (VS) Single
Supplies
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
6.0
0 0.5
R
ON
– V
5.0
4.0
3.0
2.0
1.0
0
1.0 1.5 2.0 2.5 3.0
VDD = +3V
+258C
–408C
+858C
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures V
DD
= +3 V
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
0 0.5
R
ON
– V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD = +5V
+258C
–408C
+858C
6.0
5.5
5.0
4.5
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures V
DD
= +5 V
FREQUENCY – Hz
1m
10 1M
I
SUPPLY
– A
100 1k 10k 100k
100m
10m
1m
100n
10n
1n
10M
VDD = +5V
Figure 4. Supply Current vs. Input Switching Frequency
FREQUENCY – Hz
–30
1M
OFF ISOLATION – dB
10k 100k
–40
–50
–60
–70
–80
–90
10M 100M
–100
VDD = +3V, +5V
Figure 5. Off Isolation vs. Frequency
FREQUENCY – Hz
–30
1M
CROSSTALK – dB
10k 100k
–40
–50
–60
–70
–80
–90
10M 100M
–100
–110
VDD = +3V, +5V
Figure 6. Crosstalk vs. Frequency
Typical Performance Characteristics–
ADG721/ADG722/ADG723
–6– REV. 0
–6
ON RESPONSE – dB
–7
–8
–9
–10
–11
–12
FREQUENCY – Hz
1M100 1k 10k 100k 10M
100M
VDD = +5V
Figure 7. On Response vs. Frequency
I
DS
V1
SD
V
S
R
ON
= V1/I
DS
Test Circuit 1. On Resistance
Test Circuits
SD
V
S
A A
V
D
I
S
(OFF) ID (OFF)
Test Circuit 2. Off Leakage
SD
V
S
A
V
D
I
D
(ON)
Test Circuit 3. On Leakage
0.1mF
V
S
IN
SD
V
DD
GND
R
L
300V
C
L
35pF
V
OUT
V
DD
ADG721
ADG722
V
IN
V
IN
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
50% 50%
Test Circuit 4. Switching Times
S1 D1
0.1mF
V
DD
IN1, IN2
V
S1
GND
R
L1
300V
C
L1
35pF
V
OUT1
V
S2
V
OUT2
R
L2
300V
C
L2
35pF
S2
V
IN
D2
V
DD
t
D
t
D
50% 50%
90%
V
IN
V
OUT1
V
OUT2
90%
90%
90%
0V
0V
0V
Test Circuit 5. Break-Before-Make Time Delay, tD (ADG723 Only)
ADG721/ADG722/ADG723
–7–REV. 0
SD
V
DD
IN
V
S
GND
C
L
1nF
V
OUT
R
S
V
DD
SW ON
V
IN
V
OUT
DV
OUT
Q
INJ
= CL 3 DV
OUT
SW OFF
Test Circuit 6. Charge Injection
SD
0.1mF
V
DD
IN
V
S
GND
R
L
50V
V
OUT
V
IN
V
DD
Test Circuit 7. Off Isolation
SD
0.1mF
V
DD
V
S
GND
50V
V
OUT
V
IN1
V
IN2
R
L
50V
NC
CHANNEL-TO-CHANNEL
CROSSTALK
= 20 3 LOG V
S/VOUT
V
DD
SD
Test Circuit 8. Channel-to-Channel Crosstalk
SD
0.1mF
V
DD
IN
V
S
GND
R
L
50V
V
OUT
V
IN
V
DD
Test Circuit 9. Bandwidth
ADG721/ADG722/ADG723
–8–
REV. 0
C3294–8–4/98
PRINTED IN U.S.A.
APPLICATIONS INFORMATION
The ADG721/ADG722/ADG723 belongs to Analog Devices’
new family of CMOS switches. This series of general purpose
switches have improved switching times, lower on resistance,
higher bandwidths, low power consumption and low leakage
currents.
ADG721/ADG722/ADG723 Supply Voltages
Functionality of the ADG721/ADG722/ADG723 extends from
+1.8 V to +5.5 V single supply, which makes it ideal for battery
powered instruments, where important design parameters are
power efficiency and performance.
It is important to note that the supply voltage effects the input
signal range, the on resistance and the switching times of the
part. By taking a look at the typical performance characteristics
and the specifications, the effects of the power supplies can be
clearly seen.
For V
DD
= +1.8 V, on resistance is typically 40 Ω over the tem-
perature range.
On Response vs. Frequency
Figure 8 illustrates the parasitic components that affect the ac
performance of CMOS switches (the switch is shown surrounded
by a box). Additional external capacitances will further degrade
some performance. These capacitances affect feedthrough,
crosstalk and system bandwidth.
C
DS
S
V
IN
C
D
C
LOAD
R
LOAD
D
V
OUT
R
ON
Figure 8. Switch Represented by Equivalent Parasitic
Components
The transfer function that describes the equivalent diagram of
the switch (Figure 8) is of the form (A)s shown below.
A(s) = R
T
s(RONC
DS
) +1
s(R
ONCTRT
) +1
where:
C
T
= C
LOAD
+ CD + C
DS
RT = R
LOAD
/(R
LOAD
+ RON)
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function A(s). Because the
switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with C
DS
and the load capacitance. The
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
The dominant effect of the output capacitance, C
D
, causes the
pole breakpoint frequency to occur first. Therefore, in order to
maximize bandwidth a switch must have a low input and
output capacitance and low on resistance. The On Response
vs. Frequency plot for the ADG721/ADG722/ADG723 can
be seen in Figure 7.
Off Isolation
Off isolation is a measure of the input signal coupled through an
off switch to the switch output. The capacitance, C
DS
, couples
the input signal to the output load, when the switch is off as
shown in Figure 9.
C
DS
S
V
IN
C
D
C
LOAD
R
LOAD
D
V
OUT
Figure 9. Off Isolation Is Affected by External Load Resistance and Capacitance
The larger the value of CDS, larger values of feedthrough will be
produced. The typical performance characteristic graph of Figure 5 illustrates the drop in off isolation as a function of frequency. From dc to roughly 1 MHz, the switch shows better
than –80 dB isolation. Up to frequencies of 10 MHz, the off
isolation remains better than –60 dB. As the frequency increases,
more and more of the input signal is coupled through to the
output. Off isolation can be maximized by choosing a switch
with the smallest C
DS
as possible. The values of load resistance
and capacitance also affect off isolation, as they contribute to
the coefficients of the poles and zeros in the transfer function of
the switch when open.
A(s) =
s(R
LOADCDS
)
s(R
LOAD
)(C
LOAD+CD+CDS
) +1
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead mSOIC
(RM-8)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33°
27°
0.120 (3.05)
0.112 (2.84)
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