Datasheet ADG715, ADG714 Datasheet (Analog Devices)

CMOS, Low Voltage

a

Serially-Controlled, Octal SPST Switches

FEATURES
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I

2

C™-Compatible Interface

2.7 V to 5.5 V Single Supply
3 V Dual Supply

2.5  On Resistance

0.6  On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package

APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching

GENERAL DESCRIPTION

The ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a two- or 3-wire
serial interface. On resistance is closely matched between switches
and very flat over the full signal range. Each switch conducts
equally well in both directions and the input signal range extends
to the supplies. Data is written to these devices in the form of
8 bits, each bit corresponding to one channel.

The ADG714 utilizes a 3-wire serial interface that is compatible
with SPI

, QSPI and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.

The ADG715 utilizes a 2-wire serial interface that is compatible
with the I

2

C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by the
user. A maximum of four of these devices may be connected to
the bus.

ADG714/ADG715

FUNCTIONAL BLOCK DIAGRAMS

ADG714

S1

S1

S2

S3

S4

S5

S6

S7

S8

INPUT SHIFT

REGISTER

SCLK DIN SYNC RESET

D1

D2

D3

D4

D5

D6

D7

D8

DOUT

S2

S3

S4

S5

S6

S7

S8

On power-up of these devices, all switches are in the OFF con­dition, and the internal registers contain all zeros.

Low power consumption and operating supply range of 2.7 V to

5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual ±3 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.

PRODUCT HIGHLIGHTS

1. 2-3-Wire Serial Interface.

2. Single/Dual Supply Operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and ±3 V
supply rails.

3. Low On Resistance, typically 2.5 Ω.

4. Low Leakage.

5. Power-On Reset.

6. Small 24-lead TSSOP package.

ADG715

INTERFACE

LOGIC

SDA SCL A0 A1

D1

D2

D3

D4

D5

D6

D7

D8

RESET

I2C is a trademark of Philips Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

1

ADG714/ADG715–SPECIFICATIONS

B Version

–40C

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

On-Resistance Match Between Channels (∆R

On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

Channel ON Leakage I

DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)

Input High Voltage, V
Input Low Voltage, V
Input Current, I

CIN, Digital Input Capacitance

DIGITAL OUTPUT ADG714 DOUT

Output Low Voltage 0.4 max I
C

Digital Output Capacitance 4 pF typ

OUT

DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

IIN, Input Leakage Current 0.005 µA typ VIN = 0 V to V

, Input Hysteresis 0.05 V

V

HYST

CIN, Input Capacitance 6 pF typ

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V max I

DYNAMIC CHARACTERISTICS

tON ADG714 20 ns typ VS = 3 V, RL = 300 Ω, CL = 35 pF

ADG715 95 ns typ VS = 3 V, RL = 300 Ω, CL = 35 pF

t

ON

ADG714 8 ns typ VS = 3 V, RL = 300 Ω, CL = 35 pF

t

OFF

ADG715 85 ns typ VS = 3 V, RL = 300 Ω, CL = 35 pF

t

OFF

Break-Before-Make Time Delay, t

Charge Injection ± 3 pC typ V
Off Isolation –60 dB typ

Channel-to-Channel Crosstalk –70 dB typ

–3 dB Bandwidth 155 MHz typ RL = 50 Ω, CL = 5 pF
CS (OFF) 11 pF typ

(OFF) 11 pF typ

C

D

CD, CS (ON) 22 pF typ

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)2.5Ω typ VS = 0 V to VDD, IS = 10 mA

ON

4.5 5 Ω max

)0.4Ω typ

ON

0.8 Ω max V

)0.6 Ω typ VS = 0 V to VDD, IS = 10 mA

FLAT(ON)

1.2 Ω max

(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V

S

± 0.1 ± 0.3 nA max

(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V

D

± 0.1 ± 0.3 nA max

, IS (ON) ± 0.01 nA typ VD = VS = 1 V, or 4.5 V

D

± 0.1 ± 0.3 nA max

2.4 V min

0.8 V max

± 0.1 µA max

0.7 V
V

DD

–0.3 V min

INL

or I

INH

INL

INH

INL

INH

0.005 µA typ VIN = V

2

2

2

3 pF typ

0.3 V

± 1 µA max

DD

2

0.6 V max I

2

32 ns max

140 ns max

15 ns max

130 ns max

D

8 ns typ VS = 3 V, RL = 300 Ω, CL = 35 pF

1 ns min

–80 dB typ R

–90 dB typ R

10 µA typ Digital Inputs = 0 V or 5.5 V

20 µA max

(VDD = 5 V  10%, VSS = 0 V, GND = 0 V unless otherwise noted)

V

DD

DD

V min

= 0 V to V

S

= 5.5 V

DD

INL

= 6 mA

SINK

DD

or V

INH

, IS = 10 mA

+ 0.3 V max

V max

DD

DD

V min

= 3 mA

SINK

= 6 mA

SINK

= 2 V, RS = 0 Ω, CL = 1 nF

S

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

= 5.5 V

DD

–2–

REV. 0

1

ADG714/ADG715

SPECIFICATIONS

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

On-Resistance Match Between Channels (∆RON) 0.4 Ω typ VS = 0 V to V

On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage ID (OFF) ± 0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V

Channel ON Leakage I

DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)

Input High Voltage, V
Input Low Voltage, V
Input Current, I

CIN, Digital Input Capacitance

DIGITAL OUTPUT ADG714 DOUT

Output Low Voltage 0.4 max I
C

Digital Output Capacitance 4 pF typ

OUT

DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

I

, Input Leakage Current 0.005 µA typ VIN = 0 V to V

IN

V

, Input Hysteresis 0.05 V

HYST

CIN, Input Capacitance 6 pF typ

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V max I

DYNAMIC CHARACTERISTICS

tON ADG714 35 ns typ VS = 2 V, RL = 300 Ω, CL = 35 pF

tON ADG715 130 ns typ VS = 2 V, RL = 300 Ω, CL = 35 pF

t

ADG714 11 ns typ VS = 2 V, RL = 300 Ω, CL = 35 pF

OFF

t

ADG715 115 ns typ VS = 2 V, RL = 300 Ω, CL = 35 pF

OFF

Break-Before-Make Time Delay, t

Charge Injection ± 2 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF
Off Isolation –60 dB typ

Channel-to-Channel Crosstalk –70 dB typ

–3 dB Bandwidth 155 MHz typ RL = 50 Ω, CL = 5 pF

(OFF) 11 pF typ

C

S

C

(OFF) 11 pF typ

D

CD, CS (ON) 22 pF typ

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)6Ω typ VS = 0 V to VDD, IS = 10 mA

ON

FLAT(ON)

(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V

S

, IS (ON) ± 0.01 nA typ VS = VD = 1 V, or 3 V

D

INH

INL

or I

INL

INH

INH

INL

2

(VDD = 3 V  10%, VSS = 0 V, GND = 0 V unless otherwise noted)

B Version

11 12 Ω max

) 3.5 Ω typ VS = 0 V to VDD, IS = 10 mA

± 0.1 ± 0.3 nA max

± 0.1 ± 0.3 nA max

± 0.1 ± 0.3 nA max

0.005 µA typ VIN = V

2

2

2

2

D

3 pF typ

8 ns typ VS = 2 V, RL = 300 Ω, CL = 35 pF

–80 dB typ R

–90 dB typ R

10 µA typ Digital Inputs = 0 V or 3.3 V

–40C

V

DD

1.2 Ω max

2.0 V min

0.4 V max

± 0.1 µA max

0.7 V
+ 0.3 V max

V

DD

DD

V min

–0.3 V min

DD

V max

0.3 V

± 1 µA max

DD

V min

0.6 V max I

65 ns max

200 ns max

20 ns max

180 ns max

1 ns min

20 µA max

, IS = 10 mA

DD

= 3.3 V

DD

or V

INL

INH

= 6 mA

SINK

DD

= 3 mA

SINK

= 6 mA

SINK

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

= 3.3 V

DD

REV. 0

–3–

ADG714/ADG715–SPECIFICATIONS

1

DUAL SUPPLY

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V
On Resistance (R

On-Resistance Match Between Channels (∆R

On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

Channel ON Leakage I

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

CIN, Digital Input Capacitance

DIGITAL OUTPUT ADG714 DOUT

Output Low Voltage 0.4 max

C

Digital Output Capacitance 4 pF typ

OUT

DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V

Input Low Voltage, V

I

, Input Leakage Current 0.005 µA typ VIN = 0 V to V

IN

V

, Input Hysteresis 0.05 V

HYST

CIN, Input Capacitance 6 pF typ

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V max I

DYNAMIC CHARACTERISTICS

tON ADG714 20 ns typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF

t

ADG715 133 ns typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF

ON

t

ADG714 8 ns typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF

OFF

t

ADG715 124 ns typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF

OFF

Break-Before-Make Time Delay, t

Charge Injection ± 3 pC typ V
Off Isolation –60 dB typ

Channel-to-Channel Crosstalk –70 dB typ

–3 dB Bandwidth 155 MHz typ RL = 50 Ω, CL = 5 pF
C

(OFF) 11 pF typ

S

C

(OFF) 11 pF typ

D

CD, CS (ON) 22 pF typ

POWER REQUIREMENTS V

I

DD

I

SS

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

(VDD = +3 V  10%, VSS = 3 V  GND = 0 V unless otherwise noted)

B Version

) 2.5 Ω typ VS = VSS to VDD, IDS = 10 mA

ON

4.5 5 Ω max

) 0.4 Ω typ VS = VSS to VDD, IDS = 10 mA

ON

) 0.6 Ω typ VS = VSS to VDD, IDS = 10 mA

FLAT(ON)

(OFF) ± 0.01 nA typ VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V

S

± 0.1 ± 0.3 nA max

(OFF) ± 0.01 nA typ VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V

D

± 0.1 ± 0.3 nA max

, IS (ON) ± 0.01 nA typ VS = VD = +2.25 V/–1.25 V

D

± 0.1 ± 0.3 nA max

INH

INL

INL

or I

INH

2

2

2

INH

INL

2

2

D

0.005 µA typ VIN = V

3 pF typ

8 ns typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF

–80 dB typ R

–90 dB typ R

15 µA typ Digital Inputs = 0 V or 3.3 V

15 µA typ

–40C

to VDDV

SS

0.8 Ω max

1 Ω max

2.0 V min

0.4 V max

± 0.1 µA max

0.7 V
V

+ 0.3 V max

DD

DD

V min

–0.3 V min

0.3 V

DD

V max

± 1 µA max

DD

V min

0.6 V max I

32 ns max

200 ns max

18 ns max

190 ns max

1 ns min

25 µA max

25 µA max

= +3.3 V, VSS = –3.3 V

DD

or V

INL

INH

I

= 6 mA

SINK

DD

= 3 mA

SINK

= 6 mA

SINK

= 0 V, RS = 0 Ω, CL = 1 nF

S

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

RL = 50 Ω, CL = 5 pF, f = 10 MHz

= 50 Ω, CL = 5 pF, f = 1 MHz

L

= +3.3 V, VSS = –3.3 V

DD

–4–

REV. 0

ADG714/ADG715

ADG714 TIMING CHARACTERISTICS

Parameter Limit at T

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

3

t

9

NOTES

1

See Figure 1.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

CL = 20 pF, RL = 1 kΩ.

Specifications subject to change without notice.

30 MHz max SCLK Cycle Frequency
33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
0 ns min SYNC to SCLK Rising Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
33 ns min Minimum SYNC High Time
20 ns min SCLK Rising Edge to DOUT Valid

SCLK

SYNC

DIN

DOUT

t

8

, T

MIN

DB71DB6

t

4

t

MAX

9

t

5

1, 2

(VDD = 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)

Unit Conditions/Comments

t

1

t

t

2

t

6

1

DB21DB11DB0

3

t

7

DB0DB7

1

NOTE

1

DATA FROM PREVIOUS WRITE CYCLE

Figure 1. 3-Wire Serial Interface Timing Diagram

REV. 0

–5–

ADG714/ADG715

ADG715 TIMING CHARACTERISTICS

1

(VDD = 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)

Parameter Limit at T

f

SCL

t

1

t

2

t

3

t

4

t

5

t

6

2

400 kHz max SCL Clock Frequency

2.5 µs min SCL Cycle Time

0.6 µs min t

1.3 µs min t

0.6 µs min t
100 ns min t

0.9 µs max t

MIN

, T

MAX

Unit Conditions/Comments

, SCL High Time

HIGH

, SCL Low Time

LOW

, Start/Repeated Start Condition Hold Time

HD, STA

, Data Setup Time

SU, DAT

, Data Hold Time

HD, DAT

0 µs min

t

7

t

8

t

9

0.6 µs min t

0.6 µs min t

1.3 µs min t

, Setup Time for Repeated Start

SU, STA

, Stop Condition Setup Time

SU, STO

, Bus Free Time Between a STOP Condition and

BUF

a Start Condition

t

10

t

11

t

11

C

b

4

t

SP

NOTES

1

See Figure 2.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.

3

Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

4

Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

Specifications subject to change without notice.

300 ns max tR, Rise Time of both SCL and SDA when Receiving
20 + 0.1C

3

b

ns min
250 ns max tF, Fall Time of SDA When Receiving
300 ns max tF, Fall Time of SDA when Transmitting
20 + 0.1C

3

b

ns min
400 pF max Capacitive Load for Each Bus Line
50 ns max Pulsewidth of Spike Suppressed

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

t

11

t

2

t

5

Figure 2. 2-Wire Serial Interface Timing Diagram

REPEATED

START

CONDITION

t

4

t

7

t

1

t

8

STOP

CONDITION

–6–

REV. 0

ADG714/ADG715

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

A0

RESET

A1

V

SS

S8

D8

S7

D7

S6

D6

S5

D5

SCL

V

DD

SDA

GND

S1

D1

S2

D2

S3

D3

S4

D4

ADG715

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –3.5 V

SS

Analog Inputs

Digital Inputs

2

. . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V

2

. . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

or 30 mA, Whichever Occurs First

or 30 mA, Whichever Occurs First

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

1

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128°C/W

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42°C/W

θ

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Interface Package Description Package Option

ADG714BRU –40°C to +85°C SPI/QSPI/MICROWIRE TSSOP RU-24
ADG715BRU –40°C to +85°CI

2

C-Compatible TSSOP RU-24

PIN CONFIGURATIONS

24-Lead TSSOP

24

23

22

21

20

19

18

17

16

15

14

13

SYNC

RESET

DOUT

V

SS

S8

D8

S7

D7

S6

D6

S5

D5

–7–

REV. 0

SCLK

V

DIN

GND

D1

D2

D3

D4

DD

S1

S2

S3

S4

1

2

3

4

5

ADG714

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

ADG714/ADG715

ADG714 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. These devices can accommodate serial input rates of up to 30 MHz.

2V

DD

3 DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial

4 GND Ground Reference.
5, 7, 9, 11, 14, Sx Source. May be an input or output.

16, 18, 20
6, 8, 10, 12, 13, Dx Drain. May be an input or output.

15, 17, 19
21 V

SS

22 DOUT Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of

23 RESET Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
24 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When

Positive Analog Supply Voltage.

clock input.

Negative Analog Supply Voltage. For single supply operation this should be tied to GND.

the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.

SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the

switches.

ADG715 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input

shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface.

2V

DD

Positive Analog Supply Voltage.

3 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input

shift register during the write cycle and used to readback one byte of data during the read cycle. It
is a bidirectional open-drain data line which should be pulled to the supply with an external pull-

up resistor.
4 GND Ground Reference.
5, 7, 9, 11, 14, Sx Source. May be an input or output.

16, 18, 20
6, 8, 10, 12, 13, Dx Drain. May be an input or output.

15, 17, 19
21 V

SS

Negative Analog Supply Voltage. For single supply operation this should be tied to GND.

22 A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
23 RESET Active Low Control Input. Clears the input register and turns all switches to the OFF condition.

24 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

–8–

REV. 0

TERMINOLOGY

ADG714/ADG715

V

DD

V

SS

Most positive power supply potential.
Most negative power supply in a dual supply

application. In single supply applications, this

should be tied to ground.
I
I

DD

SS

Positive Supply Current.

Negative Supply Current.
GND Ground (0 V) Reference
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
R

ON

∆R

ON

R

FLAT(ON)

Ohmic resistance between D and S.

On-resistance match between any two channels,

i.e., R

max–RON min.

ON

Flatness is defined as the difference between the

maximum and minimum value of on-resistance

as measured over the specified analog signal range.

I

(OFF) Source leakage current with the switch “OFF.”

S

I

(OFF) Drain leakage current with the switch “OFF.”

D

I

, IS (ON) Channel leakage current with the switch “ON.”

D

V

) Analog voltage on terminals D and S.

D (VS

C

(OFF) “OFF” Switch Source Capacitance. Measured

S

with reference to ground.

C

(OFF) “OFF” Switch Drain Capacitance. Measured

D

with reference to ground.

CD, CS (ON) “ON” Switch Capacitance. Measured with ref-

erence to ground.
C
t

IN

ON

Digital Input Capacitance.

Delay time between loading new data to the

shift register and selected switches switching on.
t

OFF

Delay time between loading new data to the

shift register and selected switches switching off.
Off Isolation A measure of unwanted signal coupling through

an “OFF” switch.
Crosstalk A measure of unwanted signal which is coupled

through from one channel to another as a result

of parasitic capacitance.
Charge A measure of the glitch impulse transferred

Injection from the digital input to the analog output

during switching.
Bandwidth The frequency at which the output is attenuated

by –3 dBs.
On Response The frequency response of the “ON” switch.
Insertion Loss The loss due to the ON resistance of the switch.

V

INL

V

INH

I

INL(IINH

I

DD

Insertion Loss = 20 log

without switch.

V

OUT

Maximum input voltage for Logic 0.

Minimum input voltage for Logic 1.

) Input current of the digital input.

Positive Supply Current.

(V

10

with switch/

OUT

REV. 0

–9–

ADG714/ADG715

–Typical Performance Characteristics

8

7

6

5

4

3

ON RESISTANCE – 

2

1

0

0 1 2345

VD, VS, DRAIN OR SOURCE VOLTAGE – V

VDD = 2.7V

VDD = 3.3V

VDD = 4.5V

TA = 25C

= GND

V

SS

VDD = 5.5V

Figure 3. On Resistance as a Function of VD (VS) Single
Supply

8

7

6

5

TA = 25C

8

VDD = 3V
V

7

6

5

4

ON RESISTANCE – 

3

2

0.5 1.0 1.5 2.52.0

0

VD OR VS DRAIN OR SOURCE VOLTAGE – V

+85C

–40C

SS

+25C

= GND

3.0

Figure 6. On Resistance as a Function of VD (VS) for
Different Temperatures; V

8

7

6

5

DD

= 5 V

VDD = +3.0V

= –3.0V

V

SS

4

3

ON RESISTANCE – 

2

1

0

–3.3

VDD = +3.0V
V

= –3.0V

SS

–2.7 –2.1 –1.5 –0.9 –0.3 0.3 0.9 1.5 2.1 2.7 3.3

VD OR VS DRAIN OR SOURCE VOLTAGE – V

VDD = +2.7V
V

= –2.7V

SS

VDD = +3.3V
V

= –3.3V

SS

Figure 4. On Resistance as a Function of VD (VS); Dual
Supply

8

7

6

5

4

3

ON RESISTANCE – 

2

1

0

0

+85C

12 3 54

VD OR VS DRAIN OR SOURCE VOLTAGE – V

+25C

–40C

VDD = 5V
V

= GND

SS

Figure 5. On Resistance as a Function of VD (VS) for
Different Temperatures; V

DD

= 3 V

4

3

ON RESISTANCE – 

2

1

0

–3.0 –2.5 –2.0

+85C

–40C

–1.5

–1.0 1.0 1.5 2.0 2.50.50

–0.5

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

+25C

3.0

Figure 7. On Resistance as a Function of VD (VS) for
Different Temperatures; Dual Supply

0.04

0.02

0

CURRENT – nA

–0.02

–0.04

012 43

IS (OFF)

VD OR VS – Volts

IS, ID (ON)

VDD = 5V

= GND

V

SS

= 25C

T

A

ID (OFF)

5

Figure 8. Leakage Currents as a Function of VD (VS)

–10–

REV. 0

ADG714/ADG715

FREQUENCY – Hz

0

30k

ATTENUATION – dB

–120

–100

–80

–60

–40

–20

100k 1M 10M 100M

VDD = 5V
T

A

= 25C

0.04

VDD = 3V

= GND

V

SS

= 25C

T

0.02

IS, ID (ON)

0

CURRENT – nA

–0.02

–0.04

010.5 21.5

ID (OFF)

I

(OFF)

S

VOLTAGE – V

A

2.5

3

Figure 9. Leakage Currents as a Function of VD (VS)

0.04

VDD = +3V

= –3V

V

SS

= 25C

T

0.02

(OFF)

I

0

S

ID (OFF)

A

0.1

VDD = 3V

= GND

V

SS

= 3V/ 1V

V

IS (OFF)

6050

D

= 1V/ 3V

V

S

ID (OFF)

80

0.05

0

CURRENT – nA

–0.05

–0.1

10 20 30 7040

ID, IS (ON)

TEMPERATURE – C

Figure 12. Leakage Currents as a Function of Temperature

CURRENT – nA

–0.02

–0.04

–3 –2 –130

VOLTAGE – V

Figure 10. Leakage Currents as a Function of VD (VS) Dual

IS, ID (ON)

21

Figure 13. Off Isolation vs. Frequency

Supply

0.1

VDD = +3V

= –3V

V

SS

= +2.25V/ –1.25V

V

D

= –1.25V/ +2.25V

V

0.05

S

0

CURRENT – nA

–0.05

–0.1

10 20 30 7040

V

= +5V

DD

= GND

V

SS

= 4.5V/ 1V

V

D

= 1V/ 4.5V

V

S

ID (OFF)

TEMPERATURE – C

6050

IS, ID (ON)

IS (OFF)

80

Figure 11. Leakage Currents as Function of Temperature

0

–2

–4

–6

–8

ATTENUATION – dB

–10

–12

–14

FREQUENCY – Hz

Figure 14. On Response vs. Frequency

100M10M1M100k30k

300M

REV. 0

–11–

ADG714/ADG715

S8 S7 S6 S5 S4 S3 S2 S1

DB7 (MSB) DB0 (LSB)

DATA BITS

–40

–50

–60

–70

–80

ATTENUATION – dB

–90

–100

30k

100k 1M 10M

FREQUENCY – Hz

VDD = 5V

= 25C

T

A

100M

Figure 15. Crosstalk vs. Frequency

– pC

INJ

Q

–10

–15

–20

10

5

0

VDD = +3.0V
V

= –3.0V

–5

SS

–3

–2 –1012345

VOLTAGE – V

VDD = +3.3V
V

SS

= GND

TA = 25C

VDD = +5V
V

= GND

SS

Figure 16. Charge Injection vs. Source/Drain Voltage

45

40

35

30

25

20

TIME – ns

15

10

5

0

10 20 30 7040

Figure 17. TON/T

, V

T

TON, V

T

T

OFF

= 3V

ON

DD

= 5V

DD

, V

= 3V

OFF

DD

, V

= 5V

OFF

DD

TEMPERATURE – C

Times vs. Temperature for ADG714

6050

VSS = GND

80

GENERAL DESCRIPTION

The ADG714 and ADG715 are serially controlled, octal SPST
switches, controlled by either a 2- or 3-wire interface. Each bit
of the 8-bit serial word corresponds to one switch of the part. A
Logic 1 in the particular bit position turns on the switch, while a
Logic 0 turns the switch off. Because each switch is independently
controlled by an individual bit, this provides the option of having
any, all, or none of the switches ON.

When changing the switch conditions, a new 8-bit word is writ­ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.

POWER-ON RESET

On power-up of the device, all switches will be in the OFF con­dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.

SERIAL INTERFACE
3-Wire Serial Interface

The ADG714 has a 3-wire serial interface (SYNC, SCLK, and
DIN), that is compatible with SPI, QSPI, MICROWIRE
interface standards and most DSPs. Figure 1 shows the tim­ing diagram of a typical write sequence.

Data is written to the 8-bit shift register via DIN under the con­trol of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.

When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on the falling edge of
SCLK. Each bit of the 8-bit word corresponds to one of the eight
switches. Figure 18 shows the contents of the input shift regis­ter. Data appears on the DOUT pin on the rising edge of SCLK
suitable for daisy chaining, delayed of course by eight bits. When
all eight bits have been written into the shift register, the SYNC
line is brought high again. The switches are updated with the
new configuration and the input shift register is disabled. With
SYNC held high, the input shift register is disabled, so further data
or noise on the DIN line will have no effect on the shift register.

Figure 18. Input Shift Register Contents

SERIAL INTERFACE
2-Wire Serial Interface

The ADG715 is controlled via an I2C-compatible serial bus.
This device is connected to the bus as a slave device (no clock is
generated by the switch).

The ADG715 has a 7-bit slave address. The five MSBs are 10010
and the two LSBs are determined by the state of the A0 and
A1 pins.

–12–

REV. 0

ADG714/ADG715

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is the
address byte that consists of the 7-bit slave address followed
by a R/W bit (this bit determines whether data will be read
from or written to the slave device).

The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage,
all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master will read from the
slave device. However, if the R/W bit is low, the master will
write to the slave device.

2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.

3. When all data bits have been read or written, a STOP con­dition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a no acknowledge
for the ninth clock pulse (i.e., the SDA line remains high).
The master will then bring the SDA line low before the tenth
clock pulse and then high during the tenth clock pulse to estab­lish a STOP condition.

See Figure 19 for a graphical explanation of the serial interface.

A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con­figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and received one data byte,
the switches will update after the data byte; if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause a switch configuration update.
Repeat read of the matrix switch is also allowed.

Input Shift Register

The input shift register is eight bits wide. Figure 18 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure

2. The 8-bit word consists of eight data bits, each controlling
one switch. MSB (Bit 7) is loaded first.

Write Operation

When writing to the ADG715, the user must begin with an address
byte and R/W bit, after which the switch will acknowledge that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in the Figure 19 below.

READ Operation

When reading data back from the ADG715, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to transmit data by pulling SDA
low. The readback operation is a single byte that consists of the
eight data bits in the input register. The read operation for the
part is shown in Figure 20.

SCL

A1

START

COND

BY

1

ADDRESS BYTE

SDA S8 S7 S6 S5 S4 S3 S2 S10 0 1 0 A0 R/W

MASTER

Figure 19. ADG715 Write Sequence

SCL

SDA S8 S7 S6 S5 S4 S3 S2 S10 0 1 0 A0 R/W

MASTER

START

COND

BY

1

ADDRESS BYTE DATA BYTE

A1

Figure 20. ADG715 Readback Sequence

ACK

BY

ADG715

ACK

BY

ADG715

DATA BYTE

ACK

BY

ADG715

NO ACK

BY

MASTER

STOP

COND

BY

MASTER

STOP
COND

BY

MASTER

REV. 0

–13–

ADG714/ADG715

APPLICATIONS
Multiple Devices On One Bus

Figure 21 shows four ADG715 devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each switch to be written to or
read from independently.

Daisy-Chaining Multiple ADG714s

A number of ADG714 switches may be daisy-chained simply by
using the DOUT pin. Figure 22 shows a typical implementa­tion. The SYNC pin of all three parts in the example are tied
together. When SYNC is brought low, the input shift registers
of all parts are enabled, data is written to the parts via DIN, and
clocked through the shift registers. When the transfer is complete,
SYNC is brought high and all switches are updated simulta­neously. Further shift registers may be added in series.

V

DD

R

R

P

P

MASTER

V

SDA SCL SDA SCL SDA SCL SDA SCL

A1

A0

DD

A1

A0

ADG715ADG715 ADG715 ADG715

Power Supply Sequencing

When using CMOS devices, care must be taken to ensure correct
power-supply sequencing. Incorrect power-supply sequencing
can result in the device being subjected to stresses beyond those
maximum ratings listed in the data sheet. Digital and analog inputs
should always be applied after power supplies and ground. In dual
supply applications, if digital or analog inputs may be applied to
the device prior to the V
Schottky diode connected between V

and VSS supplies, the addition of a

DD

and GND will ensure

SS

that the device powers on correctly. For single supply operation,

should be tied to GND as close to the device as possible.

V

SS

Decoding Multiple ADG714s Using an ADG739

The dual 4-channel ADG739 multiplexer can be used to multiplex
a single chip select line in order to provide chip selects for up to

SDA

SCL

V

DD

A1

A0

V

DD

A1

A0

Figure 21. Multiple ADG715s On One Bus

-

SCLK

DIN

SYNC

SCLK

ADG714

DIN

SYNC

V

DD

R R R

SCLK

DOUT

ADG714

DIN

SYNC

DOUT

V

DD

SCLK

ADG714

DIN

SYNC

DOUT

V

DD

TO
OTHER
SERIAL
DEVICES

Figure 22. Multiple ADG714 Devices in a Daisy-Chained Configuration

–14–

REV. 0

ADG714/ADG715

four devices on the SPI bus. Figure 23 illustrates the ADG739 and
multiple ADG714s in such a typical configuration. All devices
receive the same serial clock and serial data, but only one device
will receive the SYNC signal at any one time. The ADG739 is a
serially controlled device also. One bit programmable pin of the
microcontroller is used to enable the ADG739 via SYNC2,
while another bit programmable pin is used as the chip select for
the other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By bringing
SYNC1 low, the selected serial device hanging from the SPI bus
will be enabled and data will be clocked into its shift register on
the falling edges of SCLK. The convenient design of the matrix
switch allows for different combinations of the four serial
devices to be addressed at any one time. If more devices need
to be addressed via one chip select line, the ADG738 is an 8­channel device and would allow further expansion of the chip
select scheme. There may be some digital feedthrough from the
digital input lines because SCLK and DIN are permanently
connected to each device. Using a burst clock will minimize the
effects of digital feedthrough on the analog channels.

SYNC

DIN

SCLK

FROM



CONTROLLER

OR DSP

SYNC1

SYNC2

SCLK

DIN

V

DD

1/2 of ADG739

DA

SCLK

DIN

S1A

S2A

S3A

S4A

SYNC

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC

DIN

SCLK

Figure 23. Addressing Multiple ADG714s Using an
ADG739

ADG714

ADG714

OTHER
SPI
DEVICE

OTHER
SPI
DEVICE

REV. 0

–15–

ADG714/ADG715

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead TSSOP

(RU-24)

0.311 (7.90)

0.303 (7.70)

24

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.0256 (0.65)
BSC

13

121

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

0.177 (4.50)

0.169 (4.30)

0.0079 (0.20)

0.0035 (0.090)

0.256 (6.50)

0.246 (6.25)

C3768–2.5–4/00 (rev. 0) 00043

8
0

0.028 (0.70)

0.020 (0.50)

–16–

PRINTED IN U.S.A.

REV. 0