Datasheet ADG663, ADG662, ADG661 Datasheet (Analog Devices)

LC2MOS

a

FEATURES
+5 V, 65 V Power Supplies
Ultralow Power Dissipation (<0.5 mW)
Low Leakage (<100 pA)
Low On Resistance (<50 V)
Fast Switching Times
Low Charge Injection
TTL/CMOS Compatible
TSSOP Package

APPLICATIONS
Battery Powered Instruments
Single Supply Systems
Remote Powered Equipment
+5 V Supply Systems
Computer Peripherals such as Disk Drives
Precision Instrumentation
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Sample Hold Systems
Communication Systems

Precision 5 V Quad SPST Switches

ADG661/ADG662/ADG663

FUNCTIONAL BLOCK DIAGRAM

IN1

IN2

ADG661

IN3

IN4

SWITCHES SHOWN FOR A LOGIC "1" INPUT

S1

D1
S2

D2
S3

D3
S4

D4

IN1

IN2

ADG663

IN3

IN4

IN1

IN2

ADG662

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

S1

D1
S2

D2
S3

D3
S4

D4

GENERAL DESCRIPTION

The ADG661, ADG662 and ADG663 are monolithic CMOS
devices comprising four independently selectable switches.
These switches feature low, well-controlled on resistance and
wide analog signal range, making them ideal for precision analog
signal switching.

They are fabricated using Analog Devices' advanced linear
compatible CMOS (LC

2

MOS) process, which offers benefits of
low leakage currents, ultralow power dissipation and low capaci­tance for fast switching speeds with minimum charge injection.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa­tion making the parts ideally suited for portable and battery
powered instruments.

The ADG661, ADG662 and ADG663 contain four indepen­dent SPST switches. The ADG661 and ADG662 differ only in
that the digital control logic is inverted. The ADG661 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG662. The ADG663
has two switches with digital control logic similar to that of the
ADG661, while the logic is inverted on the other two switches.

Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the supplies. In the
OFF condition, signal levels up to the supplies are blocked. All
switches exhibit break-before-make switching action for use in
multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.

PRODUCT HIGHLIGHTS

1. +5 V Single Supply Operation
The ADG661, ADG662 and ADG663 offer high perfor­mance, including low on resistance and wide signal range,
fully specified and guaranteed with ± 5 V and +5 V supply
rails.

2. Ultralow Power Dissipation
CMOS construction ensures ultralow power dissipation.

3. Low R

ON

4. Break-Before-Make Switching
This prevents channel shorting when the switches are config­ured as a multiplexer.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADG661/ADG662/ADG663–SPECIFICA TIONS

1

Dual Supply

(VDD = +5 V 6 10%, VSS = –5 V 6 10%, GND = 0 V, unless otherwise noted)

B Versions

Parameter +258C–408C to +858C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to V
R

ON

30 Ω typ VD = –3.5 V to +3.5 V, IS = –10 mA;

SS

38 50 Ω max VDD = +4.5 V, V

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.025 nA typ VD = ±4.5 V, VS = ±4.5 V;

S

V

= –4.5 V

SS

= +5.5 V, VSS = –5.5 V

DD

±0.1 ±2.5 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.025 nA typ VD = ±4.5 V, VS = ±4.5 V;

D

±0.1 ±2.5 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.05 nA typ VD = VS = ±4.5 V;

D

±0.2 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

±0.1 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG663 Only) V

Charge Injection 6 pC typ V

2

150 ns typ RL = 300 Ω, CL = 35 pF;

275 ns max V

= ±3 V; Test Circuit 4

S

55 ns typ RL = 300 Ω, CL = 35 pF;

120 ns max V

D

80 ns typ RL = 300 Ω, CL = 35 pF;

= ±3 V; Test Circuit 4

S

= VS2 = +3 V; Test Circuit 5

S1

= 0 V, RS = 0 Ω, CL = 10 nF;

S

Test Circuit 6

OFF Isolation 70 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 90 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

C

(OFF) 9 pF typ f = 1 MHz

S

C

(OFF) 9 pF typ f = 1 MHz

D

CD, CS (ON) 28 pF typ f = 1 MHz

POWER REQUIREMENTS

+4.5/5.5 V min/max

V

DD

I

DD

0.0001 µA typ VDD = +5.5 V, VSS = –5.5 V

–4.5/5.5 V min/max
1 µA max Digital Inputs = 0 V or 5 V

I

SS

0.0001 µA typ
1 µA max

NOTES

1

Temperature ranges are as follows: B Versions, –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. 0

ADG661/ADG662/ADG663

Single Supply

(VDD = +5 V 6 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)

B Versions

Parameter +258C–408C to +858C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
R

ON

45 Ω typ VD = 0 V to +3.5 V, IS = –10 mA;

DD

V

68 75 Ω max VDD = +4.5 V

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.025 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

S

= +5.5 V

DD

±0.1 ±2.5 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.025 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

D

±0.1 ±2.5 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.05 nA typ VD = VS = +4.5 V/+1 V;

D

±0.2 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

±0.1 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG663 Only) V

Charge Injection 12 pC typ V

2

250 ns typ RL = 300 Ω, CL = 35 pF;

400 ns max V

= +2 V; Test Circuit 4

S

45 ns typ RL = 300 Ω, CL = 35 pF;

100 ns max V

D

140 ns typ RL = 300 Ω, CL = 35 pF;

= +2 V; Test Circuit 4

S

= VS2 = +2 V; Test Circuit 5

S1

= 0 V, RS = 0 Ω, CL = 10 nF;

S

Test Circuit 6

OFF Isolation 70 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 90 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

C

(OFF) 9 pF typ f = 1 MHz

S

C

(OFF) 9 pF typ f = 1 MHz

D

CD, CS (ON) 28 pF typ f = 1 MHz

POWER REQUIREMENTS

V

DD

I

DD

0.0001 µA typ VDD = +5.5 V

+4.5/5.5 V min/max
1 µA max Digital Inputs = 0 V or 5 V

NOTES

1

Temperature ranges are as follows: B Versions, –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–3–REV. 0

ADG661/ADG662/ADG663

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

1

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

SS

Analog, Digital Inputs

2

. . . . . . . . . . . VSS –2 V to VDD +2 V or

30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 115°C/W

JA

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W

JC

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADG661BRU –40°C to +85°C 16-Lead TSSOP RU-16
ADG662BRU –40°C to +85°C 16-Lead TSSOP RU-16
ADG663BRU –40°C to +85°C 16-Lead TSSOP RU-16

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG661/ADG662/ADG663 features proprietary ESD protection circuitry, per­manent damage may occur on devices subjected to high energy electrostatic discharges. There­fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

–4–

REV. 0

ADG661/ADG662/ADG663

PIN CONFIGURATION

IN1

1

2

D1

3

S1

4

V

SS

5

GND

6

S4

(Not to Scale)

7

D4

8

IN4

NC = NO CONNECT

ADG661
ADG662
ADG663

TOP VIEW

16

IN2

15

D2

14

S2
V

13

DD

12

NC

11

S3

10

D3

9

IN3

Table I. Truth Table (ADG661/ADG662)

ADG661 In ADG662 In Switch Condition

01ON
1 0 OFF

Table II. Truth Table (ADG663)

Logic Switch 1, 4 Switch 2, 3

0 OFF ON
1 ON OFF

TERMINOLOGY

V

DD

V

SS

Most positive power supply potential.

Most negative power supply potential in
dual supplies. In single supply applications,
it may be connected to GND.

GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
R

ON

I

(OFF) Source leakage current with the switch “OFF.”

S

(OFF) Drain leakage current with the switch “OFF.”

I

D

I

, IS (ON) Channel leakage current with the switch “ON.”

D

V

) Analog voltage on terminals D, S.

D (VS

(OFF) “OFF” Switch Source Capacitance.

C

S

C

(OFF) “OFF” Switch Drain Capacitance.

D

C

, CS (ON) “ON” Switch Capacitance.

D

t

ON

Ohmic resistance between D and S.

Delay between applying the digital control
input and the output switching on.

t

OFF

Delay between applying the digital control
input and the output switching off.

t

D

“OFF” time or “ON” time measured between
the 90% points of both switches, when
switching from one address state to another.

Crosstalk A measure of unwanted signal which is

coupled through from one channel to another
as a result of parasitic capacitance.

Off Isolation A measure of unwanted signal coupling

through an “OFF” switch.

Charge A measure of the glitch impulse transferred
Injection from the digital input to analog output during

switching.

–5–REV. 0

ADG661/ADG662/ADG663

Typical Performance Characteristics

50

TA = +258C

40

50

40

VDD = +5V
V

= –5V

SS

50

TA = +25°C

40

30

– V

ON

R

20

VDD = +5V
V

= –5V

10

0

–55–4 34210–1–2–3

OR VS – DRAIN OR SOURCE VOLTAGE – V

V

D

SS

Figure 1. On Resistance as a
Function of V

10mA

1mA

100mA

10mA

SUPPLY

I

1mA

100nA

10nA

10

(VS) Dual Supplies

D

VDD = +5V
V

= –5V

SS

4 SW

1 SW

I–, I+

100

10k 1M

1k

FREQUENCY – Hz

100k

10M

Figure 4. Supply Current vs. Input
Switching Frequency

30

– V

ON

R

20

10

0

–5
V

OR VS – DRAIN OR SOURCE VOLTAGE – V

D

+858C

+258C

Figure 2. On Resistance as a
Function of V

(VS) for

D

Different Temperatures

10

VDD = +5V
V

= –5V

SS

1

VS = 65V
V

= 65V

D

0.1

0.01

LEAKAGE CURRENT – nA

IS (OFF)

0.001
25

35

TEMPERATURE – 8C

ID (OFF)

ID (ON)

Figure 5. Leakage Currents as a
Function of Temperature

30

– V

ON

R

20

10

5–4 3 4210–1–2–3

0

01 5

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

234

VDD = +5V

= 0V

V

SS

Figure 3. On Resistance as a
Function of V

120

100

80

OFF ISOLATION – dB

60

40

105958575655545

100 10M1k 10k 100k 1M

(VS) Single Supply

D

V

= +5V

DD

= –5V

V

SS

FREQUENCY – Hz

Figure 6. Off Isolation vs.
Frequency

0.006

0.004

0.002

0.000

–0.002

LEAKAGE CURRENT – nA

–0.004

–0.006

VDD = +5V

= –5V

V

SS

= +258C

T

A

–5 5–4 –3 –2 –1 0 1 2 3 4

VD OR VS – DRAIN OR SOURCE VOLTAGE

ID(ON)

ID(OFF)

IS(OFF)

Figure 7. Leakage Currents as a
Function of V

(VS)

D

110

100

90

80

CROSSTALK – dB

70

60

100 10M1k 10k 100k 1M

FREQUENCY – Hz

VDD = +5V

= –5V

V

SS

Figure 8. Crosstalk vs. Frequency

–6–

REV. 0

Test Circuits

V

S

RON = V1/I

I

DS

V1

SD

DS

V

S

I

(OFF)

S

A

SD

I

D

(OFF)

A

ADG661/ADG662/ADG663

SD

V

D

V

S

I

(ON)

D

A

V

D

1. On Resistance 2. Off Leakage

V

DD

0.1mF

V

DD

SD

R

V

S

IN

V

GND

SS

L

300V

C

L

35pF

V

OUT

V

V

V

OUT

0.1mF
V

SS

4. Switching Times

V

DD

0.1mF

V

GND

DD

0.1mF

V

C

L1

35pF

OUT1

R

OUT2

L1

300V

D2

R
300V

V

SS

V

SS

V

C

L2

L2

35pF

V

S1

V

S1 D1

S2

S2

IN1, IN2

V

IN

IN

IN

3V

ADG661

ADG662

V

IN

V

OUT1

V

OUT2

50% 50%

3V

50% 50%

90% 90%

t

ON

3V

0V

50% 50%

0V

90%

0V

t

3. On Leakage

t

OFF

t

90%

90%

D

90%

D

5. Break-Before-Make Time Delay

V

DD

V

DD

R

S

V

S

SD

IN

GND

V

OUT

C

L

10nF

V

SS

V

SS

3V

V

IN

V

OUT

Q

INJ

= CL 3 DV

OUT

DV

OUT

6. Charge Injection

–7–REV. 0

ADG661/ADG662/ADG663

+5V

–5V

2200pF

R

C

75V

C

C

1000pF

C

H

2200pF

V

OUT

ADG661
ADG662
ADG663

SW2

SW1

S

S

D

D

+5V

–5V

AD845

+5V

–5V

V

IN

OP07

Test Circuits (Continued)

V

DD

0.1mF

V

DD

SD

V

S

V

S

V

OUT

R

L

50V

IN

V

IN

V

GND

0.1mF

SS

V

SS

7. Off Isolation

V

DD

0.1mF

V

DD

SD

V

IN1

SD
V

GND

0.1mF

SS

CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG V

V

SS

APPLICATION

Figure 9 illustrates a precise, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an OP07. During the track mode, SW1 is closed and
the output V
SW1 is opened and the signal is held by the hold capacitor C

follows the input signal VIN. In the hold mode,

OUT

.

H

Due to switch and capacitor leakage, the voltage on the hold

R

L

50V

V

OUT

capacitor will decrease with time. The ADG661/ADG662/
ADG663 minimizes this droop due to its low leakage specifica­tions. The droop rate is further minimized by the use of a poly­styrene hold capacitor. The droop rate for the circuit shown is

C3257–8–1/98

typically 15 µV/µs.
A second switch SW2, which operates in parallel with SW1, is

included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen­tial effect on the op amp OP07 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa­tion network R

and CC. This compensation network also re-

C

duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes­tal error has a maximum value of 5 mV over the ±3 V input
range. The acquisition time is 2.5 ms while the settling time is

50V

V

IN2

NC

S/VOUT

1.85 µs.

8. Channel-to-Channel Crosstalk

Figure 9. Accurate Sample-and-Hold

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead TSSOP

(RU-16)

0.201 (5.10)

0.193 (4.90)

16

0.177 (4.50)

0.169 (4.30)

1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

PIN 1

0.0256
(0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

9

8

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

–8–

8°
0°

PRINTED IN U.S.A.

0.028 (0.70)

0.020 (0.50)

REV. 0