2.7 V to 5.5 V Single Supply
ⴞ2.7 V to ⴞ5.5 V Dual Supply
Rail-to-Rail Operation
10-Lead SOIC Package
Typical Power Consumption (<0.01 W)
TTL/CMOS Compatible Inputs
APPLICATIONS
Automatic Test Equipment
Power Routing
Communication Systems
Data Acquisition Systems
Sample and Hold Systems
Avionics
Relay Replacement
Battery-Powered Systems
4 ⍀ Dual SPST Switches
ADG621/ADG622/ADG623
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADG621, ADG622, and the ADG623 are monolithic,
CMOS SPST (single-pole, single-throw) switches. Each switch
of the ADG621, ADG622, and ADG623 conducts equally well
in both directions when on.
The ADG621/ADG622/ADG623 contain two independent
switches. The ADG621 and ADG622 differ only in that both
PRODUCT HIGHLIGHTS
1. Low On Resistance (RON) (4 Ω typ)
2. Dual ±2.7 V to ±5.5 V or Single 2.7 V to 5.5 V
3. Low Power Dissipation. CMOS construction ensures low
power dissipation.
4. Tiny 10-Lead µSOIC Package
switches are normally open and normally closed respectively. In the
ADG623, Switch 1 is normally open and Switch 2 is normally
closed. The ADG623 exhibits break-before-make switching action.
The ADG621/ADG622/ADG623 offers low on-resistance of
4 Ω, which is matched to within 0.25 Ω between channels.
These switches also provide low power dissipation yet gives
high switching speeds. The ADG621, ADG622, and ADG623
are available in a 10-lead µSOIC package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum
rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Table I. Truth Table for the ADG621/ADG622
ADG621 INxADG622 INxSwitch x Condition
01OFF
10ON
Table II. Truth Table for the ADG623
IN1IN2Switch S1Switch S2
00 OFF ON
01 OFFOFF
10 ON ON
11 ONOFF
ORDERING GUIDE
Model OptionTemperature RangeDescriptionPackageBranding Information*
ADG621BRM–40°C to +85°CµSOIC (microSmall Outline IC)RM-10SXB
ADG622BRM–40°C to +85°CµSOIC (microSmall Outline IC)RM-10SYB
ADG623BRM–40°C to +85°CµSOIC (microSmall Outline IC)RM-10SZB
*Branding on µSOIC packages is limited to three characters due to space constraints.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG621/ADG622/ADG623 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADG621/ADG622/ADG623
PIN CONFIGURATION
10-Lead SOIC
(RM-10)
V
1
S1
ADG621/
2
D1
ADG622/
3
IN2
ADG623
TOP VIEW
4
GND
(Not to Scale)
V
5
SS
NC = NO CONNECT
TERMINOLOGY
V
DD
V
SS
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied
to ground at the device.
GNDGround (0 V) Reference
I
DD
I
SS
Positive Supply Current
Negative Supply Current
SSource Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
INLogic Control Input
R
ON
∆R
ON
R
FLAT(ON)
Ohmic resistance between D and S.
On resistance match between any two Channels i.e., R
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
I
(OFF)Source Leakage Current with the switch “OFF.”
S
I
(OFF)Drain Leakage Current with the switch “OFF.”
D
I
, IS (ON)Channel Leakage Current with the switch “ON.”
D
V
)Analog Voltage on Terminals D, S.
D (VS
V
INL
V
INH
I
INL(IINH
C
C
C
t
ON
t
OFF
t
BBM
)Input Current of the Digital Input
(OFF)“OFF” Switch Source Capacitance
S
(OFF)“OFF” Switch Drain Capacitance
D
, CS (ON)“ON” Switch Capacitance
D
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Delay between applying the digital control input and the output switching on.
Delay between applying the digital control input and the output switching off.
“OFF” time or “ON” time measured between the 90% points of both switches, when switching from one
address state to another.
Charge InjectionA measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching.
CrosstalkA measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
Off IsolationA measure of unwanted signal coupling through an “OFF” switch.
BandwidthThe frequency response of the “ON” switch.
Insertion LossThe loss due to the ON resistance of the Switch.
10
9
8
7
6
DD
IN1
D2
S2
NC
ON
max – R
ON
min.
REV. 0
–5–
ADG621/ADG622/ADG623
–Typical Performance Characteristics
8
TA = 25ⴗC
7
6
5
, VSS = ⴞ3.3V
V
4
V
, VSS = ⴞ4.5V
DD
3
ON RESISTANCE – ⍀
2
1
0
–5–4–3–2–1012354
DD
VDD, VSS = ⴞ2.5V
V
, VSS = ⴞ3V
DD
, VS – V
V
D
V
, VSS = ⴞ5V
DD
TPC 1. On Resistance vs. VD (VS). (Dual Supply)
20
VDD = 2.7V
16
12
VDD = 3.3V
8
ON RESISTANCE – ⍀
4
0
0
VDD = 5V
12345
VDD = 3V
VD, VS – V
TA = 25ⴗC
V
SS
VDD = 4.5V
= 0V
10
9
8
7
6
5
4
ON RESISTANCE – ⍀
3
2
1
0
0
12354
TA = +85ⴗC
TA = +25ⴗC
TA = –40ⴗC
VD, VS – V
VDD = 5V
= 0V
V
SS
TPC 4. On Resistance vs. VD (VS) for Different
Temperature. (Single Supply)
0.5
0.4
0.3
0.2
0.1
0
, IS (ON)
= 0V
I
D
TEMPERATURE – ⴗC
–0.1
–0.2
LEAKAGE CURRENT – nA
VDD = 5V
–0.3
V
SS
–0.4
= ⴞ4.5V
V
D
= ⴟ4.5V
V
S
–0.5
0 1020304050
IS (OFF)
ID (OFF)
60
7080
TPC 2. On Resistance vs. VD (VS). (Single Supply)
6
5
4
3
2
ON RESISTANCE – ⍀
1
0
–5
–3–1153–4–2024
TA = +85ⴗC
TA = +25ⴗC
TA = –40ⴗC
VD, VS – V
VDD = +5V
= –5V
V
SS
TPC 3. On Resistance vs. VD (VS) for Different
Temperatures. (Dual Supply)
TPC 5. Leakage Currents vs. Temperature. (Dual Supply)
0.5
0.4
0.3
0.2
0.1
0
ID, IS (ON)
VDD = 5V
= 0V
V
SS
= 4.5V/1V
V
D
= 1V/4.5V
V
S
0 1020304050607080
TEMPERATURE – ⴗC
LEAKAGE CURRENT – nA
–0.1
–0.2
–0.3
–0.4
–0.5
IS (OFF)
ID (OFF)
TPC 6. Leakage Currents vs. Temperature. (Single Supply)
–6–
REV. 0
CHARGE INJECTION – pC
0.2100101
FREQUENCY – MHz
ATTENUATION – dB
0
–10
–20
–30
–40
–50
–60
–70
–80
VDD = +5V
V
SS
= –5V
T
A
= 25ⴗC
0.21000
0
10
VDD = +5V
V
SS
= –5V
TA = 25ⴗC
–2
–4
–6
–8
–10
–12
1100
FREQUENCY – MHz
ATTENUATION – dB
250
200
150
100
50
TA = 25ⴗC
V
V
DD
SS
= +5V
= –5V
VDD = 5V
= 0V
V
SS
ADG621/ADG622/ADG623
0
–5
–4–3–2–101235
TPC 7. Charge Injection vs. Source Voltage
180
160
140
120
100
80
TIME – ns
60
40
20
0
–40–20
ALTERNATION – dB
0
–10
–20
–30
–40
–50
–60
–70
–80
0.2
TPC 8. t
ON
TPC 9. OFF Isolation vs. Frequency
VDD ⴝ 5V
ⴝ 0V
V
SS
t
ON
t
OFF
VDD ⴝ 5V
ⴝ 0V
V
SS
020
TEMPERATURE – C
/ t
Times vs. Temperature
OFF
110100
FREQUENCY – MHz
REV. 0
V
S
4
TPC 10. Crosstalk vs. Frequency
VDD ⴝ +5V
ⴝ –5V
V
SS
VDD ⴝ +5V
ⴝ –5V
V
SS
40
60
80
TPC 11. On Response vs. Frequency
VDD = +5V
= –5V
V
SS
= 25ⴗC
T
A
–7–
ADG621/ADG622/ADG623
Test Circuits
I
DS
V1
SD
IS (OFF)ID (OFF)
SD
A
A
NC
SD
ID (ON)
A
V
S
RON = V1/I
DS
Test Ciruit 1. On Resistance
0.1F
V
S
0.1F
S1
V
S1
S2
V
S2
IN1, IN2
V
IN
IN
V
V
DD
V
V
DD
GND
V
S
V
V
SS
DD
V
DD
SD
GND
0.1F
V
SS
Test Ciruit 4. Switching Times
SS
0.1F
SS
D1
D2
R
300Ω
V
C
L2
L2
35pF
Test Ciruit 2. Off Leakage
V
IN
V
OUT2
R
L
300⍀
R
L1
300⍀
C
L
35pF
OUT
C
L1
35pF
V
OUT1
V
IN
V
OUT
V
V
V
D
OUT1
OUT2
ADG621
ADG622
V
IN
0V
0V
0V
50%50%
50%50%
90%90%
t
ON
50%50%
90%
90%
t
BBM
V
NC = NO CONNECT
D
Test Ciruit 3. On Leakage
t
OFF
90%
90%
t
BBM
Test Ciruit 5. Break-Before-Make Time Delay,
V
V
DD
SS
V
V
DD
SS
R
S
V
S
SD
IN
GND
C
1nF
V
OUT
L
SW ON
V
IN
V
OUT
Test Ciruit 6. Charge Injection
–8–
t
(ADG623 Only)
BBM
SW OFF
Q
= CL ∆V
ⴛ
INJ
OUT
∆V
OUT
REV. 0
ADG621/ADG622/ADG623
0.1F
IN
V
IN
OFF ISOLATION = 20 LOG
NETWORK
ANALYZER
V
OUT
R
L
50⍀
50⍀
V
S
V
V
SS
DD
0.1F
V
V
SS
DD
S
50⍀
D
GND
V
OUT
V
S
Test Ciruit 7. Off Isolation
V
DD
0.1F
V
DD
D1
S2
IN
GND
V
SS
V
SS
NETWORK
ANALYZER
50⍀
V
V
OUT
R
L
50⍀
0.1F
S1
D2
V
V
DD
SS
S
GND
0.1F
V
SS
D
V
OUT
V
WITHOUTSWITCH
OUT
NETWORK
ANALYZER
50⍀
R
L
50⍀
WITHSWITCH
V
S
V
OUT
0.1F
V
DD
S
IN
V
IN
INSERTIONLOSS=20LOG
Test Ciruit 9. Bandwidth
R
50⍀
R
50⍀
V
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
OUT
V
S
Test Ciruit 8. Channel-to-Channel Crosstalk
REV. 0
–9–
ADG621/ADG622/ADG623
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead SOIC Package
(RM-10)
0.122 (3.10)
0.114 (2.90)
0.122 (3.10)
0.114 (2.90)
0.037 (0.94)
0.031 (0.78)
0.006 (0.15)
0.002 (0.05)
106
1
PIN 1
0.0197 (0.50) BSC
0.120 (3.05)
0.112 (2.85)
0.199 (5.05)
0.187 (4.75)
5
0.012 (0.30)
0.006 (0.15)
0.043 (1.10)
MAX
SEATING
PLANE
0.009 (0.23)
0.005 (0.13)
0.120 (3.05)
0.112 (2.85)
6ⴗ
0ⴗ
0.028 (0.70)
0.016 (0.40)
–10–
REV. 0
–11–
C02616–.8–10/01(0)
–12–
PRINTED IN U.S.A.
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