Datasheet ADG5408 Datasheet (ANALOG DEVICES)

4-/8-Channel Multiplexers

ADG5408/ADG5409

Rev. B

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ADG5408

S1

S8

D

ADG5409

S1A

S4B

DA

DB

S4A

S1B

1-OF-4

DECODER

1-OF-8

DECODER

A0 A1 ENA0 A1 A2 EN

09206-001

Data Sheet

FEATURES

Latch-up proof
8 kV human body model (HBM) ESD rating
Low on resistance (13.5 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V

to VDD analog signal range

SS

APPLICATIONS

Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems

High Voltage Latch-Up Proof,

FUNCTIONAL BLOCK DIAGRAMS

Figure 1.

GENERAL DESCRIPTION

The ADG5408/ADG5409 are monolithic CMOS analog multi­plexers comprising eight single channels and four differential
channels, respectively. The ADG5408 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG5409 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1.

An EN input on both devices enables or disables the device.
When EN is disabled, all channels switch off. The on-resistance
profile is very flat over the full analog input range, which ensures
good linearity and low distortion when switching audio signals.
High switching speed also makes the parts suitable for video
signal switching.

Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The ADG5408/ADG5409 do not have V

pins; rather, the logic

L

power supply is generated internally by an on-chip voltage
generator.

PRODUCT HIGHLIGHTS

1. Tre nch isolation guards against latch-up. A dielectric trench

separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.

2. Low R

3. Dual-supply operation. For applications where the analog

signal is bipolar, the ADG5408/ADG5409 can be operated
from dual supplies up to ±22 V.

4. Single-supply operation. For applications where the analog

signal is unipolar, the ADG5408/ADG5409 can be operated
from a single rail power supply up to 40 V.

5. 3 V logic compatible digital inputs: V

6. No V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

.

ON

logic power supply required.

L

= 2.0 V, V

INH

www.analog.com

INL

= 0.8 V.

ADG5408/ADG5409 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ........................................................................... 2

Specifications ..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 4

12 V Single Supply ........................................................................ 5

36 V Single Supply ........................................................................ 6

Continuous Current per Channel, Sx or D ............................... 8

REVISION HISTORY

5/12—Rev. A to Rev. B

Removed Automotive Information (Throughout)....................... 1

Changes to Ordering Guide .......................................................... 22

Deleted Automotive Products Section ......................................... 22

6/11—Rev. 0 to Rev. A

Change to Features Section ............................................................. 1

Change to I

Changes to Figure 3 ........................................................................ 10

Changes to Figure 5 ........................................................................ 11

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

Added Automotive Products Section........................................... 21

7/10—Revision 0: Initial Version

Parameter, Table 2 ..................................................... 5

SS

Absolute Maximum Ratings ............................................................9

ESD Caution...................................................................................9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 12

Test Circuits ..................................................................................... 16

Terminology .................................................................................... 18

Trench Isolation .............................................................................. 19

Applications Information .............................................................. 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

Rev. B | Page 2 of 24

Data Sheet ADG5408/ADG5409

15

18

22

Ω max

VDD = +13.5 V, VSS = −13.5 V

±0.25

±1

±7

nA max

±0.4

±4

±30

nA max

217

258

292

ns max

VS = 10 V; see Figure 32

tON (EN)

140

ns typ

RL = 300 Ω, CL = 35 pF

ADG5409

50

pF typ

VS = 0 V, f = 1 MHz

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance, RON 13.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 26

On-Resistance Match Between

Channels, ∆R

ON

0.3 Ω typ V

= ±10 V, IS = −10 mA

S

0.8 1.3 1.4 Ω max
On-Resistance Flatness, R

1.8 Ω typ VS = ±10 V, IS = −10 mA

FL AT (ON)

2.2 2.6 3 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off ) ±0.05 nA typ VS = ±10 V, VD = 10 V; see Figure 29

Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = ±10 V, VD = 10 V; see Figure 29
±0.4 ±4 ±30 nA max
Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 25

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

GND

or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

170 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

175 213 242 ns max VS = 10 V; see Figure 34
t

(EN) 130 ns typ RL = 300 Ω, CL = 35 pF

OFF

161 183 198 ns max VS = 10 V; see Figure 34
Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF

16 ns min VS1 = VS2 = 10 V; see Figure 33

Charge Injection, Q

115 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;

INJ

see Figure 35

Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 28

Channel-to-Channel Crosstalk −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 27

Total Harmonic Distortion + Noise 0.01 % typ RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz;

see Figure 30

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 31

ADG5408 50 MHz typ
ADG5409 87 MHz typ

Insertion Loss 0.9 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Figure 31
CS (Off ) 15 pF typ VS = 0 V, f = 1 MHz
CD (Off )

ADG5408 102 pF typ VS = 0 V, f = 1 MHz

Rev. B | Page 3 of 24

ADG5408/ADG5409 Data Sheet

DIGITAL INPUTS

11

ns min

VS1 = VS2 = 10 V; see Figure 33

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

CD (On), CS (On)

ADG5408 133 pF typ VS = 0 V, f = 1 MHz
ADG5409 81 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 µA typ Digital inputs = 0 V or VDD

55 70 µA max

ISS 0.001 µA typ Digital inputs = 0 V or VDD

1 µA max

VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance, RON 12.5 Ω typ VS = ±15 V, IS = −10 mA; see Figure 26
14 17 21 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between

Channels, ∆R

ON

0.8 1.3 1.4 Ω max
On-Resistance Flatness, R

FL AT (ON)

2.7 3.1 3.5 Ω max

LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off ) ±0.1 nA typ VS = ±15 V, VD = 15 V; see Figure 29
±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off ) ±0.15 nA typ VS = ±15 V, VD = 15 V; see Figure 29
±0.4 ±4 ±30 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±15 V; see Figure 25
±0.4 ±4 ±30 nA max

0.3 Ω typ V

= ±15 V, IS = −10 mA

S

2.3 Ω typ VS = ±15 V, IS = −10 mA

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t
207 237 262 ns max VS = 10 V; see Figure 32
tON (EN) 140 ns typ RL = 300 Ω, CL = 35 pF
165 194 218 ns max VS = 10 V; see Figure 34
t

(EN) 133 ns typ RL = 300 Ω, CL = 35 pF

OFF

153 174 189 ns max VS = 10 V; see Figure 34
Break-Before-Make Time Delay, tD 38 ns typ RL = 300 Ω, CL = 35 pF

Charge Injection, Q

Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Channel-to-Channel Crosstalk −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

160 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

155 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see

INJ

GND

or VDD

Figure 35

Figure 28

see Figure 27

Rev. B | Page 4 of 24

Data Sheet ADG5408/ADG5409

1 µA max

Input Current, I

or I

0.002

µA typ

VIN = V

or VDD

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Total Harmonic Distortion + Noise 0.012 % typ RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;

see Figure 30

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 31

ADG5408 50 MHz typ
ADG5409 88 MHz typ

Insertion Loss 0.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 31
CS (Off ) 17 pF typ VS = 0 V, f = 1 MHz
CD (Off )

ADG5408 98 pF typ VS = 0 V, f = 1 MHz
ADG5409 48 pF typ VS = 0 V, f = 1 MHz

CD (On), CS (On)

ADG5408 128 pF typ VS = 0 V, f = 1 MHz
ADG5409 80 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 µA typ Digital inputs = 0 V or VDD

70 110 µA max

ISS 0.001 µA typ Digital inputs = 0 V or VDD

VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance, RON 26 Ω typ VS = 0 V to 10 V, IS = −10 mA; see

Figure 26
30 36 42 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between

Channels, ∆R

ON

0.3 Ω typ V

1 1.5 1.6 Ω max
On-Resistance Flatness, R

5.5 Ω typ VS = 0 V to 10 V, IS = −10 mA

FL AT (ON)

6.5 8 12 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see

±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see

±0.4 ±4 ±30 nA max
Channel On Leakage, ID (On), IS (On) ±0.05 nA typ VS = VD = 1 V/10 V; see Figure 25
±0.4 ±4 ±30 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

2.0 V min

INH

0.8 V max

INL

INH

±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

= 0 V to 10 V, IS = −10 mA

S

Figure 29

Figure 29

GND

Rev. B | Page 5 of 24

ADG5408/ADG5409 Data Sheet

276

345

397

ns max

VS = 8 V; see Figure 34

4.3

5.5

6.5

Ω max

Source Off Leakage, IS (Off )

±0.1

nA typ

VS = 1 V/30 V, VD = 30 V/1 V; see

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

DYNAMIC CHARACTERISTICS1

Transition Time, t
321 388 430 ns max VS = 8 V; see Figure 32
tON (EN) 215 ns typ RL = 300 Ω, CL = 35 pF

t

(EN) 134 ns typ RL = 300 Ω, CL = 35 pF

OFF

161 187 209 ns max VS = 8 V; see Figure 34
Break-Before-Make Time Delay, tD 118 ns typ RL = 300 Ω, CL = 35 pF

55 ns min VS1 = VS2 = 8 V; see Figure 33

Charge Injection, Q

Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Channel-to-Channel Crosstalk −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Total Harmonic Distortion + Noise 0.1 % typ RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz;

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 31
ADG5408 35 MHz typ
ADG5409 74 MHz typ

Insertion Loss −1.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

CS (Off ) 22 pF typ VS = 6 V, f = 1 MHz
CD (Off )

ADG5408 119 pF typ VS = 6 V, f = 1 MHz
ADG5409 59 pF typ VS = 6 V, f = 1 MHz

CD (On), CS (On)

ADG5408 146 pF typ VS = 6 V, f = 1 MHz
ADG5409 86 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 µA typ Digital inputs = 0 V or VDD

50 65 µA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

230 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

45 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see

INJ

Figure 35

see Figure 28

see Figure 27

see Figure 30

see Figure 31

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance, RON 14.5 Ω typ VS = 0 V to 30 V, IS = −10 mA; see

16 19 23 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between

Channels, ∆R

0.8 1.3 1.4 Ω max

On-Resistance Flatness, R

LEAKAGE CURRENTS VDD =39.6 V, VSS = 0 V

±0.25 ±1 ±7 nA max

ON

Figure 26

0.3 Ω typ V

3.5 Ω typ VS = 0 V to 30 V, IS = −10 mA

FL AT (ON)

= 0 V to 30 V, IS = −10 mA

S

Figure 29

Rev. B | Page 6 of 24

Data Sheet ADG5408/ADG5409

Input Low Voltage, V

0.8

V max

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Drain Off Leakage, ID (Off ) ±0.15 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see

Figure 29
±0.4 ±4 ±30 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = 1 V/30 V; see Figure 25
±0.4 ±4 ±30 nA max

DIGITAL INPUTS

Input High Voltage, V

Input Current, I

INL

±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t
242 257 281 ns max VS = 18 V; see Figure 32
tON (EN) 160 ns typ RL = 300 Ω, CL = 35 pF
195 219 237 ns max VS = 18 V; see Figure 34
t

(EN) 147 ns typ RL = 300 Ω, CL = 35 pF

OFF

184 184 190 ns max VS = 18 V; see Figure 34
Break-Before-Make Time Delay, tD 53 ns typ RL = 300 Ω, CL = 35 pF

17 ns min VS1 = VS2 = 18 V; see Figure 33

Charge Injection, Q

Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Channel-to-Channel Crosstalk −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Total Harmonic Distortion + Noise 0.4 % typ RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz;

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 31

ADG5408 45 MHz typ
ADG5409 76 MHz typ

Insertion Loss −1 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

CS (Off ) 18 pF typ VS = 18 V, f = 1 MH z
CD (Off )

ADG5408 120 pF typ VS = 18 V, f = 1 MH z
ADG5409 60 pF typ VS = 18 V, f = 1 MH z

CD (On), CS (On)

ADG5408 137 pF typ VS = 18 V, f = 1 MH z
ADG5409 80 pF typ VS = 18 V, f = 1 MH z

POWER REQUIREMENTS VDD = 39.6 V

IDD 80 µA typ Digital inputs = 0 V or VDD

100 130 µA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

2.0 V min

INH

INL

or I

0.002 µA typ VIN = V

INH

187 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

150 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF;

INJ

GND

or VDD

see Figure 35

see Figure 28

see Figure 27

see Figure 30

see Figure 31

Rev. B | Page 7 of 24

ADG5408/ADG5409 Data Sheet

LFCSP (θJA = 30.4°C/W)

136

50

16

mA maximum

CONTINUOUS CURRENT PER CHANNEL, Sx OR D

Table 5. ADG5408

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR D

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 100 44 16 mA maximum
LFCSP (θJA = 30.4°C/W) 170 54 16 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 106 45 16 mA maximum
LFCSP (θJA = 30.4°C/W) 178 55 16 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 81 39 15 mA maximum
LFCSP (θJA = 30.4°C/W) 140 51 16 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 104 44 16 mA maximum
LFCSP (θJA = 30.4°C/W) 175 55 16 mA maximum

Table 6. ADG5409

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR D

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 75 37 15 mA maximum
LFCSP (θJA = 30.4°C/W) 130 49 16 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 79 38 15 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 60 32 14 mA maximum
LFCSP (θJA = 30.4°C/W) 105 44 16 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 78 38 15 mA maximum
LFCSP (θJA = 30.4°C/W) 133 50 16 mA maximum

Rev. B | Page 8 of 24

Data Sheet ADG5408/ADG5409

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Peak Current, Sx or D Pins

ADG5408 370 mA (pulsed at 1 ms, 10%

duty cycle maximum)

ADG5409 275 mA (pulsed at 1 ms, 10%

duty cycle maximum)
Continuous Current, Sx or D2 Data + 15%
Temperature Range

Operating −40°C to +125°C

Storage −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θJA

16-Lead TSSOP (4-Layer

Board)

16-Lead LFCSP (4-Layer

Board)

Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at the Ax, EN, Sx, and D pins are clamped by internal diodes.

Limit current to the maximum ratings given.

2

See Table 5.

112.6°C/W

30.4°C/W

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any
one time.

ESD CAUTION

Rev. B | Page 9 of 24

ADG5408/ADG5409 Data Sheet

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

EN

V

SS

S1

S4

S3

S2

A0

A2
GND
V

DD

S7

D S8

S6

S5

A1

ADG5408

TOP VIEW

(Not to S cale)

09206-002

1V

SS

NOTES

1. THE EXPOSED PAD IS
CONNECTED I NTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JO INTS AND MAXIM UM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V

SS

.

2

S1

3

S2

4S3

11

V

DD

12 GND

10 S5
9 S6

5S4

6D

7S8

8S7

15

A0

16

EN

14

A1

13

A2

09206-003

TOP VIEW

(Not to S cale)

ADG5408

3 1 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
8 6 D

Drain Terminal. This pin can be an input or an output.

X

X

X

0

None

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. ADG5408 Pin Configuration (TSSOP)

Figure 3. ADG5408 Pin Configuration (LFCSP)

Table 8. ADG5408 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,

Ax logic inputs determine on switches.

to ground.
4 2 S1 Source Terminal 1. This pin can be an input or an output.
5 3 S2 Source Terminal 2. This pin can be an input or an output.
6 4 S3 Source Terminal 3. This pin can be an input or an output.
7 5 S4 Source Terminal 4. This pin can be an input or an output.

9 7 S8 Source Terminal 8. This pin can be an input or an output.
10 8 S7 Source Terminal 7. This pin can be an input or an output.
11 9 S6 Source Terminal 6. This pin can be an input or an output.
12 10 S5 Source Terminal 5. This pin can be an input or an output.
13 11 VDD Most Positive Power Supply Potential.
14 12 GND Ground (0 V) Reference.
15 13 A2 Logic Control Input.
16 14 A1 Logic Control Input.
EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and

maximum thermal capability, it is recommended that the pad be soldered to the substrate, V

SS

.

Table 9. ADG5408 Truth Table

A2 A1 A0 EN On Switch

0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8

Rev. B | Page 10 of 24

Data Sheet ADG5408/ADG5409

S1A

S4A

S3A

S2A

1V

SS

2

S1A

3

S2A

4S3A

11

S1B

12 V

DD

10

S2B

9 S3B

5

S4A

6
DA

7
DB

8

S4B

15

A0

16

EN

14

A1

13

GND

NOTES

1. THE EXPOSED PAD IS
CONNECTED I NTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JO INTS AND MAXIM UM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V

SS

.

09206-005

TOP VIEW

(Not to S cale)

ADG5409

6 4 S3A

Source Terminal 3A. This pin can be an input or an output.

1

1

1

4

1

A0

2

EN

3

V

SS

4

ADG5409

TOP VIEW

5

(Not to S cale)

6

7

8

DA DB

16

A1

15

GND

14

V

DD

13

S1B

12

S2B

11

S3B

10

S4B

9

09206-004

Figure 4. ADG5409 Pin Configuration (TSSOP)

Figure 5. ADG5409 Pin Configuration (LFCSP)

Table 10. ADG5409 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,

Ax logic inputs determine on switches.

3 1 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected

to ground.
4 2 S1A Source Terminal 1A. This pin can be an input or an output.
5 3 S2A Source Terminal 2A. This pin can be an input or an output.

7 5 S4A Source Terminal 4A. This pin can be an input or an output.
8 6 DA Drain Terminal A. This pin can be an input or an output.
9 7 DB Drain Terminal B. This pin can be an input or an output.
10 8 S4B Source Terminal 4B. This pin can be an input or an output.
11 9 S3B Source Terminal 3B. This pin can be an input or an output.
12 10 S2B Source Terminal 2B. This pin can be an input or an output.
13 11 S1B Source Terminal 1B. This pin can be an input or an output.
14 12 VDD Most Positive Power Supply Potential.
15 13 GND Ground (0 V) Reference.
16 14 A1 Logic Control Input.
EP Exposed

Pad

The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, V

.

SS

Table 11. ADG5409 Truth Table

A1 A0 EN On Switch Pair

X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3

Rev. B | Page 11 of 24

ADG5408/ADG5409 Data Sheet

0

5

10

15

20

25

–18 –14 –10 –6 –2 2 6 10 14 18

ON RESISTANCE (Ω)

VS, VD (V)

TA = 25°C

V

DD

= +9V

V

SS

= –9V

V

DD

= +10V

V

SS

= –10V

VDD = +11V
V

SS

= –11V

V

DD

= +13.5V

V

SS

= –13.5V

V

DD

= +15V

V

SS

= –15V

V

DD

= +16.5V

V

SS

= –16.5V

09206-028

0

2

4

6

8

10

12

14

16

–25

–20 –15 –10 –5 0 5 10 15 20 25

ON RESISTANCE (Ω)

V

S

, VD (V)

TA = 25°C

V

DD

= +22V

V

SS

= –22V

VDD = +20V
V

SS

= –20V

V

DD

= +18V

V

SS

= –18V

09206-029

0

–5

–10

–15

–20

–25

–30

–35

0 –2 –4 –6 –8 –10 –12 –14

ON RESISTANCE (Ω)

VS, VD (V)

TA = 25°C

VDD = 9V
VSS = 0V

VDD = 10V
VSS = 0V

VDD = 10.8V
VSS = 0V

VDD = 11V
VSS = 0V

VDD = 12V
VSS = 0V

VDD = 13.2V
VSS = 0V

09206-023

0

2

4

6

8

10

12

14

16

0 5 10 15 20 25 30 35 40 45

ON RESISTANCE (Ω)

V

S

, V

D

(V)

T

A

= 25°C

V

DD

= 39.6V

V

SS

= 0V

V

DD

= 36V

V

SS

= 0V

V

DD

= 32.4V

VSS = 0V

09206-027

0

5

10

15

20

25

–15 –10 –5 0 5 10 15

ON RESISTANCE (Ω)

VS, VD (V)

VDD = +15V
VSS = –15V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09206-030

0

5

10

15

20

25

–20 –15 –10

–5 0 5 10 15 20

ON RESISTANCE (Ω)

TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

V

S

, VD (V)

VDD = +20V
VSS = –20V

09206-024

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. RON as a Function of VS, VD (Dual Supply)

Figure 7. RON as a Function of VS, VD (Dual Supply)

Figure 9. RON as a Function of VS, VD (Single Supply)

Figure 10. RON as a Function of VS (VD) for Different Temperatures,

±15 V Dual Supply

Figure 8. R

as a Function of VS, VD (Single Supply)

ON

Figure 11. RON as a Function of VS (VD) for Different Temperatures,

±20 V Dual Supply

Rev. B | Page 12 of 24

Data Sheet ADG5408/ADG5409

0

5

10

15

20

25

30

35

40

0 2 4 6 8 10 12

V

S

, V

D

(V)

ON RESISTANCE (Ω)

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

V

DD

= 12V

V

SS

= 0V

09206-031

0

5

10

15

20

25

0 5 10 15 20 25 30 35 40

ON RESISTANCE (Ω)

TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

V

S

, VD (V)

VDD = 36V
V

SS

= 0V

09206-032

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.5

–1.0

0

–2.0

–0.5

–1.5

V

DD

= +15V

V

SS

= –15V

V

BIAS

= +10V/–10V

ID, IS (ON) + +

ID, IS (ON) – –

ID (OFF) + –

IS (OFF) + –

IS (OFF) – +

ID (OFF) – +

09206-034

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

1

–1

0

–3

–2

VDD = +20V
V

SS

= –20V

V

BIAS

= +15V/–15V

I

D

, IS (ON) + +

ID, IS (ON) – –

ID (OFF) + –

I

S

(OFF) + –

I

S

(OFF) – +

ID (OFF) – +

09206-035

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.5

–1.0

0

–2.0

–0.5

–1.5

V

DD

= 12V

V

SS

= 0V

V

BIAS

= 1V/10V

I

D

, I

S

(ON) + +

I

D

, I

S

(ON) – –

ID (OFF) + –

I

S

(OFF) + –

ID (OFF) – +

I

S

(OFF) – +

09206-033

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

1

–1

0

–3

–2

VDD = +36V
V

SS

= 0V

V

BIAS

= 1V/30V

ID, I

S

(ON) + +

ID, I

S

(ON) – –

I

D

(OFF) + –

IS (OFF) + –

IS (OFF) – +

ID (OFF) – +

09206-036

Figure 12. RON as a Function of VS (VD) for Different Temperatures,

12 V Single Supply

Figure 13. RON as a Function of VD (VS) for Different Temperatures,

36 V Single Supply

Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply

Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply

Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply

Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply

Rev. B | Page 13 of 24

ADG5408/ADG5409 Data Sheet

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

OFF ISOLATION (dB)

FREQUENCY (Hz)

100k10k 1M 10M 100M 1G1k

TA = 25°C
VDD = +15V
VSS = –15V

09206-021

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

CROSSTALK (dB)

FREQUENCY (Hz)

10k 100k 1M 10M 100M 1G

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

09206-026

0

50

100

150

200

250

300

20 10 0 10 20 30 40

CHARGE INJECT ION (pC)

T

A

= 25°C

V

DD

= +20V

V

SS

= –20V

V

DD

= +15V

VSS = –15V

V

DD

= +36V

V

SS

= 0V

V

DD

= +12V

VSS = 0V

V

S

(V)

09206-019

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

ACPSRR (dB)

FREQUENCY (Hz)

1k 1M 10M10k 100k

TA = 25°C
V

DD

= +15V

V

SS

= –15V

NO DECOUPL ING
CAPACITORS

DECOUPLING
CAPACITORS

09206-022

0

0.02

0.04

0.06

0.08

0.10

0.12

0 5 10 15 20

THD + N (%)

FREQUENCY (kHz)

VDD = 12V, VSS = 0V, VS = 6V p-p

VDD = 36V, VSS = 0V, VS = 18V p-p

VDD = 15V, VSS = 15V, VS = 15V p-p

V

DD

= 20V, VSS = 20V, VS = 20V p-p

LOAD = 1kΩ

T

A

= 25°C

09206-025

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

INSERTION LOSS (dB)

FREQUENCY (Hz)

10k 100k 1M 10M 100M1k 1G

ADG5408

ADG5409

TA = 25°C
V

DD

= +15V

V

SS

= –15V

09206-020

Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply

Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply

Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply

Figure 22. THD + N vs. Frequency

Figure 20. Charge Injection vs. Source Voltage

Figure 23. Bandwidth

Rev. B | Page 14 of 24

Data Sheet ADG5408/ADG5409

0

50

100

150

200

250

300

350

400

–40 –20 0

20 40 60 80 100 120

TIME (ns)

V

DD

= +12V, V

SS

= 0V

VDD = +15V, V

SS

= –15V

V

DD

= +36V, V

SS

= 0V

VDD = +20V, V

SS

= –20V

TEMPERATURE (°C)

09206-018

Figure 24. t

Times vs. Temperature

TRANSITION

Rev. B | Page 15 of 24

ADG5408/ADG5409 Data Sheet

V

V

V

V

V

V

V

V

V

V

TEST CIRCUITS

IS(OFF) ID (OFF)

Sx D

A A

NC

Sx Dx

ID (ON)

A

NETWO RK
ANALYZER

V

OUT

R

L

10kΩ

V

D

09206-007

AUDIO PRECISION

R

S

V

S

V p-p

V

OUT

NETWORK

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

09206-015

V

NC = NO CONNECT

D

09206-008

Figure 25. On Leakage

0.1µF

I

DS

IN

V1

Sx D

S

RON = V1/I

DS

09206-006

IN

Figure 26. On Resistance

DD

0.1µF

V

DD

R

L

50Ω

V

S

S1

S2

GND

SS

0.1µF

V

SS

D

R

L

50Ω

0.1µF

S

Figure 29. Off Leakage

DD

SS

0.1µF

V

V

DD

SS

Sx

D

GND

Figure 30. THD + Noise Figure

V

DD

SS

0.1µF

V

V

DD

SS

Sx

D

GND

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

Figure 27. Channel-to-Channel Crosstalk

0.1µF

DD

V

DDVSS

0.1µF

Sx

D

GND

OFF ISOLATION = 20 log

50Ω

SS

Figure 28. Off Isolation

WITH SWITCH

V

V

OUT

V

S

09206-014

INSERTION LOSS = 20 log

OUT

WITHOUT SWITCH

V

OUT

09206-017

Figure 31. Bandwidth

NETWORK

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

09206-013

Rev. B | Page 16 of 24

Data Sheet ADG5408/ADG5409

3V

0V

OUTPUT

t

r

< 20ns

t

f

< 20ns
ADDRESS
DRIVE (V

IN

)

t

TRANSITION

t

TRANSITION

50% 50%

90%

90%

OUTPUT

ADG5408*

A0
A1
A2

50Ω

300Ω

GND

S1

S2 TO S7

S8

D

35pF

V

IN

2.4V EN

V

DD

V

SS

V

DD

V

SS

V

S1

V

S8

*

SIMIL AR CONNECTION FOR ADG5409.

09206-009

OUTPUT

ADG5408*

A0
A1
A2

50Ω

300Ω

GND

S1

S2 TO S7

S8

D

35pF

V

IN

2.4V

EN

V

DD

V

SS

V

DD

V

SS

V

S

*

SIMIL AR CONNECTION FOR ADG5409.

3V

0V

OUTPUT

80% 80%

ADDRESS
DRIVE (V

IN

)

t

D

09206-010

OUTPUT

ADG5408*

A0
A1
A2

50Ω

300Ω

GND

S1

S2 TO S8

D

35pF

V

IN

EN

V

DD

V

SS

V

DD

V

SS

V

S

*SIMIL AR CONNECTION FOR ADG5409.

3V

0V

OUTPUT

50% 50%

t

OFF

(EN)

t

ON

(EN)

0.9V

O

0.9V

O

ENABLE
DRIVE (V

IN

)

09206-011

3V

V

IN

V

OUT

Q

INJ

= CL × ΔV

OUT

ΔV

OUT

DSx

EN

GND

C

L

1nF

V

OUT

V

IN

R

S

V

S

V

DD

V

SS

V

DD

V

SS

A0
A1
A2

ADG5408*

*SIMIL AR CONNECTION FOR ADG5409.

09206-012

Figure 32. Address to Output Switching Times, t

Figure 33. Break-Before-Make Delay, t

TRANSITION

D

(EN), t

(EN)

OFF

Figure 34. Enable Delay, t

Figure 35. Charge Injection

Rev. B | Page 17 of 24

ON

ADG5408/ADG5409 Data Sheet

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

V

, VS

D

V

and VS represent the analog voltage on Terminal D and

D

Terminal S, respectively.

R

ON

R

is the ohmic resistance between Terminal D and

ON

Terminal S.

∆R

ON

∆R

represents the difference between the RON of any two

ON

channels.

R

FL AT (ON)

The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by R

(Off)

I

S

I

(Off) is the source leakage current with the switch off.

S

I

(Off)

D

I

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

I

D

I

(On) and IS (On) represent the channel leakage currents with

D

FLAT (ON)

.

the switch on.

V

INL

V

is the maximum input voltage for Logic 0.

INL

V

INH

V

is the minimum input voltage for Logic 1.

INH

I

, I

INL

INH

I

INL

and I

represent the low and high input currents of the

INH

digital inputs.

C

(Off)

D

C

(Off) represents the off switch drain capacitance, which is

D

measured with reference to ground.

C

(Off)

S

C

(Off) represents the off switch source capacitance, which is

S

measured with reference to ground.

C

(On), CS (On)

D

C

(On) and CS (On) represent on switch capacitances, which

D

are measured with reference to ground.

C

IN

C

represents digital input capacitance.

IN

t

(EN)

ON

t

(EN) represents the delay time between the 50% and 90%

ON

points of the digital input and switch on condition.

t

(EN)

OFF

t

(EN) represents the delay time between the 50% and 90%

OFF

points of the digital input and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

t

D

t

represents the off time measured between the 80% point of

D

both switches when switching from one address state to
an other.

Off Isolation

Off isolation is a measure of unwanted signal coupling through
an off channel.

Charge Injection

Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated
by 3 dB.

On Response

On response is the frequency response of the on switch.

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.

AC Power Supply Rejection Ratio (ACPSRR)

ACPSRR is a measure of the ability of a part to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR.

Rev. B | Page 18 of 24

Data Sheet ADG5408/ADG5409

09206-016

NMOS PMOS

P-WELL N-WELL

BURIED OXI DE LAYER

HANDLE WAFE R

TRENCH

TRENCH ISOLATION

In the ADG5408/ADG5409, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.

Figure 36. Trench Isolation

Rev. B | Page 19 of 24

ADG5408/ADG5409 Data Sheet

APPLICATIONS INFORMATION

The ADG54xx family switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is
an undesirable high current state that can lead to device failure
and persist until the power supply is turned off. The ADG5408/
ADG5409 high voltage switches allow single-supply operation

from 9 V to 40 V and dual-supply operation from ±9 V to
±22 V. The ADG5408/ADG5409 (as well as select devices
within the same family) achieve an 8 kV human body model
ESD rating that provides a robust solution eliminating the need
for separate protect circuitry designs in some applications.

Rev. B | Page 20 of 24

Data Sheet ADG5408/ADG5409

16

9

81

PIN 1

SEATING
PLANE

8°
0°

4.50

4.40

4.30

6.40
BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20
MAX

0.20

0.09

0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLI ANT TO JEDEC STANDARDS MO-153-AB

2.70

2.60 SQ

2.50

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

1

0.65

BSC

BOTTOMVIEWTOP VIEW

16

5

8

9

12

13

4

EXPOSED

PAD

PIN 1
INDICATOR

4.10

4.00 SQ

3.90

0.45

0.40

0.35

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

0.35

0.30

0.25

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

08-16-2010-C

OUTLINE DIMENSIONS

Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

Rev. B | Page 21 of 24

ADG5408/ADG5409 Data Sheet

Model1

Temperature Range

Package Description

Package Option

ORDERING GUIDE

ADG5408BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5408BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5408BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17
ADG5409BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5409BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5409BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17

1

Z = RoHS Compliant Part.

Rev. B | Page 22 of 24

Data Sheet ADG5408/ADG5409

NOTES

Rev. B | Page 23 of 24

ADG5408/ADG5409 Data Sheet

©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D09206-0-5/12(B)

Rev. B | Page 24 of 24