Datasheet ADG5236 Datasheet (ANALOG DEVICES)

High Voltage Latch-Up Proof,

Data Sheet

FEATURES

Latch-up proof

2.5 pF off source capacitance
12 pF off drain capacitance

−0.6 pC charge injection
Low leakage: 0.4 nA maximum at 85°C
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V

to VDD analog signal range

SS

APPLICATIONS

Automatic test equipment
Data acquisition
Instrumentation
Avio nics
Audio and video switching
Communication systems

Dual SPDT Switches

ADG5236

FUNCTIONAL BLOCK DIAGRAMS

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

S1A

D1

S1B

ADG5236

Figure 1. TSSOP Package

ADG5236

D1

D2

S2A
D2
S2B

09769-001

GENERAL DESCRIPTION

The ADG5236 is a monolithic CMOS device containing two
independently selectable single-pole/double throw (SPDT)
switches. An EN input on the LFCSP package enables or
disables the device. When disabled, all channels switch off. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the device suitable for video signal switching.

LOGIC

IN2 ENIN1

SWITCHES SHOWN F OR A LOGIC 1 INPUT.

Figure 2. LFCSP Package

09769-002

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel
transistors thereby preventing latch-up even under severe
overvoltage conditions.

2. Ultralow Capacitance and <1 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5236 can be operated from dual supplies up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5236 can be operated from a single rail power supply

up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

V

INH

6. No V

= 2.0 V, V

Logic Power Supply Required.

L

= 0.8 V.

INL

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

ADG5236 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 4

12 V Single Supply ........................................................................ 5

36 V Single Supply ........................................................................ 6

Continuous Current per Channel, Sx or Dx ............................. 7

REVISION HISTORY

4/12—Rev. 0 to Rev. A

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 19

7/11—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions ............................9

Truth Tables for Switches .............................................................9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 14

Terminology .................................................................................... 16

Trench Isolation .............................................................................. 17

Applications Information .............................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

Data Sheet ADG5236

50

65

70

Ω max

0.2

0.4

1.2

Digital Input Capacitance, CIN

3

pF typ

30

ns min

VS1 = VS2 = 10 V, see Figure 31

Channel-to-Channel Crosstalk

−85

dB typ

RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CD (Off )

12

pF typ

VS = 0 V, f = 1 MHz

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance, RON

On-Resistance Match

Between Channels, ∆R

On-Resistance Flatness, R

ON

FL AT (ON)

VDD to VSS
160
200 250 280

1.4

8 9 10
38

V max
Ω typ VS = ±10 V, IS = −1 mA, see Figure 25
Ω max VDD = +13.5 V, VSS = −13.5 V
Ω typ VS = ±10 V, IS = −1 mA

Ω max
Ω typ VS = ±10 V, IS = −1 mA

LEAKAGE CURRENTS

Source Off Leakage, IS (Off )

Drain Off Leakage, ID (Off )

Channel On Leakage, ID (On), IS (On)

0.01

0.1 0.2 0.4

0.01

0.1 0.4 1.2

0.02

VDD = +16.5 V, VSS = −16.5 V
nA typ

V

= ±10 V, VD = 10 V, see Figure 27

S

nA max
nA typ

V

= ±10 V, VD = 10 V, see Figure 27

S

nA max
nA typ VS = VD = ±10 V, see Figure 24
nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

GND

or VDD

±0.1 µA max

DYNAMIC CHARACTERISTICS1

Transition Time, t

150 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

230 280 315 ns max VS = 10 V, see Figure 30
tON 170 ns typ RL = 300 Ω, CL = 35 pF
215 265 300 ns max VS = 10 V, see Figure 32
t

160 ns typ RL = 300 Ω, CL = 35 pF

OFF

185 205 225 ns max VS = 10 V, see Figure 32
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF

Charge Injection, Q

−0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF,

INJ

see Figure 33

Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

see Figure 28

−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CS (Off ) 2.5 pF typ VS = 0 V, f = 1 MHz

CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz

see Figure 26

see Figure 29

Rev. A | Page 3 of 20

ADG5236 Data Sheet

1

µA max

0.1

0.4

1.2

±0.1

µA max

Channel-to-Channel Crosstalk

−85

dB typ

RL = 50 Ω, CL = 5 pF, f = 1 MHz,

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD

ISS

VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance, RON

On-Resistance Match

Between Channels, ∆R

On-Resistance Flatness, R

LEAKAGE CURRENTS

Source Off Leakage, IS (Off )

Drain Off Leakage, ID (Off )

Channel On Leakage, ID (On), IS (On)

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

or I

INL

ON

FL AT (ON)

2.0 V min

INH

0.8 V max

INL

0.002 µA typ VIN = V

INH

45
55 70

0.001

VDD to VSS
140
160 200 230

1.3

8 9 10
33
45 55 60

0.01

0.1 0.2 0.4

0.01

0.02

0.2 0.4 1.2

µA typ Digital inputs = 0 V or VDD
µA max
µA typ Digital inputs = 0 V or VDD

V max
Ω typ VS = ±15 V, IS = −1 mA, see Figure 25
Ω max VDD = +18 V, VSS = −18 V
Ω typ VS = ±15 V, IS = −1 mA

Ω max
Ω typ VS = ±15 V, IS = −1 mA
Ω max
VDD = +22 V, VSS = −22 V
nA typ

V

= ±15 V, VD = 15 V, see Figure 27

S

nA max
nA typ

V

= ±15 V, VD = 15 V, see Figure 27

S

nA max
nA typ VS = VD = ±15 V, see Figure 24
nA max

or VDD

GND

Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t
210 260 290 ns max VS = 10 V, see Figure 30
tON 150 ns typ RL = 300 Ω, CL = 35 pF
190 235 267 ns max VS = 10 V, see Figure 32
t

155 ns typ RL = 300 Ω, CL = 35 pF

OFF

180 200 215 ns max VS = 10 V, see Figure 32
Break-Before-Make Time Delay, tD 60 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V, see Figure 31

Charge Injection, Q

Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

150 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

−0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see

INJ

Figure 33

see Figure 28

see Figure 26

see Figure 29

Rev. A | Page 4 of 20

Data Sheet ADG5236

1

3

0.1

0.2

0.4

nA max

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

CS (Off ) 2.5 pF typ VS = 0 V, f = 1 MHz
CD (Off ) 12 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD

ISS

VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance, RON

On-Resistance Match

Between Channels, ∆R

On-Resistance Flatness, R

LEAKAGE CURRENTS

Source Off Leakage, IS (Off )

ON

FL AT (ON)

50
70 110

0.001

0 V to VDD
350

500 610 700

20 21 22
145
280 335 370

0.01

µA typ Digital inputs = 0 V or VDD
µA max
µA typ Digital inputs = 0 V or VDD
µA max

V max
Ω typ VS = 0 V to 10 V, IS = −1 mA, see

Figure 25
Ω max VDD = 10.8 V, VSS = 0 V
Ω typ VS = 0 V to 10 V, IS = −1 mA

Ω max
Ω typ VS = 0 V to 10 V, IS = −1 mA
Ω max
VDD = 13.2 V, VSS = 0 V
nA typ VS = 1 V/10 V, VD = 10 V/1 V,

see Figure 27

Drain Off Leakage, ID (Off )

0.01

nA typ VS = 1 V/10 V, VD = 10 V/1 V,

see Figure 27

Channel On Leakage, ID (On), IS (On)

0.1 0.4 1.2

0.02

0.2 0.4 1.2

nA max
nA typ VS = VD = 1 V/10 V, see Figure 24
nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

GND

or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

220 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

390 430 490 ns max VS = 8 V, see Figure 30
tON 275 ns typ RL = 300 Ω, CL = 35 pF
380 440 510 ns max VS = 8 V, see Figure 32
t

160 ns typ RL = 300 Ω, CL = 35 pF

OFF

195 225 245 ns max VS = 8 V, see Figure 32
Break-Before-Make Time Delay, tD 145 ns typ RL = 300 Ω, CL = 35 pF

65 ns min VS1 = VS2 = 8 V, see Figure 31

Charge Injection, Q

−0.6 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see

INJ

Figure 33

Rev. A | Page 5 of 20

ADG5236 Data Sheet

−3 dB Bandwidth

185

MHz typ

RL = 50 Ω, CL = 5 pF, see Figure 29

VDD

9/40

V min/V max

GND = 0 V, VSS = 0 V

ANALOG SWITCH

Drain Off Leakage, ID (Off )

0.01

nA typ

VS = 1 V/30 V, VD = 30 V/1 V,

Input Current, I

or I

0.002

µA typ

VIN = V

or VDD

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

see Figure 28

Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

see Figure 26

Insertion Loss −11 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

see Figure 29
CS (Off ) 3 pF typ VS = 6 V, f = 1 MHz
CD (Off ) 16 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 16 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD

1

Guaranteed by design; not subject to production test.

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

40
65

µA typ Digital inputs = 0 V or VDD
µA max

Analog Signal Range
On Resistance, RON

0 V to VDD
150

V max
Ω typ VS = 0 V to 30 V, IS = −1 mA,

see Figure 25

On-Resistance Match

Between Channels, ∆R

On-Resistance Flatness, R

LEAKAGE CURRENTS

Source Off Leakage, IS (Off )

ON

FL AT( ON)

170 215 245

1.4

8 9 10
35
50 60 65

0.01

Ω max VDD = 32.4 V, VSS = 0 V
Ω typ VS = 0 V to 30 V, IS = −1 mA

Ω max
Ω typ VS = 0 V to 30 V, IS = −1 mA
Ω max
VDD = 39.6 V, VSS = 0 V
nA typ VS = 1 V/30 V, VD = 30 V/1 V,

see Figure 27

0.1 0.2 0.4

nA max

see Figure 27

Channel On Leakage, ID (On), IS (On)

0.1 0.4 1.2

0.02

0.2 0.4 1.2

nA max
nA typ VS = VD = 1 V/30 V, see Figure 24
nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

2.0 V min

INH

0.8 V max

INL

INH

GND

±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

180 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

250 275 305 ns max VS = 18 V, see Figure 30
tON 170 ns typ RL = 300 Ω, CL = 35 pF
225 265 295 ns max VS = 18 V, see Figure 32

Rev. A | Page 6 of 20

Data Sheet ADG5236

Charge Injection, Q

−0.6

pC typ

VS = 18 V, RS = 0 Ω, CL = 1 nF,

CD (On), CS (On)

15

pF typ

VS = 18 V, f = 1 MHz

TSSOP (θJA = 112.6°C/W)

24

7.4

2.8

mA max

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

t

170 ns typ RL = 300 Ω, CL = 35 pF

OFF

215 215 225 ns max VS = 18 V, see Figure 32
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF

35 ns min VS1 = VS2 = 18 V, see Figure 31

INJ

Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CS (Off ) 2.5 pF typ VS = 18 V, f = 1 MHz
CD (Off ) 12 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

IDD

85
100 130

µA typ Digital inputs = 0 V or VDD
µA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

see Figure 33

see Figure 28

see Figure 26

see Figure 29

CONTINUOUS CURRENT PER CHANNEL, SxA, SxB, OR Dx

Table 5.

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, SxA, SxB, or Dx

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 19 7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 30 7.7 2.8 mA max

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 21 7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 31 7.7 2.8 mA max

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 14 6.3 2.7 mA max
LFCSP (θJA = 30.4°C/W) 22.5 7.3 2.8 mA max

VDD = 36 V, VSS = 0 V

LFCSP (θJA = 30.4°C/W) 35 7.8 2.8 mA max

Rev. A | Page 7 of 20

ADG5236 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Peak Current, SxA, SxB, or Dx
Pin

Continuous Current, SxA, SxB,

2

or Dx

Temperature Range

Operating −40°C to +125°C
Storage −65°C to +150°C

Junction Temperature 150°C
Thermal Impedance, θJA

16-Lead TSSOP (4-Layer

Board)

16-Lead LFCSP 30.4°C/W

Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at the INx, SxA, SxB, and Dx pins are clamped by internal diodes.

Limit the current to the maximum ratings given.

2

See Table 5.

63 mA (pulsed at 1 ms,
10% duty cycle maximum)

Data + 15%

112°C/W

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any
one time.

ESD CAUTION

Rev. A | Page 8 of 20

Data Sheet ADG5236

IN1

1

S1A

2

D1

3

S1B

4

NC

16

NC

15

NC

14

V

DD

13

V

SS

5

S2B

12

GND

6

D2

11

NC

7

S2A

10

NC

8

IN2

9

NC = NO CONNECT

ADG5236

TOP VIEW

(Not to S cale)

09769-003

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

SS

.

2. NC = NO CONNECT.

1D1
2S1B
3

V

SS

4GND

11

V

DD

12 EN

10 S2B
9 D2

5
NC

6

IN2

7
NC

8

S2A

15

IN1

16

S1A

14

NC

13

NC

TOP VIEW

(Not to S cale)

ADG5236

09769-004

The exposed pad is connected internally. For increased reliability of the solder

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 IN1 Logic Control Input 1.
2 16 S1A Source Terminal 1A. This pin can be an input or output.
3 1 D1 Drain Terminal 1. This pin can be an input or output.
4 2 S1B Source Terminal 1B. This pin can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14 to 16 5, 7, 13, 14 NC No Connect. These pins are open.
9 6 IN2 Logic Control Input 2.
10 8 S2A Source Terminal 2A. This pin can be an input or output.
11 9 D2 Drain Terminal 2. This pin can be an input or output.
12 10 S2B Source Terminal 2B. This pin can be an input or output.
13 11 VDD Most Positive Power Supply Potential.
N/A1 12 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are

off. When this pin is high, the INx logic inputs determine the on switches.

N/A1 EP Exposed Pad Exposed Pad.

joints and maximum thermal capability, it is recommended that the pad be soldered to the

.

SS

1

N/A means not applicable.

substrate, V

TRUTH TABLES FOR SWITCHES

Table 8. TSSOP Truth Table

INx SxA SxB

0 Off On
1 On Off

Table 9. LFCSP Truth Table

EN INx SxA SxB

0 X1 Off Off
1 0 Off On
1 1 On Off

1

X means don’t care.

Rev. A | Page 9 of 20

ADG5236 Data Sheet

160

0

20

40

60

80

100

120

140

–25 –20 –15 –10 –5 0 5 10 15 20 25

ON RESISTANCE (Ω)

V

S

, VD (V)

T

A

= 25°C

V

DD

= +18V

V

SS

= –18V

V

DD

= +20V

V

SS

= –20V

V

DD

= +22V

V

SS

= –22V

09769-105

250

200

150

100

50

0

–20 –15 –10 –5 0 5 10 15 20

ON RESISTANCE (Ω)

VS, V

D

(V)

T

A

= 25°C

VDD = +9V
V

SS

= –9V

VDD = +13.2V
V

SS

= –13.2V
VDD = +15V
V

SS

= –15V

V

DD

= +16.5V

V

SS

= –16.5V

09769-106

500

450

400

350

300

250

200

150

100

50

0

0 1412108642

ON RESISTANCE (Ω)

VS, V

D

(V)

T

A

= 25°C

V

DD

= 9V

V

SS

= 0V

V

DD

= 10.8V

V

SS

= 0V

V

DD

= 12V

V

SS

= 0V

V

DD

= 13.2V

V

SS

= 0V

09769-107

160

140

120

100

80

60

40

20

0

0 403530252015105

ON RESISTANCE (Ω)

VS, VD (V)

T

A

= 25°C

V

DD

= 32.4V

V

SS

= 0V

V

DD

= 36V

V

SS

= 0V

V

DD

= 39.6V

V

SS

= 0V

09769-108

250

200

150

100

50

0

–15 –10 –5 0 5 10 15

ON RESISTANCE (Ω)

VS, VD (V)

VDD = +15V
V

SS

= –15V

TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09769-109

200

160

120

80

40

180

140

100

60

20

0

–20 –15 –10 –5 0 5 10 2015

ON RESISTANCE (Ω)

VS, VD (V)

VDD = +20V
V

SS

= –20V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09769-110

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. On Resistance vs. VS, VD (Dual Supply)

Figure 6. On Resistance vs. VS, VD (Dual Supply)

Figure 8. On Resistance vs. VS, VD (Single Supply)

Figure 9. On Resistance vs. VD or VS for Different Temperatures,

±15 V Dual Supply

Figure 7. On Resistance vs. VS, VD (Single Supply)

Figure 10. On Resistance vs. VD or VS for Different Temperatures,

±20 V Dual Supply

Rev. A | Page 10 of 20

Data Sheet ADG5236

500

400

300

200

100

450

340

250

150

50

0

0 2 4 6 8 10 12

ON RESISTANCE (Ω)

VS, VD (V)

VDD = 12V
V

SS

= 0V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09769-111

250

200

100

150

50

0

0 3530252015105

ON RESISTANCE (Ω)

VS, V

D

(V)

V

DD

= 36V

V

SS

= 0V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09769-112

10

–70

–60

–50

–40

–30

–20

–10

0

0 20 40 60 80 100 120

LEAKAGE CURRENT (pA)

TEMPERATURE (°C)

V

DD

= +15V

V

SS

= –15V

V

BIAS

= +10V/–10V

I

D

(OFF) – +

I

S

(OFF) – +

I

S

(OFF) + –

I

D

(OFF) + –

I

D,

I

S

(ON) + +

I

D,

IS (ON) – –

09769-113

0 20 40 60 80 100 120

TEMPERATURE (°C)

100

–200

–150

–100

–50

0

50

LEAKAGE CURRENT (pA)

VDD = +20V
V

SS

= –20V

V

BIAS

= +15V/–15V

I

D

(OFF) – +

I

S

(OFF) – +

I

S

(OFF) + –

I

D

(OFF) + –

I

D,

I

S

(ON) + +

I

D,

I

S

(ON) – –

09769-114

0 20 40 60 80 100 120

TEMPERATURE (°C)

40

20

–120

–100

–80

–60

–40

–20

0

LEAKAGE CURRENT (pA)

VDD = 12V
V

SS

= 0V

V

BIAS

= 1V/10V

I

D

(OFF) – +

I

S

(OFF) – +

I

S

(OFF) + –

I

D

(OFF) + –

I

D,IS

(ON) + +

I

D,

I

S

(ON) – –

09769-115

0 20 40 60 80 100 120

TEMPERATURE (°C)

50

–250

–200

–150

–100

–50

0

LEAKAGE CURRENT (pA)

VDD = 36V
V

SS

= 0V

V

BIAS

= 1V/30V

I

D

(OFF) – +

I

S

(OFF) – +

I

S

(OFF) + –

I

D

(OFF) + –

I

D,IS

(ON) + +

I

D,IS

(ON) – –

09769-116

Figure 11. On Resistance vs. VD or VS for Different Temperatures,

12 V Single Supply

Figure 12. On Resistance vs. VS or VD for Different Temperatures,

36 V Single Supply

Figure 14. Leakage Current vs. Temperature, ±20 V Single Supply

Figure 15. Leakage Curr ent vs. Temperature, 1 2 V Single Supp ly

Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply

Figure 16. Leakage Current vs. Temperature, 36 V Single Supply

Rev. A | Page 11 of 20

ADG5236 Data Sheet

10k 100k 1M 10M 100M 1G

FREQUENCY ( Hz )

0

–120

–100

–80

–60

–40

–20

I

L

(dB)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

09769-117

10k 100k 1M 10M 100M 1G

FREQUENCY ( Hz )

0

–140

–120

–100

–80

–60

–40

–20

CROSSTAL K ( dB)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

BETWEEN S A AND S B

BETWEEN S 1 AND S 2

09769-118

–20 –10

0 10 20 30 40

V

S

(V)

1.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

CHARGE INJECT ION (pC)

T

A

= 25°C

V

DD

= +20V

V

SS

= –20V

V

DD

= +15V

V

SS

= –15V

V

DD

= +36V

V

SS

= 0V

V

DD

= +12V

V

SS

= 0V

09769-119

1k 10k 100k 1M 10M

FREQUENCY ( Hz )

0

–120

–100

–80

–60

–40

–20

ACPSRR (dB)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

NO DECOUPL ING CAPACITORS

DECOUPLI NG CAPACITORS

09769-120

100k 1M 10M 100M 1G

FREQUENCY ( Hz )

0

–20

–18

–16

–14

–12

–10

–8

–6

–4

–2

ATTENUATION (dB)

TA = 25°C
V

DD

= +15V

V

SS

= –15V

09769-122

350

300

250

200

150

100

50

0

–40 –20 0 20 40 60 80 100 120

TIME (ns)

TEMPERATURE (°C)

VDD = +12V
V

SS

= 0V

V

DD

= +36V

V

SS

= 0V

V

DD

= +15V

V

SS

= –15V

V

DD

= +20V

V

SS

= –20V

09769-123

Figure 17. Off Isolation vs. Frequency

Figure 18. Crosstalk vs. Frequency

Figure 20. ACPSRR vs. Frequency

Figure 21. Bandwidth

Figure 19. Charge Injection vs. Source Voltage

Figure 22. t

Time vs. Temperature

TRANSITION

Rev. A | Page 12 of 20

Data Sheet ADG5236

–15 –10 –5 0 5 10 15

V

S

(V)

0

5

10

15

20

CAPACITANCE (pF)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

SOURCE/DRAI N ON

DRAIN OFF

SOURCE OF F

09769-124

Figure 23. Capacitance vs. Source Voltage, Dual Supply

Rev. A | Page 13 of 20

ADG5236 Data Sheet

V

V

V

V

V

V

V

V

TEST CIRCUITS

NC

SxA/SxB Dx

ID (ON)

A

IS(OFF) ID (OFF)

SxA/SxB Dx

A A

NETWO RK

ANALYZER

V

OUT

S

R

L

50Ω

V

S

NC = NO CONNECT

Figure 24. On Leakage

V

SxA/SxB Dx

Figure 25. On Resistance

0.1µF

SxA

SxB

INx

V

D

09769-025

S

V

D

09769-024

Figure 27. Off Leakage

DD

SS

0.1µF

V

DD

INx

V

IN

I

DS

09769-023

SxA

GND

0.1µF

V

SS

D

x

OFF ISOLATION = 20 log

SxB

NC

50Ω

NETWORK

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

09769-030

Figure 28. Off Isolation

DD

SS

0.1µF

0.1µF

V

V

DD

SS

Dx

GND

R
50Ω

L

INx

IN

V

DD

V

SS

0.1µF

NETWORK

V

DD

SxA

GND

SS

D

x

SxB

NC

50Ω

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

S

CHANNEL-TO -CHANNEL CROS STALK = 20 log

Figure 26. Channel-to-Channel Crosstalk

V

OUT

V

S

09769-032

INSERTION LOSS = 20 log

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

OUT

09769-031

Figure 29. Bandwidth

Rev. A | Page 14 of 20

Data Sheet ADG5236

V

V

VDDV

VDDV

V

V

DD

SS

0.1µF0.1µF

V

V

DD

SxB

V

S

SxA

INx

V

IN

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

V

IN

V

IN

V

OUT

50%

50%

t

ON

TRANSITION

90%

50%

50%

t

OFF

TRANSITION

90%

09769-026

Figure 30. Switching Times

SS

0.1µF0.1µF

V

V

V

DD

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

V

V

IN

SxB

S

SxA

INx

Figure 31. Break-Before-Make Time Delay t

IN

80%

V

OUT

t

D

D

t

D

09769-027

SS

3V

ENABLE
DRIVE (V

0V

OUTPUT

)

IN

t

(EN)

ON

50% 50%

0.9V

OUT

t

(EN)

OFF

0.1V

OUT

Figure 32. Enable Delay, t

V

IN

(EN), t

ON

50

OFF

(EN)

V

INx

EN

DDVSS

GND

SxA

SxB

Dx

OUTPUT

300

V

S

35pF

09769-028

DD

SS

0.1µF0.1µF

VIN(NORMALLY

NC

V

OUT

CLOSED SWI TCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

V

OUT

Q

INJ

ON

= CL × V

OUT

OFF

09769-029

V

V

DD

SS

GND

SxB

SxA

C
1nF

L

Dx

V

S

INx

V

IN

Figure 33. Charge Injection

Rev. A | Page 15 of 20

ADG5236 Data Sheet

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

V

, VS

D

V

and VS represent the analog voltage on Terminal D and

D

Terminal S, respectively.

R

ON

R

represents the ohmic resistance between Terminal D and

ON

Terminal S.

∆R

ON

∆R

represents the difference between the RON of any two

ON

channels.

R

FL AT (ON)

Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by R

(Off)

I

S

I

(Off) is the source leakage current with the switch off.

S

I

(Off)

D

I

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

I

D

I

(On) and IS (On) represent the channel leakage currents with

D

FLAT (ON)

.

the switch on.

V

INL

V

is the maximum input voltage for Logic 0.

INL

V

INH

V

is the minimum input voltage for Logic 1.

INH

I

, I

INL

INH

I

INL

and I

represent the low and high input currents of the

INH

digital inputs.

C

(Off)

D

C

(Off) represents the off switch drain capacitance, which is

D

measured with reference to ground.

C

(Off)

S

C

(Off) represents the off switch source capacitance, which is

S

measured with reference to ground.

C

(On), CS (On)

D

C

(On) and CS (On) represent on switch capacitances, which

D

are measured with reference to ground.

C

IN

C

is the digital input capacitance.

IN

t

ON

t

represents the delay between applying the digital control

ON

input and the output switching on.

t

OFF

t

represents the delay between applying the digital control

OFF

input and the output switching off.

t

D

t

represents the off time measured between the 80% point

D

of both switches when switching from one address state to
an other.

Off Isolation

Off isolation is a measure of unwanted signal coupling through
an off switch.

Charge Injection

Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated
by 3 dB.

On Response

On response is the frequency response of the on switch.

Insertion Loss

Insertion loss is the loss due to the on resistance of the switch.

AC Power Supply Rejection Ratio (ACPSRR)

ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the device to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.

Rev. A | Page 16 of 20

Data Sheet ADG5236

NMOS PMOS

P WELL N WEL L

BURIED OXI DE LAYER

HANDLE WAFE R

TRENCH

09769-045

TRENCH ISOLATION

In the ADG5236, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.

Figure 34. Trench Isolation

Rev. A | Page 17 of 20

ADG5236 Data Sheet

APPLICATIONS INFORMATION

The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5236 high voltage switches allow single­supply operation from 9 V to 40 V and dual supply operation
from ±9 V to ±22 V.

Rev. A | Page 18 of 20

Data Sheet ADG5236

S

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

PIN 1

INDICATOR

0.80

0.75

0.70

EATING

PLANE

4.10

4.00 SQ

3.90

0.65

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

0.35

0.30

0.25

13

12

9

8

BOTTOMVIEWTOP VIEW

COPLANARITY

0.08

N

1

I

P

C

I

A

N

I

16

EXPOSED

PAD

5

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

D

1

4

2.70

2.60 SQ

2.50

0.20 MIN

R

O

T

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

08-16-2010-C

Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG5236BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5236BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5236BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17

1

Z = RoHS Compliant Part.

Rev. A | Page 19 of 20

ADG5236 Data Sheet

NOTES

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09769-0-4/12(A)

Rev. A | Page 20 of 20