Datasheet ADG5233 Datasheet (ANALOG DEVICES)

High Voltage Latch-Up Proof,

S1A

S2A

FEATURES

Latch-up proof

4.5 pF off source capacitance
10 pF off drain capacitance

−0.6 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V

to VSS analog signal range

DD

Human body model (HBM) ESD rating

4 kV I/O port to supplies
1 kV I/O port to I/O port
4 kV all other pins

APPLICATIONS

Automatic test equipment
Data acquisition
Instrumentation
Avio nics
Audio and video switching
Communication systems

Triple/Quad SPDT Switches

ADG5233/ADG5234

FUNCTIONAL BLOCK DIAGRAMS

ADG5233

S1A

D1

S1B

S2B

D2

S2A

LOGIC

IN1 IN2 IN3 EN

SWITCHES SHOWN FOR
A 1 INPUT LO GIC.

Figure 1. ADG5233 TSSOP and LFCSP_VQ

ADG5234

D1

S1B

IN1

IN2

S2B

D2

SWITCHES S HOWN FOR
A 1 INPUT LOG IC.

Figure 2. ADG5234 TSSOP

S3B

D3

S3A

S4A

D4

S4B

IN4

IN3

S3B

D3

S3A

09919-001

09919-002

GENERAL DESCRIPTION

The ADG5233 and ADG5234 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double throw (SPDT) switches and four indepen­dently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An
input on the (LFCSP and TSSOP packages) is used to

ADG5233

enable or disable the device. When disabled, all channels are
switched off.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

EN

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.

2. Ultralow Capacitance and −0.6 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5233/ADG5234 can be operated from dual supplies

up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5233/ADG5234 can be operated from a single-rail

power supply up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

V

= 2.0 V, V

INH

6. No V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

Logic Power Supply Required.

L

= 0.8 V.

INL

ADG5233/ADG5234

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 4

12 V Single Supply........................................................................ 5

36 V Single Supply........................................................................ 6

REVISION HISTORY

7/11—Revision 0: Initial Version

Continuous Current per Channel, Sx or Dx..............................8

Absolute Maximum Ratings ............................................................9

ESD Caution...................................................................................9

Pin Configurations and Function Descriptions......................... 10

Typical Performance Characteristics........................................... 12

Test Circuits..................................................................................... 16

Terminology .................................................................................... 18

Trench Isolation.............................................................................. 19

Applications Information.............................................................. 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

ADG5233/ADG5234

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA; see Figure 26
200 250 280 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between

Channels, ∆R

ON

3.5 Ω typ V

8 9 10 Ω max
On-Resistance Flatness, R

38 Ω typ VS = ±10 V, IS = −1 mA

FLAT (ON)

50 65 70 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = ±10 V; see Figure 25

±0.2 ±0.3 ±0.9 nA max

DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V
Input Current, I

INL

2.0

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

V min

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

170 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

210 250 280 ns max VS = 10 V; see Figure 31

tON (EN)

175 ns typ R
215 255 290 ns max VS = 10 V; see Figure 33
t

(EN)

OFF

80 ns typ R
100 115 125 ns max VS = 10 V; see Figure 33

Break-Before-Make Time Delay, tD 60 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V; see Figure 32

Charge Injection, Q

−0.6 pC typ

INJ

Off Isolation −75 dB typ

Channel-to-Channel Crosstalk −80 dB typ

−3 dB Bandwidth 205 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30
Insertion Loss −6.3 dB typ

CS (Off) 4.5 pF typ VS = 0 V, f = 1 MHz
CD (Off) 10 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz

= ±10 V, IS = −1 mA

S

V

= ±10 V, VD = m10 V; see Figure 28

S

V

= ±10 V, VD = m10 V; see Figure 28

S

or VDD

GND

= 300 Ω, CL = 35 pF

L

= 300 Ω, CL = 35 pF

L

= 0 V, RS = 0 Ω, CL = 1 nF; see

V

S

Figure 34

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

Figure 27

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 30

Rev. 0 | Page 3 of 24

ADG5233/ADG5234

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance, RON 140 Ω typ VS = ±15 V, IS = −1 mA; see Figure 26
160 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between

Channels, ∆R

ON

3.5 Ω typ V

8 9 10 Ω max
On-Resistance Flatness, R

33 Ω typ VS = ±15 V, IS = −1 mA

FLAT (ON)

45 55 60 Ω max

LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = ±15 V; see Figure 25
±0.2 ±0.3 ±0.9 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

170 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

200 235 260 ns max VS = 10 V; see Figure 31
tON (EN)

165 ns typ R
200 240 265 ns max VS = 10 V; see Figure 33
t

OFF

(EN)

80 ns typ R
95 105 115 ns max VS = 10 V; see Figure 33

Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V; see Figure 32

Charge Injection, Q

0 pC typ

INJ

Off Isolation −75 dB typ

Channel-to-Channel Crosstalk −80 dB typ

−3 dB Bandwidth 210 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30
Insertion Loss −5.5 dB typ

= ±15 V, IS = −1 mA

S

V

= ±15 V, VD = m15 V; see Figure 28

S

V

= ±15 V, VD = m15 V; see Figure 28

S

or VDD

GND

= 300 Ω, CL = 35 pF

L

= 300 Ω, CL = 35 pF

L

= 0 V, RS = 0 Ω, CL = 1 nF; see

V

S

Figure 34

= 50 Ω, CL = 5 pF, f = 1MHz; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 27

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 30

Rev. 0 | Page 4 of 24

ADG5233/ADG5234

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

CS (Off) 4.5 pF typ VS = 0 V, f = 1 MHz
CD (Off) 10 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 μA typ Digital inputs = 0 V or VDD

70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance, RON 360 Ω typ

500 610 700 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between

Channels, ∆R

ON

5.5 Ω typ V

20 21 22 Ω max
On-Resistance Flatness, R

170 Ω typ VS = 0 V to 10 V, IS = −1 mA

FLAT (ON)

280 335 370 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ

±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = 1 V/10 V; see Figure 25

±0.2 ±0.3 ±0.9 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

235 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

295 365 410 ns max VS = 8 V; see Figure 31
tON (EN)

240 ns typ R
305 380 430 ns max VS = 8 V; see Figure 33
t

(EN)

OFF

70 ns typ R
90 105 115 ns max VS = 8 V; see Figure 33

Break-Before-Make Time Delay, tD 125 ns typ RL = 300 Ω, CL = 35 pF

65 ns min VS1 = VS2 = 8 V; see Figure 32

Charge Injection, Q

0 pC typ

INJ

= 0 V to 10 V, IS = −1 mA; see

V

S

Figure 26

= 0 V to 10 V, IS = −1 mA

S

= 1 V/10 V, VD = 10 V/1 V; see

V

S

Figure 28

= 1 V/10 V, VD = 10 V/1 V; see

V

S

Figure 28

or VDD

GND

= 300 Ω, CL = 35 pF

L

= 300 Ω, CL = 35 pF

L

= 6 V, RS = 0 Ω, CL = 1 nF; see

V

S

Figure 34

Rev. 0 | Page 5 of 24

ADG5233/ADG5234

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Off Isolation −75 dB typ

Channel-to-Channel Crosstalk −80 dB typ

−3 dB Bandwidth 172 MHz typ

Insertion Loss −8.7 dB typ

CS (Off) 5 pF typ VS = 6 V, f = 1 MHz
CD (Off) 11 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 16 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 μA typ Digital inputs = 0 V or VDD

50 65 μA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V
On Resistance, RON 140 Ω typ

170 215 245 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between

Channels, ∆R

ON

8 9 10 Ω max
On-Resistance Flatness, R

35 Ω typ VS = 0 V to 30 V, IS = −1 mA

FLAT (ON)

50 60 65 Ω max

LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ

±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = 1 V/30 V; see Figure 25
±0.2 ±0.3 ±0.9 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

205 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

255 275 290 ns max VS = 18 V; see Figure 31
tON (EN)
240 265 290 ns max VS = 18 V; see Figure 33
t

(EN)

OFF

115 115 115 ns max VS = 18 V; see Figure 33

3.5 Ω typ VS = 0 V to 30 V, IS = −1 mA

200 ns typ R

85 ns typ R

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 27

= 50 Ω, CL = 5 pF; see

R

L

Figure 30

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 30

= 0 V to 30 V, IS = −1 mA; see

V

S

Figure 26

= 1 V/30 V, VD = 30 V/1 V; see

V

S

Figure 28

= 1 V/30 V, VD = 30 V/1 V; see

V

S

Figure 28

or VDD

GND

= 300 Ω, CL = 35 pF

L

= 300 Ω, CL = 35 pF

L

Rev. 0 | Page 6 of 24

ADG5233/ADG5234

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Break-Before-Make Time Delay, tD 65 ns typ RL = 300 Ω, CL = 35 pF

35 ns min VS1 = VS2 = 18 V; see Figure 32

Charge Injection, Q

Off Isolation −75 dB typ

Channel-to-Channel Crosstalk −80 dB typ

−3 dB Bandwidth 190 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30
Insertion Loss −5.9 dB typ

CS (Off) 4.5 pF typ VS = 18 V, f = 1 MHz
CD (Off) 10 pF typ VS = 18 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

IDD 80 μA typ Digital inputs = 0 V or VDD

100 130 μA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

−0.6 pC typ

INJ

= 18 V, RS = 0 Ω, CL = 1 nF;

V

S

see Figure 34

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 27

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 30

Rev. 0 | Page 7 of 24

ADG5233/ADG5234

CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx

Table 5. ADG5233

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR Dx

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 24 16 11 mA maximum
LFCSP (θJA = 30.4°C/W) 42 26.5 15 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 26 17 11 mA maximum
LFCSP (θJA = 30.4°C/W) 46 28 15 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 17 12 7.7 mA maximum
LFCSP (θJA = 30.4°C/W) 24 17 11 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 25 17 11 mA maximum
LFCSP (θJA = 30.4°C/W) 45 28 15 mA maximum

Table 6. ADG5234

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR Dx

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 21 15 10 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 22 15 10 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 15 11 7 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 22 15 10 mA maximum

Rev. 0 | Page 8 of 24

ADG5233/ADG5234

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1

Digital Inputs1

Peak Current, Sx or Dx Pins

ADG5233

ADG5234

Continuous Current, Sx or Dx2 Data + 15%
Temperature Range

Operating −40°C to +125°C
Storage −65°C to +150°C

Junction Temperature 150°C
Thermal Impedance, θJA

16-Lead TSSOP (4-Layer Board) 112.6°C/W
20-Lead TSSOP (4-Layer Board) 143°C/W
16-Lead LFCSP (4-Layer Board) 30.4°C/W

Reflow Soldering Peak

Temperature, Pb Free

Human Body Model (HBM) ESD

I/O Port to Supplies

I/O Port to I/O Port

All Other Pins

1

Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.

Limit current to the maximum ratings given.

2

See Table 5 and Table 6.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs
first

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs
first

76 mA (pulsed at 1 ms, 10%
duty cycle maximum)

67 mA (pulsed at 1 ms, 10%
duty cycle maximum)

260(+0/−5)°C

4 kV

1 kV

4 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any
one time.

ESD CAUTION

Rev. 0 | Page 9 of 24

ADG5233/ADG5234

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD

S1A

2

D1

3

ADG5233

4

S1B
S2B

S2A

D2

IN2

TOP VIEW

(Not to Scale)

5
6
7
8

Figure 3. ADG5233 TSSOP Pin Configuration

16

GND
IN1

15

EN

14
13

V

SS

S3B

12

D3

11
10

S3A
IN3

9

09919-003

S1B

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

Figure 4. ADG5233 LFCSP_VQ Pin Configuration

Table 8. ADG5233 Pin Function Descriptions

Pin No.

TSSOP LFCSP_VQ

Mnemonic Description

1 15 VDD Most Positive Power Supply Potential.
2 16 S1A Source Terminal 1A. This pin can be an input or an output.
3 1 D1 Drain Terminal 1. This pin can be an input or an output.
4 2 S1B Source Terminal 1B. This pin can be an input or an output.
5 3 S2B Source Terminal 2B. This pin can be an input or an output.
6 4 D2 Drain Terminal 2. This pin can be an input or an output.
7 5 S2A Source Terminal 2A. This pin can be an input or an output.
8 6 IN2 Logic Control Input 2.
9 7 IN3 Logic Control Input 3.
10 8 S3A Source Terminal 3A. This pin can be an input or an output.
11 9 D3 Drain Terminal 3. This pin can be an input or an output.
12 10 S3B Source Terminal 3B. This pin can be an input or an output.
13 11 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to
ground.

14 12

Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx

EN

logic inputs determine the on switches.
15 13 IN1 Logic Control Input 1.
16 14 GND Ground (0 V) Reference.
EP

Exposed
Pad

The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, V

1D1
2
3S2B
4D2

DD

S1A

V

GND
14

16

15

ADG5233

TOP VIEW

(Not to Scale)

7

5

6

3

IN2

IN

S2A

IN1
13

8

S3A

12 EN

V

11

SS

10 S3B
9D3

.

SS

09919-004

.

SS

Table 9. ADG5233 Truth Table

EN

INx SxA SxB

1 X1 Off Off
0 0 Off On
0 1 On Off

1

X is don’t care.

Rev. 0 | Page 10 of 24

ADG5233/ADG5234

IN1

1

2

S1A

D1

3

S1B

4

ADG5234

5

V

SS

TOP VIEW

(Not to Scale)

GND

6

7

S2B

D2

8

9

S2A

IN2

10

NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.

Figure 5. ADG5234 TSSOP Pin Configuration

Table 10. ADG5234 Pin Function Descriptions

Pin No. Mnemonic Description

1 IN1 Logic Control Input 1.
2 S1A Source Terminal 1A. This pin can be an input or an output.
3 D1
4 S1B
5 V

SS

Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to

ground.
6 GND
7 S2B
8 D2
9 S2A
10 IN2
11 IN3
12 S3A
13 D3
14 S3B
15 NC
16 V

DD

17 S4B
18 D4
19 S4A

Most Positive Power Supply Potential.

Ground (0 V) Reference.

Source Terminal 2B. This pin can be an input or an output.

Drain Terminal 2. This pin can be an input or an output.

Source Terminal 2A. This pin can be an input or an output.

Logic Control Input 2.

Logic Control Input 3.

Source Terminal 3A. This pin can be an input or an output.

Drain Terminal 3. This pin can be an input or an output.

Source Terminal 3B. This pin can be an input or an output.

No Connect. This pin is open.

Source Terminal 4B. This pin can be an input or an output.

Drain Terminal 4. This pin can be an input or an output.

Source Terminal 4A. This pin can be an input or an output.
20 IN4 Logic Control Input 4.

IN4

20

19

S4A

D4

18

S4B

17

16

V

DD

NC

15

14

S3B

D3

13

12

S3A

IN3

11

09919-005

Table 11. ADG5234 Truth Table

INx SxA SxB

0 Off On
1 On Off

Rev. 0 | Page 11 of 24

ADG5233/ADG5234

TYPICAL PERFORMANCE CHARACTERISTICS

160

TA = 25°C

140

120

VDD = +18V
V

= –18V

SS

160

140

120

TA = 25°C

VDD = 32.4V

= 0V

V

SS

100

V

80

60

ON RESISTANCE ()

40

20

0

–25 –20 –15 –10 –5 0 5 10 15 20 25

Figure 6. On Resistance as a Function of V

V

DD

= –20V

SS

= +20V

VS, VD (V)

= +22V

V

DD

V

= –22V

SS

, VD (±20 V Dual Supply)

S

250

TA = 25°C

200

150

100

ON RESISTANCE ()

VDD = +16.5V

= –16.5V

V

SS

50

0

–20 –15 –10 –5 0 5 10 15 20

VDD = +15V

= –15V

V

SS

VS, VD (V)

Figure 7. On Resistance as a Function of V

500

ON RESISTANCE ()

450

400

350

300

250

200

150

100

50

0

TA = 25°C

01412108642

VDD = 9V
V

SS

VS, VD (V)

Figure 8. On Resistance as a Function of V

VDD = +9V

= –9V

V

SS

VDD = +13.2V

= –13.2V

V

SS

, VD (±15 V Dual Supply)

S

= 0V

VDD = 10.8V

= 0V

V

SS

VDD = 12V

= 0V

V

SS

VDD = 13.2V
V

, VD (12 V Single Supply)

S

= 0V

SS

100

80

60

ON RESISTANCE ( )

40

20

0

043530252015105

09919-006

VDD = 36V

= 0V

V

SS

VS, VD (V)

Figure 9. On Resistance as a Function of V

VDD = 39.6V

= 0V

V

SS

, VD (36 V Single Supply)

S

0

09919-009

250

VDD = +15V
V

= –15V

SS

200

150

100

ON RESISTANCE ()

50

0

–15 –10 –5 0 5 10 15

09919-007

Figure 10. On Resistance as a Function of V

TA = +125°C

T

= +85°C

A

= +25°C

T

A

T

= –40°C

A

VS,VD (V)

(VD) for Different Temperatures,

S

09919-010

±15 V Dual Supply

200

180

160

140

120

100

80

ON RESISTANCE ( )

60

40

20

VDD = +20V
V

= –20V

SS

0

–20 –15 –10 –5 0 5 10 2015

09919-008

Figure 11. On Resistance as a Function of V

T

= +125°C

A

T

= +85°C

A

= +25°C

T

A

= –40°C

T

A

VS,VD (V)

(VD) for Different Temperatures,

S

09919-011

±20 V Dual Supply

Rev. 0 | Page 12 of 24

ADG5233/ADG5234

500

450

= +125°C

400

340

300

250

200

ON RESISTANCE ( )

150

100

50

VDD = 12V
V

= 0V

SS

0

024681012

T

A

T

A

T

A

T

A

= +85°C

= +25°C

= –40°C

VS,VD (V)

Figure 12. On Resistance as a Function of V

12 V Single Supply

250

VDD = 36V
V

= 0V

SS

200

T

= +125°C

150

100

ON RESISTANCE ()

50

0

03530252015105

A

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

VS,VD (V)

Figure 13. On Resistance as a Function of V

36 V Single Supply

50

0

–50

–100

(VD) for Different Temperatures,

S

(VD) for Different Temperatures,

S

(OFF) + –

I

S

I

(OFF) – +

S

ID, IS (ON) + +

(OFF) + –

I

D

(OFF) – +

I

D

09919-012

09919-013

100

50

0

–50

–100

LEAKAGE CURRENT ( pA)

–150

VDD = +20V
V

= –20V

SS

V

= +15V/–15V

BIAS

–200

0 25 50 75 100 125

I

(OFF) – +

D

I

D

TEMPERATURE (°C)

, IS (ON) – –

(OFF) + –

I

S

I

, IS (ON) + +

D

I

(OFF) + –

D

I

Figure 15. Leakage Currents as a Function of Temperature,

±20 V Dual Supply

100

0

–100

–200

–300

–400

LEAKAGE CURRENT ( pA)

–500

VDD = 12V

–600

V

= 0V

SS

V

= 1V/10V

BIAS

–700

0 25 50 75 100 125

TEMPERATURE (°C)

(OFF) + –

I

S

ID, IS (ON) + +

(OFF) – +

I

D

ID, IS (ON) – –

I

D

(OFF) + –

Figure 16. Leakage Currents as a Function of Temperature,

12 V Single Supply

200

–200

–400

I

(OFF) – +

D

0

(OFF) + –

I

D

ID, IS (ON) + +

(OFF) – +

I

S

(OFF) – +

S

(OFF) – +

I

S

I

(OFF) + –

S

09919-015

09919-016

–150

LEAKAGE CURRENT (p A)

–200

VDD = +15V
V

= –15V

SS

V

= +10V/–10V

BIAS

–250

0 25 50 75 100 125

TEMPERATURE (°C)

ID, IS (ON) – –

09919-014

Figure 14. Leakage Currents as a Function of Temperature, ±15 V Dual Supply

Rev. 0 | Page 13 of 24

–600

LEAKAGE CURRENT (p A)

–800

VDD = 36V
V

= 0V

SS

V

= 1V/30V

BIAS

–1000

0 25 50 75 100 125

TEMPERATURE (°C)

ID, IS (ON) – –

Figure 17. Leakage Currents as a Function of Temperature,

36 V Single Supply

09919-017

ADG5233/ADG5234

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

–40

–60

–80

OFF ISOLATION (dB)

–100

–120

10k 100k 1G100M10M1M

Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply

0

TA = 25°C
V

= +15V

DD

V

= –15V

–20

SS

–40

–60

–80

CROSSTALK (dB)

–100

–120

–140

10k 100k 1G100M10M1M

Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply

FREQUENCY (Hz)

BETWEEN SxA AND SxB

FREQUENCY (Hz)

BETWEEN S1x AND S2x

14

TA = 25°C
SOURCE TO DRAIN

12

10

V

= +15V

8

6

4

2

CHARGE INJECTI ON (pC)

0

–2

–4

–20 –10 0 10 20 30 40

09919-018

V

DD

= –15V

SS

VS (V)

V
V

DD
SS

= 0V

VDD = +20V
V

= +12V

= –20V

SS

V
V

= +36V

DD

= 0V

SS

09919-020

Figure 20. Charge Injection vs. Source Voltage, Source to Drain

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

–40

–60

ACPSSR (dB)

–80

–100

–120

1k 10k 100k 10M1M

09919-019

NO DECOUPLI NG

CAPACITORS

DECOUPL ING
CAPACITORS

FREQUENCY (Hz)

09919-021

Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply

Rev. 0 | Page 14 of 24

ADG5233/ADG5234

0

–2

–4

–6

TA = 25°C
V

= +15V

DD

V

= –15V

SS

20

15

10

TA = 25°C
V

= +15V

DD

V

= –15V

SS

SOURCE/DRAIN ON

DRAIN OFF

–8

ATTENUATION (dB)

–10

–12

100k 1G100M10M1M

FREQUENCY (Hz)

Figure 22. Bandwidth

09919-023

CAPACITANCE (pF )

5

0

–15 –10 –5 0 5 10 15

SOURCE OFF

V

(V)

S

Figure 24. Capacitance vs. Source Voltage, ±15 V Dual Supply

09919-025

300

250

200

150

TIME (ns)

100

50

0

–40 –20 120100806040200

VDD = +12V, VSS = 0V

V

= +15V, VSS = –15V

DD

Figure 23. t

V

= +36V, VSS = 0V

DD

V

TEMPERATURE ( °C)

Times vs. Temperature

TRANSITION

= +20V, VSS = –20V

DD

09919-024

Rev. 0 | Page 15 of 24

ADG5233/ADG5234

V

V

V

V

V

V

TEST CIRCUITS

NC

Sx Dx

NC = NO CONNECT

Figure 25. On Leakage

IS(OFF) ID (OFF)

ID (ON)

Sx Dx

A A

A

V

D

09919-027

S

V

D

09919-031

Figure 28. Off Leakage

V

DD

SS

0.1µF

0.1µF

V

Sx Dx

S

Figure 26. On Resistance

DD

0.1µF

NETWORK

ANALYZER

V

OUT

R

L

50

V

S

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

INx

V

SxA

SxB

Figure 27. Channel-to-Channel Crosstalk

V

OUT

V

S

NETWORK

ANALYZER

50

V

OUT

R

L

50

V

S

09919-030

V

IN

V

IN

I

DS

09919-028

V

DD

SS

SxA

SxB

Dx

GND

OFF ISOLATION = 20 log

NC

50

Figure 29. Off Isolation

SS

0.1µF

V

DD

SS

Dx

R
50

GND

V

OUT

V

S

09919-029

0.1µF

INx

V

IN

V

DD

SS

V

V

DD

SS

SxA

SxB

GND

INSERTION LOSS = 20 log

0.1µF

Dx

NC

50

NETWORK

ANALYZER

50

R

L

50

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

V

S

V

OUT

09919-033

Figure 30. Bandwidth

Rev. 0 | Page 16 of 24

ADG5233/ADG5234

V

V

V

V

VDDV

V

V

DD

SS

0.1µF0.1µ F

V

V

DD

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

SxB

V

S

SxA

INx

V

IN

V

IN

V

IN

V

OUT

50%

50%

t

ON

TRANSITION

90%

50%

50%

t

OFF

TRANSITION

90%

09919-100

Figure 31. Switching Timing

DD

0.1µF

V

SxB

V

S

SxA

INx

V

IN

SS

0.1µF

V

DD

GND

SS

Dx

R

L

300

C

L

35pF

V

OUT

Figure 32. Break-Before-Make Delay, t

V

IN

80%

V

OUT

t

D

D

t

D

09919-035

SS

3V

ENABLE
DRIVE (V

0V

OUTPUT

)

IN

50% 50%

0.9V

OUT

t

(EN)tON (EN)

OFF

0.1V

OUT

Figure 33. Enable Delay, t

V

IN

(EN), t

ON

50

OFF

(EN)

V

INx

EN

DDVSS

GND

SxA

SxB

Dx

OUTPUT

300

V

S

35pF

09919-101

DD

SS

V

SS

SxB

SxA

0.1µF

C
1nF

VIN (NORMALLY
CLOSED SWITCH)

NC

V

(NORMALLY

IN

OPEN SWITCH)

V

OUT

L

V

OUT

V

OUT

ON OFF

Q

= CL × V

INJ

OUT

09919-037

0.1µF

V

DD

Dx

V

S

INx

V

IN

GND

Figure 34. Charge Injection

Rev. 0 | Page 17 of 24

ADG5233/ADG5234

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

, VS

V

D

V

and VS represent the analog voltage on Terminal Dx and

D

Terminal Sx, respectively.

R

ON

R

is the ohmic resistance between Terminal Dx and

ON

Ter m in a l S x .

ΔR

ON

ΔR

represents the difference between the RON of any two

ON

channels.

R

The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by R

I

I

I

I

I

I
the switch on.

V

V

V

V

I

I
digital inputs.

C

C
measured with reference to ground.

C

C
measured with reference to ground.

C

C
are measured with reference to ground.

FLAT (ON)

.

FLAT (ON)

(Off)

S

(Off) is the source leakage current with the switch off.

S

(Off)

D

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

D

(On) and IS (On) represent the channel leakage currents with

D

INL

is the maximum input voltage for Logic 0.

INL

INH

is the minimum input voltage for Logic 1.

INH

, I

INL

INH

and I

INL

(Off)

D

(Off) represents the off switch drain capacitance, which is

D

(Off)

S

(Off) represents the off switch source capacitance, which is

S

(On), CS (On)

D

(On) and CS (On) represent on switch capacitances, which

D

represent the low and high input currents of the

INH

C

IN

C

represents digital input capacitance.

IN

(EN)

t

ON

t

(EN) represents the delay time between the 50% and 90%

ON

points of the digital input and switch on condition.

(EN)

t

OFF

t

(EN) represents the delay time between the 50% and 90%

OFF

points of the digital input and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

t

D

represents the off time measured between the 80% point of

t

D

both switches when switching from one address state to another.

Off Isolation

Off isolation is a measure of unwanted signal coupling through
an off channel.

Charge Injection

Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated
by 3 dB.

On Response

On response is the frequency response of the on switch.

AC Power Supply Rejection Ratio (ACPSRR)

ACPSRR is a measure of the ability of a part to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR.

Rev. 0 | Page 18 of 24

ADG5233/ADG5234

TRENCH ISOLATION

In the ADG5233/ADG5234, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.

NMOS PMOS

PWELL NWELL

TRENCH

BURIED OXIDE L AYER

HANDLE WAFER

Figure 35. Trench Isolation

09919-038

Rev. 0 | Page 19 of 24

ADG5233/ADG5234

APPLICATIONS INFORMATION

The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive, aero­space, and other harsh environments that are prone to latch-up,
which is an undesirable high current state that can lead to device
failure and persists until the power supply is turned off.

The ADG5233/ADG5234 high voltage switches allow single­supply operation from 9 V to 40 V and dual supply operation
from ±9 V to ±22 V.

Rev. 0 | Page 20 of 24

ADG5233/ADG5234

Y

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

20

1

0.65

BSC

0.30

0.19

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 37. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

Temperature Range Description

ADG5233BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16
ADG5233BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16
ADG5234BRUZ −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20
ADG5234BRUZ-RL7 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20

1

Z = RoHS Compliant Part.

Rev. 0 | Page 21 of 24

EN

Pin

Package Option

ADG5233/ADG5234

NOTES

Rev. 0 | Page 22 of 24

ADG5233/ADG5234

NOTES

Rev. 0 | Page 23 of 24

ADG5233/ADG5234

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09919-0-7/11(0)

Rev. 0 | Page 24 of 24