Datasheet ADG5208 Datasheet (ANALOG DEVICES)

4-/8-Channel Multiplexers

ADG5208/ADG5209

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trad emarks and registered trademarks are the property of their respective owners.

ADG5208

S1

S8

D

1-OF-8

DECODER

A0 A1 A2 EN

ADG5209

S1A

S4A

DA

S1B

S4B

DB

1-OF-4

DECODER

A0 A1

EN

09917-001

Data Sheet

FEATURES

Latch-up proof

5.5 pF off source capacitance 52 pF off drain capacitance

0.4 pC charge injection Low on resistance: 160 Ω typical ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V V

to VDD analog signal range

SS

Human body model (HBM) ESD rating

4 kV I/O port to supplies 1 kV I/O port to I/O port 4 kV all other pins

APPLICATIONS

Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems

High Voltage, Latch-Up Proof,

FUNCTIONAL BLOCK DIAGRAMS

Figure 1.

GENERAL DESCRIPTION

The ADG5208/ADG5209 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG5208 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG5209 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1.

An EN input on both devices enables or disables the device. When EN is disabled, all channels switch off. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make these devices suitable for video signal switching.

Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The ADG5208/ADG5209 do not have V

pins; instead, the logic

L

power supply is generated internally by an on-chip voltage generator.

PRODUCT HIGHLIGHTS

1. Tre nch Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors to prevent latch-up even under severe overvoltage conditions.

2. 0.4 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the

ADG5208/ADG5209 can be operated from dual supplies

of up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the

ADG5208/ADG5209 can be operated from a single rail

power supply of up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

V

= 2.0 V, V

INH

6. No V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

Logic Power Supply Required.

L

= 0.8 V.

INL

www.analog.com

ADG5208/ADG5209 Data Sheet

REVISION HISTORY

3/12—Rev. 0 to Rev. A

Added 16-Lead LFCSP ....................................................... Universal

Changes to Ordering Guide ........................................................... 22

7/11—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................9

ESD Caution...................................................................................9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 12

Test Circuits ..................................................................................... 16

Terminology .................................................................................... 19

Trench Isolation .............................................................................. 20

Applications Information .............................................................. 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

Rev. A | Page 2 of 24

Data Sheet ADG5208/ADG5209

200

250

280

Ω max

VDD = +13.5 V, VSS = −13.5 V

±0.1

±0.2

±0.4

nA max

±0.2

±0.5

±1.4

nA max

205

245

275

ns max

VS = 10 V; see Figure 33

tON (EN)

145

ns typ

RL = 300 Ω, CL = 35 pF

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA; see Figure 28

On-Resistance Match Between

Channels, ∆R

ON

3.5 Ω typ V

= ±10 V, IS = −1 mA

S

8 9 10 Ω max On-Resistance Flatness, R

40 Ω typ VS = ±10 V, IS = −1 mA

FL AT (O N)

50 65 70 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off ) ±0.005 nA typ VS = ±10 V, VD = 10 V; see Figure 30

Drain Off Leakage, ID (Off ) ±0.005 nA typ VS = ±10 V, VD = 10 V; see Figure 30 ±0.1 ±0.4 ±1.4 nA max Channel On Leakage, ID (On), IS (On) ±0.01 nA typ VS = VD = ±10 V; see Figure 27

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

GND

or VDD ±0.1 µA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

170 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

185 220 245 ns max VS = 10 V; see Figure 35 t

(EN) 120 ns typ RL = 300 Ω, CL = 35 pF

OFF

145 165 180 ns max VS = 10 V; see Figure 35

Break-Before-Make Time Delay, tD 65 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V; see Figure 34 Charge Injection, Q

0.4 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;

INJ

see Figure 36

Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 31

Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 29

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 32

ADG5208 54 MHz typ ADG5209 133 MHz typ

Insertion Loss −6.4 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 32 CS (Off ) 5.5 pF typ VS = 0 V, f = 1 MHz CD (Off )

ADG5208 52 pF typ VS = 0 V, f = 1 MHz ADG5209 26 pF typ VS = 0 V, f = 1 MHz

Rev. A | Page 3 of 24

ADG5208/ADG5209 Data Sheet

DIGITAL INPUTS

30

ns min

VS1 = VS2 = 10 V; see Figure 34

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

CD (On), CS (On)

ADG5208 58 pF typ VS = 0 V, f = 1 MHz ADG5209 31 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 µA typ Digital inputs = 0 V or VDD

55 70 µA max

ISS 0.001 µA typ Digital inputs = 0 V or VDD

1 µA max

VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance, RON 140 Ω typ VS = ±15 V, IS = −1 mA; see Figure 28 160 200 230 Ω max VDD = +18 V, VSS = −18 V On-Resistance Match Between

Channels, ∆R

ON

8 9 10 Ω max On-Resistance Flatness, R

FL AT (O N)

45 55 60 Ω max

LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off ) ±0.005 nA typ VS = ±15 V, VD = 15 V; see Figure 30 ±0.1 ±0.2 ±0.4 nA max Drain Off Leakage, ID (Off ) ±0.005 nA typ VS = ±15 V, VD = 15 V; see Figure 30 ±0.1 ±0.4 ±1.4 nA max Channel On Leakage, ID (On), IS (On) ±0.01 nA typ VS = VD = ±15 V; see Figure 27 ±0.2 ±0.5 ±1.4 nA max

3.5 Ω typ V

= ±15 V, IS = −1 mA

S

34 Ω typ VS = ±15 V, IS = −1 mA

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

±0.1 µA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t 195 225 255 ns max VS = 10 V; see Figure 33 tON (EN) 145 ns typ RL = 300 Ω, CL = 35 pF 170 200 225 ns max VS = 10 V; see Figure 35 t

(EN) 120 ns typ RL = 300 Ω, CL = 35 pF

OFF

140 155 170 ns max VS = 10 V; see Figure 35 Break-Before-Make Time Delay, tD 55 ns typ RL = 300 Ω, CL = 35 pF

Charge Injection, Q

Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

160 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

0.3 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see

INJ

GND

or VDD

Figure 36

Figure 31

see Figure 29

Rev. A | Page 4 of 24

Data Sheet ADG5208/ADG5209

ADG5208

57

pF typ

VS = 0 V, f = 1 MHz

Parameter

25°C

−40°C to +85°C

−40°C to +125°C

Unit

Test Conditions/Comments

LEAKAGE CURRENTS

VDD = 13.2 V, VSS = 0 V

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 32

ADG5208 60 MHz typ ADG5209 130 MHz typ

Insertion Loss −5.6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 32 CS (Off ) 5.5 pF typ VS = 0 V, f = 1 MHz CD (Off )

ADG5208 51 pF typ VS = 0 V, f = 1 MHz ADG5209 26 pF typ VS = 0 V, f = 1 MHz

CD (On), CS (On)

ADG5209 31 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 µA typ Digital inputs = 0 V or VDD 70 110 µA max ISS 0.001 µA typ Digital inputs = 0 V or VDD 1 µA max VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance, RON 350 Ω typ VS = 0 V to 10 V, IS = −1 mA; see

Figure 28 500 610 700 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between

Channels, ∆R

ON

20 22 24 Ω max On-Resistance Flatness, R

FL AT (O N)

280 335 370 Ω max

Source Off Leakage, IS (Off ) ±0.005 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see

±0.1 ±0.2 ±0.4 nA max Drain Off Leakage, ID (Off ) ±0.005 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see

±0.1 ±0.4 ±1.4 nA max

Channel On Leakage, ID (On), IS (On) ±0.01 nA typ VS = VD = 1 V/10 V; see Figure 27

±0.2 ±0.5 ±1.4 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 µA typ VIN = V

INH

±0.1 µA max Digital Input Capacitance, CIN 3 pF typ

5 Ω typ V

= 0 V to 10 V, IS = −1 mA

S

160 Ω typ VS = 0 V to 10 V, IS = −1 mA

Figure 30

or VDD

GND

Rev. A | Page 5 of 24

ADG5208/ADG5209 Data Sheet

275

345

400

ns max

VS = 8 V; see Figure 35

50 65

µA max

On-Resistance Match Between

3.5

Ω typ

VS = 0 V to 30 V, IS = −1 mA ±0.1

±0.2

±0.4

nA max

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

DYNAMIC CHARACTERISTICS1

Transition Time, t 270 330 380 ns max VS = 8 V; see Figure 33 tON (EN) 215 ns typ RL = 300 Ω, CL = 35 pF

t

(EN) 115 ns typ RL = 300 Ω, CL = 35 pF

OFF

140 160 175 ns max VS = 8 V; see Figure 35 Break-Before-Make Time Delay, tD 135 ns typ RL = 300 Ω, CL = 35 pF

70 ns min VS1 = VS2 = 8 V; see Figure 34

Charge Injection, Q

Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 32

ADG5208 60 MHz typ ADG5209 120 MHz typ

Insertion Loss −8.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

CS (Off ) 6 pF typ VS = 6 V, f = 1 MHz CD (Off )

ADG5208 56 pF typ VS = 6 V, f = 1 MHz ADG5209 28 pF typ VS = 6 V, f = 1 MHz

CD (On), CS (On)

ADG5208 63 pF typ VS = 6 V, f = 1 MHz ADG5209 35 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 µA typ Digital inputs = 0 V or VDD

210 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

0.3 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see

INJ

Figure 36

see Figure 31

see Figure 29

see Figure 32

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance, RON 150 Ω typ VS = 0 V to 30 V, IS = −1 mA; see

Figure 28

170 215 245 Ω max VDD = 32.4 V, VSS = 0 V

Channels, ∆RON 8 9 10 Ω max On-Resistance Flatness, R 55 65 70 Ω max

LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V

Source Off Leakage, IS (Off ) ±0.005 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see

35 Ω typ VS = 0 V to 30 V, IS = −1 mA

FL AT (O N)

Figure 30

Rev. A | Page 6 of 24

Data Sheet ADG5208/ADG5209

Input Low Voltage, V

0.8

V max

CD (Off )

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Drain Off Leakage, ID (Off ) ±0.005 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see

Figure 30

±0.1 ±0.4 ±1.4 nA max

Channel On Leakage, ID (On), IS (On) ±0.01 nA typ VS = VD = 1 V/30 V; see Figure 27

±0.2 ±0.5 ±1.4 nA max

DIGITAL INPUTS

Input High Voltage, V

Input Current, I

INL

±0.1 µA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t 230 245 259 ns max VS = 18 V; see Figure 33 tON (EN) 170 ns typ RL = 300 Ω, CL = 35 pF 210 230 255 ns max VS = 18 V; see Figure 35 t

(EN) 125 ns typ RL = 300 Ω, CL = 35 pF

OFF

180 180 180 ns max VS = 18 V; see Figure 35 Break-Before-Make Time Delay, tD 70 ns typ RL = 300 Ω, CL = 35 pF

35 ns min VS1 = VS2 = 18 V; see Figure 34

Charge Injection, Q

Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 32

ADG5208 65 MHz typ ADG5209 130 MHz typ

Insertion Loss −6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

CS (Off ) 5.5 pF typ VS = 18 V, f = 1 MHz

2.0 V min

INH

INL

or I

0.002 µA typ VIN = V

INH

185 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

0.4 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF;

INJ

GND

or VDD

see Figure 36

see Figure 31

see Figure 29

see Figure 32

ADG5208 51 pF typ VS = 18 V, f = 1 MHz ADG5209 25 pF typ VS = 18 V, f = 1 MHz

CD (On), CS (On)

ADG5208 57 pF typ VS = 18 V, f = 1 MHz ADG5209 32 pF typ VS = 18 V, f = 1 MH z

POWER REQUIREMENTS VDD = 39.6 V

IDD 80 µA typ Digital inputs = 0 V or VDD 100 130 µA max VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

Rev. A | Page 7 of 24

ADG5208/ADG5209 Data Sheet

VDD = +15 V, VSS = −15 V

CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx

Table 5. ADG5208

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR D

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 40 24 14.5 mA maximum LFCSP (θJA = 30.4°C/W) 69 37 18 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 42 26.5 14.5 mA maximum LFCSP (θJA = 30.4°C/W) 75 40 18 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 28 19 12 mA maximum LFCSP (θJA = 30.4°C/W) 40 25 14.5 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 40 26 14.5 mA maximum LFCSP (θJA = 30.4°C/W) 72 39 18 mA maximum

Table 6. ADG5209

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR Dx

TSSOP (θJA = 112.6°C/W) 29 19 12 mA maximum LFCSP (θJA = 30.4°C/W) 51 30 16 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 30 20 12.5 mA maximum LFCSP (θJA = 30.4°C/W) 55 32 17 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 20 14 10 mA maximum LFCSP (θJA = 30.4°C/W) 29 20 12.5 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 30 20 12.5 mA maximum LFCSP (θJA = 30.4°C/W) 54 31 17 mA maximum

Rev. A | Page 8 of 24

Data Sheet ADG5208/ADG5209

Junction Temperature

150°C

Reflow Soldering Peak

260(+0/−5)°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

VDD to VSS 48 V VDD to GND −0.3 V to +48 V VSS to GND +0.3 V to −48 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Peak Current, Sx, D, or Dx Pins

ADG5208 126 mA (pulsed at 1 ms, 10%

duty cycle maximum)

ADG5209 92 mA (pulsed at 1 ms, 10%

duty cycle maximum)

Continuous Current, Sx, D, or

Temperature Range

2

Dx Pins

Operating −40°C to +125°C Storage −65°C to +150°C

Data + 15%

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Thermal Impedance, θJA

16-Lead TSSOP (4-Layer

Board)

16-Lead LFCSP (4-Layer

Board)

Temperature, Pb Free

HBM ESD

I/O Port to Supplies 4 kV I/O Port to I/O Port 1 kV All Other Pins 4 kV

1

Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal

diodes. Limit current to the maximum ratings given.

2

See Table 5 and Table 6.

112.6°C/W

30.4°C/W

Rev. A | Page 9 of 24

ADG5208/ADG5209 Data Sheet

A0

1

EN

2

V

SS

3

S1

4

A1

16

A2

15

GND

14

V

DD

13

S2

5

S5

12

S3

6

S6

11

S4

7

S7

10

D

8

S8

9

ADG5208

TOP VIEW

(Not to Scale)

09917-002

12 11 10

1

3 4

GND V

DD

S5

9

S6

V

SS

S2

2

S1

S3

6 D

5S4

7S8

8 S7

16

EN

15

A0

14

A1

13

A2

TOP VIEW

(Not to S cale)

ADG5208

NOTES

1. THE EXPOSED PAD IS CONNECTE D INTERNALLY . FOR INCREASED REL IABILIT Y OF THE SO LDER JOINT S AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE P AD BE S OLDERED TO THE SUBSTRATE , V

SS

.

09917-003

2

16

EN

Active High Digital Input. When low, the device is disabled and all switches are off. When high, the 11 9 S6

Source Terminal 6. This pin can be an input or an output.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. ADG5208 Pin Configuration (TSSOP)

Figure 3. ADG5208 Pin Configuration (LFCSP)

Table 8. ADG5208 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input.

Ax logic inputs determine the on switches.

3 1 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected

to ground. 4 2 S1 Source Terminal 1. This pin can be an input or an output. 5 3 S2 Source Terminal 2. This pin can be an input or an output. 6 4 S3 Source Terminal 3. This pin can be an input or an output. 7 5 S4 Source Terminal 4. This pin can be an input or an output. 8 6 D Drain Terminal. This pin can be an input or an output. 9 7 S8 Source Terminal 8. This pin can be an input or an output. 10 8 S7 Source Terminal 7. This pin can be an input or an output.

12 10 S5 Source Terminal 5. This pin can be an input or an output. 13 11 VDD Most Positive Power Supply Potential. 14 12 GND Ground (0 V) Reference. 15 13 A2 Logic Control Input. 16 14 A1 Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and

maximum thermal capability, it is recommended that the pad be soldered to the substrate, V

SS

.

Table 9. ADG5208 Truth Table

A2 A1 A0 EN On Switch

X1 X1 X1 0 None 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8

1

X is don’t care.

Rev. A | Page 10 of 24

Data Sheet ADG5208/ADG5209

A0

1

EN

2

V

SS

3

S1A

4

A1

16

GND

15

V

DD

14

S1B

13

S2A

5

S2B

12

S3A

6

S3B

11

S4A

7

S4B

10

DA

8

DB

9

ADG5209

TOP VIEW

(Not to Scale)

09917-004

12 11 10

1

3 4

V

DD

S1B S2B

9

S3B

V

SS

S2A

2

S1A

S3A

6 DA

5S4A

7DB

8

S4B

16

EN

15

A0

14

A1

13

GND

TOP VIEW

(Not to S cale)

ADG5209

NOTES

1. THE EXPOSED PAD IS CONNECTE D INTERNALLY . FOR INCREASED REL IABILIT Y OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE P AD BE S OLDERED TO THE SUBSTRAT E , V

SS

.

09917-005

10 8 S4B

Source Terminal 4B. This pin can be an input or an output.

15

13

GND

Ground (0 V) Reference.

Figure 4. ADG5209 Pin Configuration (TSSOP)

Figure 5. ADG5209 Pin Configuration (LFCSP)

Table 10. ADG5209 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input. 2 16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,

Ax logic inputs determine the on switches.

3 1 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected

to ground. 4 2 S1A Source Terminal 1A. This pin can be an input or an output. 5 3 S2A Source Terminal 2A. This pin can be an input or an output. 6 4 S3A Source Terminal 3A. This pin can be an input or an output. 7 5 S4A Source Terminal 4A. This pin can be an input or an output. 8 6 DA Drain Terminal A. This pin can be an input or an output. 9 7 DB Drain Terminal B. This pin can be an input or an output.

11 9 S3B Source Terminal 3B. This pin can be an input or an output. 12 10 S2B Source Terminal 2B. This pin can be an input or an output. 13 11 S1B Source Terminal 1B. This pin can be an input or an output. 14 12 VDD Most Positive Power Supply Potential.

16 14 A1 Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, V

.

SS

Table 11. ADG5209 Truth Table

A1 A0 EN On Switch Pair

X1 X1 0 None 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4

1

X is don’t care.

Rev. A | Page 11 of 24

ADG5208/ADG5209 Data Sheet

160

0

20

40

60

80

100

120

140

–25 –20 –15 –10 –5 0 5 10 15 20 25

ON RESISTANCE (Ω)

VS, V

D

(V)

TA = 25°C

VDD = +18V V

SS

= –18V

V

DD

= +20V

V

SS

= –20V

V

DD

= +22V

V

SS

= –22V

09917-006

250

200

150

100

50

0

–20 –15 –10 –5 0 5 10 15 20

ON RESISTANCE (Ω)

V

S

, VD (V)

T

A

= 25°C

VDD = +9V V

SS

= –9V

V

DD

= +13.2V

V

SS

= –13.2V

V

DD

= +15V

V

SS

= –15V

VDD = +16.5V V

SS

= –16.5V

09917-007

500

450

400

350

300

250

200

150

100

50

0

0 1412108642

ON RESISTANCE (Ω)

VS, VD (V)

TA = 25°C

VDD = 9V V

SS

= 0V

V

DD

= 10.8V

V

SS

= 0V

VDD = 12V V

SS

= 0V

VDD = 13.2V V

SS

= 0V

09917-008

160

140

120

100

80

60

40

20

0

0 403530252015105

ON RESISTANCE (Ω)

VS, VD (V)

TA = 25°C

VDD = 32.4V V

SS

= 0V

VDD = 36V V

SS

= 0V

V

DD

= 39.6V

V

SS

= 0V

09917-009

250

200

150

100

50

0

–15 –10 –5 0 5 10 15

ON RESISTANCE (Ω)

VS,VD (V)

VDD = +15V V

SS

= –15V

TA = +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09917-010

200

160

120

80

40

180

140

100

60

20

0

–20 –15 –10 –5 0 5 10 2015

ON RESISTANCE (Ω)

VS,VD (V)

VDD = +20V V

SS

= –20V

T

A

= +125°C

TA = +85°C

T

A

= +25°C

T

A

= –40°C

09917-011

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. RON as a Function of VS, VD (±20 V Dual Supply)

Figure 7. RON as a Function of VS, VD (±15 V Dual Supply)

Figure 9. RON as a Function of VS, VD (36 V Single Supply)

Figure 10. RON as a Function of VS, VD for Different Temperatures,

±15 V Dual Supply

Figure 8. RON as a Function of VS, VD (12 V Single Supply)

Figure 11. RON as a Function of VS, VD for Different Temperatures,

±20 V Dual Supply

Rev. A | Page 12 of 24

Data Sheet ADG5208/ADG5209

500

400

300

200

100

450

350

250

150

50

0

0 2 4 6 8 10 12

ON RESISTANCE (Ω)

VS,VD (V)

VDD = 12V V

SS

= 0V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09917-012

250

200

100

150

50

0

0 3530252015105

ON RESISTANCE (Ω)

VS,VD (V)

VDD = 36V V

SS

= 0V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

09917-013

50

–250

–200

–150

–100

–50

0

0 1251007550

25

LEAKAGE CURRENT (pA)

TEMPERATURE (°C)

VDD = +15V V

SS

= –15V

V

BIAS

= +10V/–10V

IS (OFF) + –

I

S

(OFF) – +

ID, I

S

(ON) + +

ID (OFF) + –

ID (OFF) – +

ID, I

S

(ON) – –

09917-014

100

–200

–150

–100

–50

0

50

0 1251007550

25

LEAKAGE CURRENT (pA)

TEMPERATURE (°C)

V

DD

= +20V

V

SS

= –20V

V

BIAS

= +15V/–15V

I

S

(OFF) + –

I

S

(OFF) – +

I

D

, I

S

(ON) + +

I

D

(OFF) + –

I

D

(OFF) – +

I

D

, I

S

(ON) – –

09917-015

100

–700

–600

–500

–400

–300

–200

–100

0

0 125100755025

LEAKAGE CURRENT (pA)

TEMPERATURE (°C)

VDD = 12V V

SS

= 0V

V

BIAS

= 1V/10V

IS (OFF) + –

IS (OFF) – +

ID, IS (ON) + +

ID (OFF) + –

I

D

(OFF) – +

I

D

, IS (ON) – –

09917-016

200

–1000

–800

–600

–400

–200

0

0 12510075

5025

LEAKAGE CURRENT (pA)

TEMPERATURE (°C)

VDD = 36V V

SS

= 0V

V

BIAS

= 1V/30V

IS (OFF) + –

I

S

(OFF) – +

ID, I

S

(ON) + +

ID (OFF) + –

I

D

(OFF) – +

ID, IS (ON) – –

09917-017

Figure 12. RON as a Function of VS, VD for Different Temperatures,

12 V Single Supply

Figure 13. RON as a Function of VS, VD for Different Temperatures,

36 V Single Supply

Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply

Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply

Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply

Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply

Rev. A | Page 13 of 24

ADG5208/ADG5209 Data Sheet

0

–140

–120

–100

–80

–60

–40

–20

10k 100k 1G100M10M1M

OFF ISOLATION (dB)

FREQUENCY ( Hz )

TA = 25°C V

DD

= +15V

V

SS

= –15V

09917-018

0

–140

–120

–100

–80

–60

–40

–20

10k 100k 1G100M10M1M

CROSSTAL K ( dB)

FREQUENCY ( Hz )

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

BETWEEN S 1 AND S 2

BETWEEN S 1 AND S 8

09917-019

16

0

2

4

6

8

10

12

14

–20 –10 0 10 20 30 40

CHARGE INJECT ION (pC)

VS (V)

TA = 25°C DEMUX (DRAIN T O SOURCE)

VDD = +20V V

SS

= –20V

V

DD

= +15V

V

SS

= –15V

V

DD

= +36V

V

SS

= 0V

V

DD

= +12V

V

SS

= 0V

09917-020

0

–120

–100

–80

–60

–40

–20

1k 10k 100k 10M1M

ACPSRR (dB)

FREQUENCY ( Hz )

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

NO DECOUPL ING

CAPACITORS

DECOUPLING

CAPACITORS

09917-021

–6

–12

–11

–10

–9

–8

–7

100k 1M 10M 1G100M

ATTENUATION (dB)

FREQUENCY ( Hz )

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

ADG5208 ADG5209

09917-023

6

–2

–1

0

1

2

3

4

5

–20 –10 0 10 20 30 40

CHARGE INJECT ION (pC)

VS (V)

TA = 25°C MUX (SOURCE TO DRAIN)

VDD = +20V V

SS

= –20V

V

DD

= +15V

V

SS

= –15V

V

DD

= +36V

V

SS

= 0V

V

DD

= +12V

V

SS

= 0V

09917-039

Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply

Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply

Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply

Figure 22. Bandwidth

Figure 20. Charge Injection vs. Source Voltage, Drain to Source

Figure 23. Charge Injection vs. Source Voltage, Source to Drain

Rev. A | Page 14 of 24

Data Sheet ADG5208/ADG5209

350

0

50

100

150

200

250

300

–40 –20 0 20 40 60 80 100 120

TIME (ns)

TEMPERATURE (°C)

VDD = +12V V

SS

= 0V

V

DD

= +15V

V

SS

= –15V

V

DD

= +20V

V

SS

= –20V

V

DD

= +36V

V

SS

= 0V

09917-024

40

35

30

25

20

15

10

5

0

–15 –10 151050–5

CAPACITANCE (pF)

VS (V)

TA = 25°C V

DD

= +15V

V

SS

= –15V

SOURCE/DRAI N ON

DRAIN OFF

SOURCE OF F

09917-025

80

70

60

50

40

30

20

10

0

–15 –10 151050–5

CAPACITANCE (pF)

VS (V)

TA = 25°C V

DD

= +15V

V

SS

= –15V

SOURCE/DRAI N ON

DRAIN OFF

SOURCE OF F

09917-040

Figure 24. t

Times vs. Temperature

TRANSITION

Figure 25. ADG5209 Capacitance vs. Source Voltage, ±15 V Dual Supply

Figure 26. ADG5208 Capacitance vs. Source Voltage, ±15 V Dual Supply

Rev. A | Page 15 of 24

ADG5208/ADG5209 Data Sheet

Sx D

A

V

D

I

D

(ON)

NC

NC = NO CONNECT

09917-027

Sx D

V

S

V1

I

DS

RON = V1/I

DS

09917-028

CHANNEL-TO - CHANNE L CROSSTAL K = 20 log

V

OUT

GND

S1

D

S2

V

OUT

NETWORK

ANALYZER

R

L

50Ω

R

L

50Ω

V

S

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

09917-029

V

S

V

D

Sx D

A

I

S

(OFF) I

D

(OFF)

09917-031

V

OUT

50Ω

NETWORK

ANALYZER

R

L

50Ω

Sx

D

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

GND

50Ω

OFF ISOLATION = 20 log

V

OUT

V

S

09917-030

V

OUT

50Ω

NETWORK ANALYZER

R

L

50Ω

Sx

D

INSERTION LOSS = 20 log

V

OUT

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

GND

09917-033

TEST CIRCUITS

Figure 27. On Leakage

Figure 28. On Resistance

Figure 30. Off Leakage

Figure 31. Off Isolation

Figure 29. Channel-to-Channel Crosstalk

Figure 32. Bandwidth

Rev. A | Page 16 of 24

Data Sheet ADG5208/ADG5209

3V

0V

OUTPUT

t

r

< 20ns

t

f

< 20ns ADDRESS DRIVE (V

IN

)

t

TRANSITION

t

TRANSITION

50% 50%

90%

OUTPUT

ADG5208*

A0 A1 A2

50Ω

300Ω

GND

S1

S2 TO S7

S8

D

35pF

V

IN

2.0V EN

V

DD

V

SS

V

DD

V

SS

V

S1

V

S8

*

SIMIL AR CONNECTION FOR ADG5209.

09917-034

OUTPUT

ADG5208*

A0 A1 A2

50Ω

300Ω

GND

S1

S2 TO S7

S8

D

35pF

V

IN

2.0V

EN

V

DD

V

SS

V

DDVSS

V

S

*

SIMIL AR CONNECTION FOR ADG5209.

3V

0V

OUTPUT

80% 80%

ADDRESS DRIVE (V

IN

)

t

D

09917-035

OUTPUT

ADG5208*

A0 A1 A2

50Ω

300Ω

GND

S1

S2 TO S8

D

35pF

V

IN

EN

V

DD

V

SS

V

DDVSS

V

S

*SIMIL AR CONNECTION FOR ADG5209.

3V

0V

OUTPUT

50% 50%

t

OFF

(EN)

t

ON

(EN)

0.9V

OUT

0.1V

OUT

ENABLE DRIVE (VIN)

09917-036

Figure 33. Address to Output Switching Times, t

TRANSITION

Figure 34. Break-Before-Make Time Delay, t

D

(EN), t

(EN)

OFF

Figure 35. Enable Delay, t

Rev. A | Page 17 of 24

ON

ADG5208/ADG5209 Data Sheet

3V

V

IN

V

OUT

Q

INJ

= C

L

× ΔV

OUT

ΔV

OUT

DS

EN

GND

C

L

1nF

V

OUT

V

IN

R

S

V

S

V

DD

V

SS

V

DDVSS

A0 A1 A2

ADG5208*

*SIMIL AR CONNECTION FOR ADG5209.

09917-037

Figure 36. Charge Injection

Rev. A | Page 18 of 24

Data Sheet ADG5208/ADG5209

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

V

, VS

D

V

and VS represent the analog voltage on Terminal D and

D

Terminal S, respec tively.

R

ON

R

is the ohmic resistance between Terminal D and

ON

Terminal S.

∆R

ON

∆R

represents the difference between the RON of any two

ON

channels.

R

FL AT (ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by R

(Off)

I

S

I

(Off) is the source leakage current with the switch off.

S

I

(Off)

D

I

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

I

D

I

(On) and IS (On) represent the channel leakage currents with

D

FLAT (ON)

.

the switch on.

V

INL

V

is the maximum input voltage for Logic 0.

INL

V

INH

V

is the minimum input voltage for Logic 1.

INH

I

, I

INL

INH

I

INL

and I

represent the low and high input currents of the

INH

digital inputs.

C

(Off)

D

C

(Off) represents the off switch drain capacitance, which is

D

measured with reference to ground.

C

(Off)

S

C

(Off) represents the off switch source capacitance, which is

S

measured with reference to ground.

C

(On), CS (On)

D

C

(On) and CS (On) represent on switch capacitances, which

D

are measured with reference to ground.

C

IN

C

represents digital input capacitance.

IN

t

(EN)

ON

t

(EN) represents the delay time between the 50% and 90%

ON

points of the digital input and switch on condition.

t

(EN)

OFF

t

(EN) represents the delay time between the 50% and 90%

OFF

points of the digital input and switch off condition.

t

TRANSIT ION

t

TRANSITION

represents the delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another.

Break-Before-Make Time Delay (t

t

represents the off time measured between the 80% point of

D

)

D

both switches when switching from one address state to an other.

Off Isolation

Off isolation is a measure of unwanted signal coupling through an off channel.

Charge Injection

Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated by 3 dB.

On Response

On response is the frequency response of the on switch.

AC Power Supply Rejection Ratio (ACPSRR)

ACPSRR is a measure of the ability of a device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

Rev. A | Page 19 of 24

ADG5208/ADG5209 Data Sheet

NMOS

PMOS

P WELL N WE LL

BURIED OXI DE LAYER

HANDLE WAFE R

TRENCH

09917-038

TRENCH ISOLATION

In the ADG5208/ADG5209, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch.

Figure 37. Trench Isolation

Rev. A | Page 20 of 24

Data Sheet ADG5208/ADG5209

APPLICATIONS INFORMATION

The ADG52xx family of switches and multiplexers provides a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5208/ADG5209 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V.

Rev. A | Page 21 of 24

ADG5208/ADG5209 Data Sheet

16

9

81

PIN 1

SEATING PLANE

8° 0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20 MAX

0.20

0.09

0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLI ANT TO JEDEC STANDARDS MO-153-AB

2.70

2.60 SQ

2.50

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

1

0.65

BSC

BOTTOMVIEWTOP VIEW

16

5

8

9

12

13

4

EXPOSED

PAD

PIN 1 INDICATOR

4.10

4.00 SQ

3.90

0.45

0.40

0.35

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

0.35

0.30

0.25

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

08-16-2010-C

OUTLINE DIMENSIONS

Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

(CP-16-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG5208BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5208BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5208BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17 ADG5209BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17 ADG5209BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5209BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

Z = RoHS Compliant Part.

Rev. A | Page 22 of 24

Data Sheet ADG5208/ADG5209

NOTES

Rev. A | Page 23 of 24

ADG5208/ADG5209 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D09917-0-3/12(A)

Rev. A | Page 24 of 24

Datasheet ADG5208 Datasheet (ANALOG DEVICES)

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±15 V DUAL SUPPLY

±20 V DUAL SUPPLY

12 V SINGLE SUPPLY

36 V SINGLE SUPPLY

CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

TERMINOLOGY

TRENCH ISOLATION

APPLICATIONS INFORMATION

OUTLINE DIMENSIONS

ORDERING GUIDE