Datasheet ADG5204 Datasheet (ANALOG DEVICES)

High Voltage, Latch-Up Proof,

S

S

S3S

FEATURES

Latch-up proof
3 pF off source capacitance
26 pF off drain capacitance

−0.6 pC charge injection
Low leakage: 0.4 nA maximum at 85°C
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V

to VDD analog signal range

SS

APPLICATIONS

Automatic test equipment
Data acquisition
Instrumentation
Avio nics
Audio and video switching
Communication systems

4-Channel Multiplexer

ADG5204

FUNCTIONAL BLOCK DIAGRAM

ADG5204

1

2

4

A0 A1 EN

1 OF 4

DECODERS

Figure 1.

D

09768-001

GENERAL DESCRIPTION

The ADG5204 is a complementary metal oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the ADG5204 suitable for video signal switching.

The ADG5204 is designed on a trench process, which guards
against latch-up. A dielectric trench separates the P and N
channel transistors, thereby preventing latch-up even under
severe overvoltage conditions.

The ADG5204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch con­ducts equally well in both directions when on, and each switch
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action.

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors,
thereby preventing latch-up even under severe overvoltage
conditions.

2. Ultralow Capacitance and <1 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the
ADG5204 can be operated from dual supplies up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the
ADG5204 can be operated from a single rail power supply
up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

V

INH

6. No V

= 2.0 V, V

Logic Power Supply Required.

L

= 0.8 V.

INL

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADG5204

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 4

12 V Single Supply........................................................................ 5

36 V Single Supply........................................................................ 6

Continuous Current per Channel, Sx or D............................... 7

REVISION HISTORY

5/11—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions............................9

Truth Table .....................................................................................9

Typical Performance Characteristics........................................... 10

Test Circuits..................................................................................... 14

Terminology.................................................................................... 16

Trench Isolation.............................................................................. 17

Applications Information.............................................................. 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG5204

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V max
On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA, see Figure 24
200 250 280 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match

Between Channels, ∆R

ON

8 9 10 Ω max
On-Resistance Flatness, R

FLAT(ON)

50 65 70 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ

0.1 0.4 1.2 nA max
Channel On Leakage, ID, IS (On) 0.02 nA typ VS = VD = ±10 V, see Figure 26

0.2 0.5 1.2 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

175 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

230 285 320 ns max VS = 10 V, see Figure 29
tON (EN) 155 ns typ RL = 300 Ω, CL = 35 pF
205 255 285 ns max VS = 10 V, see Figure 31
t

(EN) 150 ns typ RL = 300 Ω, CL = 35 pF

OFF

175 200 215 ns max VS = 10 V, see Figure 31
Break-Before-Make Time Delay, tD 80 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V, see Figure 30

Charge Injection, Q

−0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32

INJ

Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28

−3 dB Bandwidth 136 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 27
Insertion Loss −6.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
CS (Off) 3 pF typ VS = 0 V, f = 1 MHz
CD (Off) 26 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 30 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/max GND = 0 V

1

Guaranteed by design; not subject to production test.

4.5 Ω typ V

= ±10 V, IS = −1 mA

S

38 Ω typ VS = ±10 V, IS = −1 mA

V

= VS = ±10 V, VD = ∓10 V, see Figure 23

S

V

= VS = ±10 V, VD = ∓10 V, see Figure 23

S

or VDD

GND

Rev. 0 | Page 3 of 20

ADG5204

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V max
On Resistance, RON 140 Ω typ VS = ±15 V, IS = −1 mA, see Figure 24
160 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match

Between Channels, ∆R

ON

8 9 10 Ω max
On-Resistance Flatness, R

FLAT(ON)

45 55 60 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ

0.1 0.4 1.2 nA max
Channel On Leakage, ID, IS (On) 0.02 nA typ VS = VD = ±15 V, see Figure 26

0.2 0.5 1.2 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

160 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

215 260 290 ns max VS = 10 V, see Figure 29
tON (EN) 150 ns typ RL = 300 Ω, CL = 35 pF
185 225 255 ns max VS = 10 V, see Figure 31
t

(EN) 150 ns typ RL = 300 Ω, CL = 35 pF

OFF

175 195 210 ns max VS = 10 V, see Figure 31
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 10 V, see Figure 30

Charge Injection, Q

−0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32

INJ

Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz,

Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28

−3 dB Bandwidth 150 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 27
Insertion Loss −6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
CS (Off) 3 pF typ VS = 0 V, f = 1 MHz
CD (Off) 26 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 30 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 μA typ Digital inputs = 0 V or VDD
70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/max GND = 0 V

1

Guaranteed by design; not subject to production test.

4.5 Ω typ V

= ±15 V, IS = −1 mA

S

33 Ω typ VS = ±15 V, IS = −1 mA

V

= ±15 V, VD = ∓15 V, see Figure 23

S

V

= ±15 V, VD = ∓15 V, see Figure 23

S

or VDD

GND

see Figure 25

Rev. 0 | Page 4 of 20

ADG5204

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V max
On Resistance, RON 340 Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 24
500 610 700 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match

Between Channels, ∆R

ON

20 21 22 Ω max
On-Resistance Flatness, R

FLAT(ON)

280 335 370 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23

0.1 0.4 1.2 nA max
Channel On Leakage, ID, IS (On) 0.02 nA typ VS = VD = 1 V/10 V, see Figure 26

0.2 0.5 1.2 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

240 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

350 445 515 ns max VS = 8 V, see Figure 29
tON (EN) 250 ns typ RL = 300 Ω, CL = 35 pF
335 420 485 ns max VS = 8 V, see Figure 31
t

(EN) 160 ns typ RL = 300 Ω, CL = 35 pF

OFF

195 220 240 ns max VS = 8 V, see Figure 31
Break-Before-Make Time Delay, tD 140 ns typ RL = 300 Ω, CL = 35 pF

60 ns min VS1 = VS2 = 8 V, see Figure 30

Charge Injection, Q

−1.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 32

INJ

Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28

−3 dB Bandwidth 106 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 27
Insertion Loss −11 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
CS (Off) 3.5 pF typ VS = 6 V, f = 1 MHz
CD (Off) 29 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 33 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 μA typ Digital inputs = 0 V or VDD
65 μA max
VDD 9/40 V min/max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

5 Ω typ V

= 0 V to 10 V, IS = −1 mA

S

145 Ω typ VS = 0 V to 10 V, IS = −1 mA

or VDD

GND

Rev. 0 | Page 5 of 20

ADG5204

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V max
On Resistance, RON 150 Ω typ VS = 0 V to 30 V, IS = −1 mA, see Figure 24
170 215 245 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match

Between Channels, ∆R

ON

8 9 10 Ω max
On-Resistance Flatness, R

FLAT(ON)

50 60 65 Ω max
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V

Source Off Leakage, IS (Off) 0.01 nA typ VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23

0.1 0.4 1.2 nA max
Channel On Leakage, ID, IS (On) 0.02 nA typ VS = VD = 1 V/30 V, see Figure 26

0.2 0.5 1.2 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

180 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

250 275 305 ns max VS = 18 V, see Figure 29
tON (EN) 170 ns typ RL = 300 Ω, CL = 35 pF
220 251 285 ns max VS = 18 V, see Figure 31
t

(EN) 170 ns typ RL = 300 Ω, CL = 35 pF

OFF

210 215 220 ns max VS = 18 V, see Figure 31
Break-Before-Make Time Delay, tD 80 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 18 V, see Figure 30

Charge Injection, Q

−0.6 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 32

INJ

Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28

−3 dB Bandwidth 136 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 27
Insertion Loss −6.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27
CS (Off) 3 pF typ VS = 18 V, f = 1 MHz
CD (Off) 26 pF typ VS = 18 V, f = 1 MHz
CD, CS (On) 30 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

IDD 85 μA typ Digital inputs = 0 V or VDD
100 130 μA max
VDD 9/40 V min/max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

4.5 Ω typ V

= 0 V to 30 V, IS = −1 mA

S

35 Ω typ VS = 0 V to 30 V, IS = −1 mA

or VDD

GND

Rev. 0 | Page 6 of 20

ADG5204

CONTINUOUS CURRENT PER CHANNEL, Sx OR D

Table 5.

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR D PINS

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 24.5 7.5 2.8 mA max
LFCSP (θJA = 30.4°C/W) 35.7 7.7 2.8 mA max

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 26 7.5 2.8 mA max
LFCSP (θJA = 30.4°C/W) 37 7.7 2.8 mA max

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 18 7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 28 7.7 2.8 mA max

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 30 7.7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 41 7.7 2.8 mA max

Rev. 0 | Page 7 of 20

ADG5204

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1

Digital Inputs1

Peak Current, Sx or D Pins

Continuous Current, Sx or D2 Data + 15%
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θJA

16-Lead TSSOP, θJA Thermal

Impedance (4-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance (4-Layer Board)

Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at the Sx and D pins are clamped by internal diodes. Limit

current to the maximum ratings given.

2

See . Table 5

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first
81 mA (pulsed at 1 ms,

10% duty cycle maximum)

112.6°C/W

30.4°C/W

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any
one time.

ESD CAUTION

Rev. 0 | Page 8 of 20

ADG5204

2

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EN

A0

NC

1

A0

2

EN

3

V

SS

4

S1

(Not to Scale)

5

S2

6

D

7

NC

NC = NO CONNECT

ADG5204

TOP VIEW

14

A1

13

GND

12

V

DD

11

S3

10

S4

9

NC

8

NC

09768-002

NOTES

1. NC = NO CONNECT .
. EXPOSED PAD TIED TO SUBSTRATE,

Figure 2. TSSOP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input.
2 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are off.

When this pin is high, the Ax logic inputs determine the on switches.
3 1 VSS Most Negative Power Supply Potential.
4 3 S1 Source Terminal. Can be an input or an output.
5 4 S2 Source Terminal. Can be an input or an output.
6 6 D Drain Terminal. Can be an input or an output.
7 to 9 2, 5, 7, 8, 13 NC No Connect. These pins are open.
10 9 S4 Source Terminal. Can be an input or an output.
11 10 S3 Source Terminal. Can be an input or an output.
12 11 VDD Most Positive Power Supply Potential.
13 12 GND Ground (0 V) Reference.
14 14 A1 Logic Control Input.
N/A1 EP Exposed Pad

Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder

joints and maximum thermal capability, it is recommended that the pad be soldered to the

.

SS

1

N/A means not applicable.

substrate, V

1V

SS

2NC

3S1

4S2

Figure 3. LFCSP Pin Configuration

A1

14

16

15

ADG5204

TOP VIEW

(Not to Scale)

7

5

6

D

NC

NC

13

8

NC

12 GND

11 V

DD

10 S3

9S4

.

SS

09768-003

TRUTH TABLE

Table 8.

EN A1 A0 S1 S2 S3 S4

0 X1 X1 Off Off Off Off
1 0 0 On Off Off Off
1 0 1 Off On Off Off
1 1 0 Off Off On Off
1 1 1 Off Off Off On

1

X is don’t care.

Rev. 0 | Page 9 of 20

ADG5204

TYPICAL PERFORMANCE CHARACTERISTICS

160

TA = 25°C

140

120

VDD = +18V
V

= –18V

SS

160

140

120

TA = 25°C

VDD = 32.4V
V

= 0V

SS

100

V

80

60

ON RESISTANCE (Ω)

40

20

0

–25 –20 –15 –10 –5 0 5 10 15 20 25

Figure 4. R

250

TA = 25°C

200

150

100

ON RESISTANCE ( Ω)

50

0

–20 –15 –10 –5 0 5 10 15 20

Figure 5. R

500

TA = 25°C

450

400

350

300

250

200

ON RESISTANCE ( Ω)

150

100

50

0

01412108642

Figure 6. R

= +20V

DD

V

= –20V

SS

VS, VD (V)

as a Function of VD or VS, Dual Supply

ON

VDD = +16.5V
V

= –16.5V

SS

VDD = +15V
V

= –15V

SS

VS, VD (V)

as a Function of VD or VS, Dual Supply

ON

VDD = 9V
V

= 0V

SS

VDD = 10.8V
V

SS

VS, VD (V)

as a Function of VD or VS, Single Supply

ON

= +22V

V

DD

V

= –22V

SS

VDD = +9V
V

= –9V

SS

VDD = +13.2V
V

= –13.2V

SS

= 0V

VDD = 12V
V

= 0V

SS

VDD = 13.2V
V

= 0V

SS

100

80

60

ON RESISTANCE (Ω)

40

20

0

043530252015105

09768-104

09768-105

Figure 7. R

250

VDD = +15V
V

SS

200

150

100

ON RESISTANCE ( Ω)

50

0

–15 –10 –5 0 5 10 15

Figure 8. R

as a Function of VD or VS, Single Supply

ON

= –15V

as a Function of VD or VS, for Different Temperatures,

ON

VDD = 36V
V

= 0V

SS

VS, VD (V)

TA = +125°C

T

= +85°C

A

= +25°C

T

A

T

= –40°C

A

VS,VD (V)

VDD = 39.6V
V

= 0V

SS

0

09768-107

09768-108

±15 V Dual Supply

200

180

160

140

120

100

80

ON RESISTANCE ( Ω)

60

40

20

VDD = +20V
V

= –20V

SS

0

–20 –15 –10 –5 0 5 10 2015

09768-106

Figure 9. R

as a Function of VD or VS, for Different Temperatures,

ON

T

= +125°C

A

T

= +85°C

A

= +25°C

T

A

= –40°C

T

A

VS,VD (V)

09768-109

±20 V Dual Supply

Rev. 0 | Page 10 of 20

ADG5204

500

450

= +125°C

400

340

T

A

T

A

= +85°C

300

= +25°C

T

250

200

ON RESISTANCE ( Ω)

150

A

= –40°C

T

A

100

50

VDD = 12V
V

= 0V

SS

0

024681012

VS,VD (V)

Figure 10. R

as a Function of VD or VS for Different Temperatures,

ON

12 V Single Supply

250

VDD = 36V

= 0V

V

SS

200

T

= +125°C

150

100

ON RESISTANCE (Ω)

A

T

= +85°C

A

= +25°C

T

A

T

= –40°C

A

50

0

03530252015105

VS,VD (V)

Figure 11. R

as a Function of VD or VS for Different Temperatures,

ON

36 V Single Supply

10

ID (OFF) – +

I

D,IS

(ON) + +

0

–10

(OFF) + –

I

–20

–30

D

(ON) – –

I

D,IS

–40

LEAKAGE CURRENT (p A)

–50

VDD = +15V

–60

V

= –15V

SS

V

= +10V/–10V

BIAS

–70

0 20 40 60 80 100 120

TEMPERATURE (°C)

I

(OFF) + –

S

(OFF) – +

I

S

Figure 12. Leakage Current vs. Temperature, ±15 V Dual Supply

09768-110

09768-111

09768-112

100

I

(OFF) + –

S

I

D,IS

(ON) + +

I

(OFF) – +

D

50

0

(OFF) – +

I

S

–50

I

(OFF) + –

–100

LEAKAGE CURRENT (p A)

–150

VDD = +20V
V

= –20V

SS

V

= +15V/–15V

BIAS

–200

0 20 40 60 80 100 120

D

I

(ON) – –

D,IS

TEMPERATURE (°C)

Figure 13. Leakage Current vs. Temperature, ±20 V Dual Supply

40

20

0

–20

–40

–60

LEAKAGE CURRENT (p A)

–80

VDD = 12V

–100

V

= 0V

SS

V

= 1V/10V

BIAS

–120

0 20406080100120

(OFF) + –

I

S

I

(OFF) – +

S

I

D,IS

TEMPERATURE ( °C)

(ON) + +

I

(OFF) + –

D

I

D,IS

I

(OFF) – +

D

(ON) – –

Figure 14. Leakage Current vs. Temperature, 12 V Single Supply

50

I

(OFF) – +

D

ID,IS (ON) + +

0

–50

–100

I

(OFF) + –

–150

D

LEAKAGE CURRENT (p A)

–200

VDD = 36V
V

= 0V

SS

V

= 1V/30V

BIAS

–250

0 20406080100120

TEMPERATURE ( °C)

I

D,IS

I

(OFF) + –

S

(OFF) – +

I

S

(ON) – –

Figure 15. Leakage Current vs. Temperature, 36 V Single Supply

09768-113

09768-114

09768-115

Rev. 0 | Page 11 of 20

ADG5204

0

TA = 25°C
V

DD

V

SS

–20

= +15V
= –15V

350

300

–40

–60

–80

OFF ISOLATION (dB)

–100

–120

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

–40

BETWEEN S1 AND S2

–60

CROSSTALK (dB)

–80

BETWEEN S1 AND S4

–100

–120

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply

2.5
TA = 25°C

2.0

1.5

1.0

0.5

0

–0.5

–1.0

CHARGE INJECTI ON (pC)

–1.5

–2.0

–2.5

–20 –10 0 10 20 30 40

V
V

DD

SS

= +15V
= –15V

V

V

V
V

DD

V

S

= +20V

DD

= –20V

SS

= +12V

= 0V

SS

(V)

V

DD

V

SS

Figure 18. Charge Injection vs. Source Voltage

= +36V

= 0V

250

VDD = +12V
V

= 0V

SS

200

150

TIME (ns)

V
V

DD
SS

= +20V

= –20V

100

50

0

–40 –20 0 20 40 60 80 100 120

09768-116

V
V

TEMPERATURE (°C)

DD
SS

V
V

= +15V
= –15V

DD
SS

= +36V
= 0V

09768-120

Figure 19. Transition Time vs. Temperature

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

–40

–60

ACPSRR (dB)

–80

–100

–120

1k 10k 100k 1M 10M

09768-117

NO DECOUPLING CAPACITORS

DECOUPLING CAPACITORS

FREQUENCY (Hz)

09768-121

Figure 20. ACPSRR vs. Frequency, ±15 V Dual Supply

40

TA = 25°C
V

= +15V

DD

35

V

= –15V

SS

30

25

20

15

CAPACITANCE (pF )

10

5

0

–15 –10 –5 0 5 10 15

09768-119

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

(V)

S

09768-123

Figure 21. Capacitance vs. Source Voltage, Dual Supply

Rev. 0 | Page 12 of 20

ADG5204

0

TA = 25°C
V

= +15V

DD

–2

V

= –15V

SS

–4

–6

–8

–10

–12

ATTENUATION (dB)

–14

–16

–18

–20

100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 22. Bandwidth

09768-125

Rev. 0 | Page 13 of 20

ADG5204

V

V

V

V

V

V

V

V

TEST CIRCUITS

IS (OFF) ID (OFF)

A A

Sx D

NC

Sx D

ID (ON)

A

0.1µF

S

S

DD

V

DDVSS

Sx

GND

Figure 23. Off Leakage

V

Sx D

Figure 24. On Resistance

SS

0.1µF

50Ω

D

V

D

09768-006

DD

0.1µF

V

DDVSS

Sx

I

DS

09768-005

NC = NO CONNECT

Figure 26. On Leakage

SS

0.1µF

D

GND

INSERTION LOSS = 20 log

V

D

NETWORK

ANALYZER

50Ω

R

L

50Ω

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

09768-007

V

S

V

OUT

09768-009

Figure 27. Bandwidth

DD

GND

SS

0.1µF

V

SS

D

R

L

50Ω

NETWORK

ANALYZER

50Ω

V

OUT

R

L

50Ω

0.1µF

NETWORK

ANALYZER

V

OUT

R

L

50Ω

V

S

V

S

V

DD

S1

S2

OFF ISOLATION = 20 log

Figure 25. Off Isolation

V

OUT

V

S

09768-008

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 28. Channel-to-Channel Crosstalk

V

OUT

V

S

09768-010

Rev. 0 | Page 14 of 20

ADG5204

V

VDDV

V

VDDV

0.1µF

V

IN

2.4V

A1

A0

EN

V

DD

SS

0.1µF

V

V

DD

SS

S1

S2

V

S1

ADDRESS

DRIVE (VIN)

S3

GND

S4

D

R

L

300Ω

V

S4

V

OUT

C

L

35pF

3V

0V

V

OUT

50% 50%

90%

t

TRANSITION

t

TRANSITI ON

90%

09768-012

Figure 29. Address to Output Switching Times

SS

VDDV

0.1µF

SS

S1

S2

V

S1

ADDRESS

DRIVE (V

3V

)

IN

0V

S3

0.1µF

A1

V

IN

300Ω

A0

S4

50% 50%

t

ON

80%

0.9V

(EN)

2.4V

EN

GND

D

R

L

300Ω

Figure 30. Break-Before-Make Time Delay, t

V

DD

SS

VDDV

GND

0.1µF

SS

S1

S2

S3

S4

D

R

L

300Ω

0.1µF

A1

A0

EN

V

IN

300Ω

V

OUT

C

L

35pF

ENABLE

V

S

C

L

35pF

DRIVE (V

OUTPUT

V

OUT

V

OUT

D

3V

)

IN

0V

V

OUT

0V

OUT

80%

t

D

0.1V

OUT

t

(EN)

OFF

09768-013

09768-014

Figure 31. Enable-to-Output Switching Delay

SS

V

V

R

S

V

S

DD

Sx D

DECODER

SS

V

OUT

C

L

1nF

V

OUT

V

Q

= CL × ∆V

INJ

IN

SW OFF

OUT

∆V

OUT

SW OFF

SW ON

GND

SW OFF

V

A2A1

IN

EN

SW OFF

09768-015

Figure 32. Charge Injection

Rev. 0 | Page 15 of 20

ADG5204

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

, VS

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.

I

The source leakage current with the switch off.

I

The drain leakage current with the switch off.

I

The channel leakage current with the switch on.

V

The maximum input voltage for Logic 0.

V

The minimum input voltage for Logic 1.

I

The input current of the digital input.

C

The off switch source capacitance, which is measured with
reference to ground.

C

The off switch drain capacitance, which is measured with
reference to ground.

C

The on switch capacitance, which is measured with reference to
ground.

FLAT(ON)

(Off)

S

(Off)

D

, IS (On)

D

INL

INH

, I

INL

INH

(Off)

S

(Off)

D

(On), CS (On)

D

C

IN

The digital input capacitance.

t

TRANSITION

The delay time between the 50% and 90% points of the digital
input and switch-on condition when switching from one address
state to another.

t

(EN)

ON

The delay between applying the digital control input and the
output switching on. See Figure 31.

t

(EN)

OFF

The delay between applying the digital control input and the
output switching off. See Figure 31.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

ACPSRR (AC Power Supply Rejection Ratio)

The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the device
to avoid coupling noise and spurious signals that appear on the
supply voltage pins to the output of the switch. The dc voltage on
the device is modulated by a sine wave of 0.62 V p-p.

Rev. 0 | Page 16 of 20

ADG5204

TRENCH ISOLATION

In the ADG5204, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. By using trench isolation, this diode is removed, and
the result is a latch-up proof switch.

NMOS PMOS

P WELL N WELL

TRENCH

BURIED OXIDE L AYER

HANDLE WAFER

Figure 33. Trench Isolation

09768-004

Rev. 0 | Page 17 of 20

ADG5204

APPLICATIONS INFORMATION

The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5204 high voltage multiplexer allows
single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V.

Rev. 0 | Page 18 of 20

ADG5204

S

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40
BSC

7

1.20

0.20

MAX

SEATING
PLANE

0.09

8°
0°

0.75

0.60

0.45

061908-A

Figure 34. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

PIN 1

INDICATOR

0.80

0.75

0.70

EATING

PLANE

4.10

4.00 SQ

3.90

0.65
BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

0.35

0.30

0.25

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

N

1

P

I

D

C

I

N

I

16

EXPOSED

1

PAD

4

5

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

2.70

2.60 SQ

2.50

0.20 MIN

R

O

A

T

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

08-16-2010-C

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG5204BRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG5204BRUZ-RL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG5204BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17

1

Z = RoHS Compliant Part.

Rev. 0 | Page 19 of 20

ADG5204

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09768-0-5/11(0)

Rev. 0 | Page 20 of 20