Page 1
LC2MOS
a
FEATURES
+3 V, +5 V or ⴞ5 V Power Supplies
Ultralow Power Dissipation (<0.5 W)
Low Leakage (<100 pA)
Low On Resistance (<50 ⍀)
Fast Switching Times
Low Charge Injection
TTL/CMOS Compatible
16-Lead DIP or SOIC Package
APPLICATIONS
Battery Powered Instruments
Single Supply Systems
Remote Powered Equipment
+5 V Supply Systems
Computer Peripherals such as Disk Drives
Precision Instrumentation
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Sample Hold Systems
Communication Systems
Compatible with ⴞ5 V Supply DACs and ADCs such as
AD7840/8, AD7870/1/2/4/5/6/8
Precision 5 V/3 V Quad SPST Switches
ADG511/ADG512/ADG513
FUNCTIONAL BLOCK DIAGRAMS
S1
IN1
IN2
ADG511
IN3
IN4
IN1
D1
S2
IN2
D2
S3
D3
S4
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
ADG512
IN3
IN4
The ADG511, ADG512 and ADG513 contain four independent SPST switches. The ADG511 and ADG512 differ only in
that the digital control logic is inverted. The ADG511 switch is
turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG512. The ADG513
contains two switches whose digital control logic is similar to
that of the ADG511 while the logic is inverted in the remaining
two switches.
S1
IN1
D1
S2
IN2
D2
S3
D3
S4
D4
ADG513
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
GENERAL DESCRIPTION
The ADG511, ADG512 and ADG513 are monolithic CMOS
ICs containing four independently selectable analog switches.
These switches feature low, well-controlled on resistance and
wide analog signal range, making them ideal for precision
analog signal switching.
These switch arrays are fabricated using Analog Devices’
advanced linear compatible CMOS (LC
2
MOS) process which
offers the additional benefits of low leakage currents, ultralow
power dissipation and low capacitance for fast switching speeds
with minimum charge injection. These features make the
ADG511, ADG512 and ADG513 the optimum choice for a
wide variety of signal switching tasks in precision analog signal
processing and data acquisition systems.
The ability to operate from single +3 V, +5 V or ±5 V bipolar
supplies make the ADG511, ADG512 and ADG513 perfect for
use in battery-operated instruments, 4–20 mA loop systems and
with the new generation of DACs and ADCs from Analog
Devices. The use of 5 V supplies and reduced operating currents
give much lower power dissipation than devices operating from
±15 V supplies.
PRODUCT HIGHLIGHTS
1. +5 Volt Single Supply Operation
The ADG511/ADG512/ADG513 offers high performance,
including low on resistance and wide signal range, fully
specified and guaranteed with +3 V, ±5 V as well as +5 V
supply rails.
2. Ultralow Power Dissipation
CMOS construction ensures ultralow power dissipation.
3. Low R
ON
4. Break-Before-Make Switching
Switches are guaranteed to have break-before-make operation. This allows multiple outputs to be tied together for
multiplexer applications without the possibility of momentary
shorting between channels.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
ADG511/ADG512/ADG513–SPECIFICATIONS
1
Dual Supply
Parameter +25ⴗC+85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
R
ON
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time 100 100 ns typ R
Delay, t
Charge Injection 11 11 pC typ V
OFF Isolation 68 68 dB typ R
Channel-to-Channel Crosstalk 85 85 dB typ R
C
C
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
V
I
I
NOTES
1
Temperature ranges are as follows: B Versions –40°C to +85°C; T Versions –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(ADG513 Only) VS1 = VS2 = +3 V; Test Circuit 5
D
(OFF) 9 9 pF typ f = 1 MHz
S
(OFF) 9 9 pF typ f = 1 MHz
D
DD
SS
DD
SS
(VDD = +5 V ⴞ 10%, VSS = –5 V ⴞ 10%, GND = 0 V, unless otherwise noted)
B Versions T Versions
–40ⴗC to –55ⴗC to
to V
DD
SS
INH
30 30 Ω typ VD = ±3.5 V, I
50 50 Ω max V
(OFF) ±0.025 ±0.025 nA typ VD = ±4.5 V, V
S
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
(OFF) ±0.025 ±0.025 nA typ VD = ±4.5 V, V
D
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
, I
(ON) ±0.05 ±0.05 nA typ V
D
S
±0.2 ±5 ±0.2 ±5 nA max Test Circuit 3
INH
INL
2.4 2.4 V min
0.8 0.8 V max
0.005 0.005 µA typ V
±0.1 ±0.1 µA max
2
200 200 ns typ R
375 375 ns max V
120 120 ns typ R
150 150 ns max V
+4.5/5.5 +4.5/5.5 V min/max
–4.5/–5.5 –4.5/–5.5 V min/max
0.0001 0.0001 µA typ V
11µA max Digital Inputs = 0 V or 5 V
0.0001 0.0001 µA typ
11µA max
VDD to VSSV
= –10 mA;
= +4.5 V, VSS = –4.5 V
DD
= +5.5 V, VSS = –5.5 V
DD
= V
D
= V
IN
= 300 Ω. C
L
= ±3 V; Test Circuit 4
S
= 300 Ω. C
L
= ±3 V; Test Circuit 4
S
= 300 Ω, C
L
= 0 V, R
S
S
= ±4.5 V;
S
or V
INL
L
L
L
= 0 Ω, C
S
= ⫿4.5 V;
S
= ⫿4.5 V;
S
INH
= 35 pF;
= 35 pF;
= 35 pF;
Test Circuit 6
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 7
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 8
= +5.5 V, VSS = –5.5 V
DD
= 10 nF;
L
–2–
REV. B
Page 3
ADG511/ADG512/ADG513
Single Supply
(VDD = +5 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Versions T Versions
–40ⴗC to –55ⴗC to
Parameter +25ⴗC+85ⴗC+25ⴗC +125ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
R
ON
45 45 Ω typ V
DD
75 75 Ω max V
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ±0.025 ±0.025 nA typ V
S
0 V to VDDV
= +3.5 V, IS = –10 mA;
D
= +4.5 V
DD
= +5.5 V
DD
= 4.5/1 V, VS = 1Ⲑ4.5 V;
D
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.025 ±0.025 nA typ V
D
= 4.5/1 V, VS = 1Ⲑ4.5 V;
D
±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2
Channel ON Leakage I
(ON) ±0.05 ±0.05 nA typ V
D
S
= VS = +4.5 V/+1 V;
D
, I
±0.2 ±5 ±0.2 ±5 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 2.4 V min
0.8 0.8 V max
Input Current
I
INL
or I
INH
0.005 0.005 µA typ V
IN
= V
INL
or V
INH
±0.1 ±0.1 µA max
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time 200 200 ns typ R
Delay, t
(ADG513 Only) VS1 = VS2 = +2 V; Test Circuit 5
D
Charge Injection 16 16 pC typ V
2
250 250 ns typ R
500 500 ns max V
50 50 ns typ R
100 100 ns max V
= 300 Ω, C
L
= +2 V; Test Circuit 4
S
= 300 Ω, C
L
= +2 V; Test Circuit 4
S
= 300 Ω, C
L
= 0 V, R
S
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 10 nF;
L
Test Circuit 6
OFF Isolation 68 68 dB typ R
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 7
Channel-to-Channel Crosstalk 85 85 dB typ R
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 8
(OFF) 9 9 pF typ f = 1 MHz
C
S
(OFF) 9 9 pF typ f = 1 MHz
C
D
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
DD
I
DD
0.0001 0.0001 µA typ V
+4.5/5.5 +4.5/5.5 V min/max
= +5.5 V
DD
11µA max Digital Inputs = 0 V or 5 V
NOTES
1
Temperature ranges are as follows: B Versions –40°C to +85°C; T Versions –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
–3–
Page 4
ADG511/ADG512/ADG513–SPECIFICATIONS
1
Single Supply
Parameter +25ⴗC +70ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
R
ON
LEAKAGE CURRENTS V
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
INH
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time 500 ns typ R
Delay, t
Charge Injection 11 pC typ V
OFF Isolation 68 dB typ R
Channel-to-Channel Crosstalk 85 dB typ R
C
C
CD, CS (ON) 35 pF typ f = 1 MHz
POWER REQUIREMENTS
V
DD
I
DD
NOTES
1
Temperature ranges are as follows: B Versions –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(ADG513 Only) VS1 = VS2 = +1 V; Test Circuit 5
D
(OFF) 9 pF typ f = 1 MHz
S
(OFF) 9 pF typ f = 1 MHz
D
(VDD = +3.3 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Versions
0ⴗC to
DD
V
200 Ω typ V
500 Ω max V
(OFF) ±0.025 nA typ V
S
±0.1 ±2.5 nA max Test Circuit 2
(OFF) ±0.025 nA typ V
D
±0.1 ±2.5 nA max Test Circuit 2
, I
(ON) ±0.05 nA typ V
D
S
±0.2 ±5 nA max Test Circuit 3
INH
INL
2.4 V min
0.8 V max
0.005 µA typ V
±0.1 µA max
2
600 ns typ R
1200 ns max V
100 ns typ R
160 ns max V
3/3.6 V min/max
0.0001 µA typ V
1 µA max Digital Inputs = 0 V or 3 V
= +1.5 V, IS = –1 mA;
D
= +3 V
DD
= +3.6 V
DD
= 2.6/1 V, VS = 1Ⲑ2.6 V;
D
= 2.6/1 V, VS = 1Ⲑ2.6 V;
D
= VS = +2.6 V/+1 V;
D
= V
INL
or V
INH
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
IN
= 300 Ω, C
L
= +1 V; Test Circuit 4
S
= 300 Ω, C
L
= +1 V; Test Circuit 4
S
= 300 Ω, C
L
= 0 V, R
S
Test Circuit 6
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 7
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
L
Test Circuit 8
= +3.6 V
DD
= 10 nF;
L
–4–
REV. B
Page 5
ADG511/ADG512/ADG513
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(T
= +25°C unless otherwise noted)
A
V
to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
SS
Analog, Digital Inputs
2
. . . . . . . . . . . VSS –2 V to VDD + 2 V or
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
θ
JA
1
30 mA, Whichever Occurs First
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
θ
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . +300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss
of functionality.
ORDERING GUIDE
Model
1
Temperature Range
2
Package Option
ADG511BN –40°C to +85°C N-16
ADG511BR –40°C to +85°C R-16A
ADG511ABR
ADG511TQ
4
4
–40°C to +85°C R-16A
–55°C to +125°C Q-16
ADG512BN –40°C to +85°C N-16
ADG512BR –40°C to +85°C R-16A
ADG512ABR
ADG512TQ
4
4
–40°C to +85°C R-16A
–55°C to +125°C Q-16
ADG513BN –40°C to +85°C N-16
ADG513BR –40°C to +85°C R-16A
ADG513ABR
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
3.3 V specifications apply over 0°C to +70°C temperature range.
3
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
4
Trench isolated latch-up proof parts. See Trench Isolation section.
4
–40°C to +85°C R-16A
3
REV. B
–5–
Page 6
ADG511/ADG512/ADG513
PIN CONFIGURATION
(DIP/SOIC)
IN1
1
D1
2
S1
3
V
4
SS
GND
TOP VIEW
5
(Not to Scale)
S4
6
D4
7
IN4
8
NC = NO CONNECT
ADG511
ADG512
ADG513
IN2
16
D2
15
S2
14
V
13
DD
12
NC
S3
11
D3
10
IN3
9
Truth Table (ADG511/ADG512)
ADG511 ADG512 Switch
In In Condition
01 ON
1 0 OFF
Truth Table (ADG513)
Switch Switch
Logic 1, 4 2, 3
0 OFF ON
1 ON OFF
TERMINOLOGY
V
DD
V
SS
Most positive power supply potential.
Most negative power supply potential in
dual supplies. In single supply applications,
it may be connected to GND.
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
I
(OFF) Source leakage current with the switch
S
Ohmic resistance between D and S.
“OFF.”
I
(OFF) Drain leakage current with the switch
D
“OFF.”
I
, IS (ON) Channel leakage current with the switch
D
“ON.”
V
) Analog voltage on terminals D, S.
D (VS
C
(OFF) “OFF” switch source capacitance.
S
C
(OFF) “OFF” switch drain capacitance.
D
C
, CS (ON) “ON” switch capacitance.
D
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
D
“OFF” or “ON” time measured between the
90% points of both switches when switching
from one address state to another.
Crosstalk A measure of unwanted signal which is
coupled through from one channel to an-
other as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” switch.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
–6–
REV. B
Page 7
50
FREQUENCY – Hz
10mA
10mA
10nA
10M10
I
SUPPLY
100 1k 10k 100k 1M
1mA
100mA
1mA
100nA
VDD = +5V
V
SS
= –5V
I–, I+
1 SW
4 SW
TEMPERATURE – 8C
10
1
0.001
25 12535
LEAKAGE CURRENT – nA
45 55 65 75 85 95 105 115
0.1
0.01
VDD = +5V
V
SS
= –5V
V
S
= 65V
V
D
= 65V
ID (OFF)
ID (ON)
IS (OFF)
40
Typical Performance Graphs–ADG511/ADG512/ADG513
TA = +258C
30
– V
ON
R
20
10
0
–5 5–4
–3 –2 –1
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
VDD = +3V
V
= –3V
SS
VDD = +5V
= –5V
V
SS
0
1234
Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies
50
VDD = +5V
= –5V
V
SS
40
30
– V
ON
R
20
10
+1258C
+858C
+258C
Figure 4. Supply Current vs. Input Switching Frequency
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures
Figure 3. On Resistance as a Function of VD (VS)
Single Supply
REV. B
0
–5 5–4
90
80
70
60
– V
ON
R
50
40
30
20
051
–3 –2 –1
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
TA = +258C
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
0
1234
VDD = +3V
= 0V
V
SS
VDD = +5V
= 0V
V
SS
234
Figure 5. Leakage Currents as a Function of Temperature
120
VDD = +5V
= –5V
V
SS
100
80
OFF ISOLATION – dB
60
40
100 10M1k
10k 100k 1M
FREQUENCY – Hz
Figure 6. Off Isolation vs. Frequency
–7–
Page 8
ADG511/ADG512/ADG513
+5V
–5V
2200pF
R
C
75V
C
C
1000pF
C
H
2200pF
V
OUT
ADG511
ADG512
ADG513
SW1
SW2
S
S
D
D
+5V
–5V
AD845
+5V
–5V
V
IN
OP07
0.008
0.004
0.002
0.000
–0.002
LEAKAGE CURRENT – nA
–0.004
–0.006
–5 5–4
VDD = +5V
= –5V
V
SS
= +258C
T
A
–3 –2 –1
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
ID (ON)
1234
0
ID (OFF)
IS (OFF)
network R
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±3 V input range.
The acquisition time is 2.5 µs while the settling time is 1.85 µs.
and CC. This compensation network also reduces
C
Figure 7. Leakage Currents as a Function of VD (VS)
110
100
VDD = +5V
= –5V
V
SS
TRENCH ISOLATION
The MOS devices that make up the ADG511A/ADG512A/
Figure 9. Accurate Sample-and-Hold
ADG513A are isolated from each other by an oxide layer
90
(trench) (see Figure 10). When the NMOS and PMOS devices
are not electrically isolated from each other, there exists the
possibility of “latch-up” caused by parasitic junctions between
80
CROSSTALK – dB
70
CMOS transistors. Latch-up is caused when P-N junctions that
are normally reverse biased, become forward biased, causing
large currents to flow. This can be destructive.
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation the N and P wells of the
60
100 10M1k
10k 100k 1M
FREQUENCY – Hz
Figure 8. Crosstalk vs. Frequency
APPLICATION
Figure 9 illustrates a precise sample-and-hold circuit. An AD845
is used as the input buffer while the output operational amplifier
is an OP07. During the track mode, SW1 is closed and the
output V
SW1 is opened and the signal is held by the hold capacitor C
follows the input signal VIN. In the hold mode,
OUT
H
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG511/ADG512/
ADG513 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is
typically 15 µV/µs.
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR)-type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With Trench Isolation, this diode is removed; the
result is a latch-up-proof circuit.
V
G
V
S
V
D
V
G
V
S
V
D
.
+
P
–
N
P-CHANNEL
P
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
+
R
E
N
C
H
T
R
E
N
C
H
+
N
–
P
N-CHANNEL
N
T
+
R
E
N
C
H
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
Figure 10. Trench Isolation
switches will be at the same potential, they will have a differential effect on the op amp OP07, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation
–8–
REV. B
Page 9
SD
V
S
V
D
A
ID (ON)
Test Circuits
ADG511/ADG512/ADG513
I
DS
SD
V
S
RON = V1/I
1. On Resistance
V1
DS
IS (OFF)
V
S
A
SD
2. Off Leakage
V
DD
0.1mF
V
DD
SD
R
C
V
S
IN
V
GND
0.1mF
SS
V
SS
L
300V
L
35pF
I
(OFF)
D
A
V
D
3. On Leakage
3V
V
ADG511
IN
V
OUT
V
IN
ADG512
V
OUT
50% 50%
3V
50% 50%
90% 90%
t
ON
t
OFF
4. Switching Times
V
DD
0.1mF
V
GND
DD
0.1mF
V
C
L1
35pF
OUT1
R
OUT2
L1
300V
D2
R
300V
V
SS
V
SS
V
C
L2
L2
35pF
V
S1
V
S2
S1 D1
S2
IN1, IN2
V
IN
V
V
V
OUT1
OUT2
3V
IN
0V
0V
0V
50% 50%
90%
90%
t
D
90%
t
D
90%
5. Break-Before-Make Time Delay
V
DD
V
DD
R
S
V
S
SD
IN
GND
V
OUT
C
L
10nF
V
SS
V
SS
3V
V
IN
V
OUT
Q
INJ
= CL 3 DV
OUT
DV
OUT
6. Charge Injection
REV. B
–9–
Page 10
ADG511/ADG512/ADG513
Test Circuits (continued)
V
DD
0.1mF
V
DD
SD
V
S
IN
V
IN
V
GND
0.1mF
SS
V
SS
R
L
50V
V
DD
0.1mF
V
DD
SD
V
OUT
V
S
V
OUT
R
L
50V
V
IN1
SD
V
GND
0.1mF
SS
CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG V
V
SS
50V
V
IN2
NC
S/VOUT
7. Off Isolation
8. Channel-to-Channel Crosstalk
–10–
REV. B
Page 11
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
OUTLINE DIMENSIONS
Dimensions are shown in inches and (mm).
16-Lead Plastic DIP
(N-16)
0.840 (21.34)
0.745 (18.92)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
9
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
16-Lead Cerdip
(Q-16)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
ADG511/ADG512/ADG513
0.195 (4.95)
0.115 (2.93)
C1688b–0–10/99
0.005 (0.13) MIN
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
16
1
PIN 1
0.840 (21.34) MAX
0.023 (0.58)
0.014 (0.36)
16 9
PIN 1
0.0500
(1.27)
BSC
0.080 (2.03) MAX
0.100
0.070 (1.78)
(2.54)
0.030 (0.76)
BSC
16-Lead SOIC
0.3937 (10.00)
0.3859 (9.80)
0.0192 (0.49)
0.0138 (0.35)
9
0.310 (7.87)
0.220 (5.59)
8
0.060 (1.52)
0.015 (0.38)
(R-16A)
0.2440 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.150
(3.81)
MIN
SEATING
PLANE
0.320 (8.13)
0.290 (7.37)
15°
0°
0.0196 (0.50)
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
0.015 (0.38)
0.008 (0.20)
x 458
PRINTED IN U.S.A.
REV. B
–11–
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