Page 1
4/8 Channel Fault-Protected
a
FEATURES
Low On Resistance (300 ⍀ typ)
Fast Switching Times
250 ns max
t
ON
250 ns max
t
OFF
Low Power Dissipation (3.3 mW max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power
Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
New Designs Requiring Multiplexer Functions
GENERAL DESCRIPTION
The ADG508F, ADG509F and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1 and A2. The ADG509F switches one of four differential
inputs to a common differential output as determined by the 2bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
*Patent Pending.
Analog Multiplexers
ADG508F/ADG509F/ADG528F*
FUNCTIONAL BLOCK DIAGRAMS
ADG508F/ADG528F
S1
D
S8
ONLY
WR
RS
1 OF 8
DECODER
A0
A1 A2 EN
ADG528F
2. ON channel turns off while fault exists.
3. Low R
ON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDE
1
Model
Temperature Range Package Option
ADG508FBN –40°C to +85°C N-16
ADG508FBRN –40°C to +85°C R-16N
ADG508FBRW –40°C to +85°C R-16W
ADG508FTQ –55°C to +125°C Q-16
ADG509FBN –40°C to +85°C N-16
ADG509FBRN –40°C to +85°C R-16N
ADG509FBRW –40°C to +85°C R-16W
ADG509FTQ –55°C to +125°C Q-16
ADG528FBN –40°C to +85°C N-18
ADG528FBP –40°C to +85°C P-20A
ADG528FTQ –55°C to +125°C Q-18
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
RN = 0.15" Small Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
S1A
S4A
S1B
S4B
ADG509F
1 OF 4
DECODER
A1
A0
EN
DA
DB
2
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
ADG508F/ADG509F/ADG528F–SPECIFICATIONS
1
Dual Supply
(V
= +15 V ⴞ 10%, V
DD
= –15 V ⴞ 10%, GND = 0 V, unless otherwise noted)
SS
B Version T Version
–40ⴗC to –55ⴗC to
Parameter +25ⴗC +85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
+ 3 VSS + 3 V min
SS
VDD – 1.5 VDD – 1.5 V max
R
ON
300 350 300 400 Ω typ –10 V < V
400 450 Ω max –10 V < V
Drift 0.6 0.6 %/°C typ V
R
ON
V
DD
V
DD
= 0 V, IS = 1 mA
S
< +10 V, IS = 1 mA;
S
= +15 V ± 10%, VSS = –15 V ± 10%
< +10 V, IS = 1 mA;
S
= +15 V ± 5%, VSS = –15 V ± 5%
RON Match 5 5 % max VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source OFF Leakage I
(OFF) ±0.02 ±0.02 nA typ VD = ±10 V, V
S
= ⫿10 V;
S
±1 ±50 ±1 ±50 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.04 ±0.04 nA typ VD = ±10 V, V
D
= ⫿10 V;
S
ADG508F/ADG528F ±1 ±60 ±1 ±200 nA max Test Circuit 3
ADG509F ±1 ±30 ±1 ±100 nA max
Channel ON Leakage I
(ON) ±0.04 ±0.04 nA typ V
D
S
= V
S
= ±10 V;
D
, I
ADG508F/ADG528F ±1 ±60 ±1 ±200 nA max Test Circuit 4
ADG509F ±1 ±30 ±1 ±100 nA max
FAULT
Output Leakage Current ±0.02 ±0.02 nA typ V
= ±33 V, V
S
= 0 V, Test Circuit 3
D
(With Overvoltage) ±2 ±2 ±2 µA max
Input Leakage Current ±0.005 ±0.005 µA typ V
= ±25 V, V
S
= ⫿10 V, Test Circuit 5
D
(With Overvoltage) ±2 ±2 µA max
Input Leakage Current ±0.001 ±0.001 µA typ V
= ±25 V, V
S
= VEN = A0, A1, A2 = 0 V
D
(With Power Supplies OFF) ±2 ±2 µA max Test Circuit 6
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 2.4 V min
0.8 0.8 V max
Input Current
I
INL
or I
INH
±1 ±1 µA max V
= 0 or V
IN
DD
CIN, Digital Input Capacitance 5 5 pF typ
DYNAMIC CHARACTERISTICS
t
TRANSITION
t
OPEN
t
(EN, WR) 200 200 ns typ R
ON
(EN, RS) 200 200 ns typ R
t
OFF
2
200 200 ns typ R
300 400 300 400 ns max V
50 50 ns typ R
25 10 25 10 ns min V
250 400 250 400 ns max V
= 1 MΩ, C
L
= ±10 V, V
S1
= 1 kΩ, C
L
= +5 V; Test Circuit 8
S
= 1 kΩ, C
L
= +5 V; Test Circuit 9
S
= 1 kΩ, C
L
= 35 pF;
L
= ⫿10 V; Test Circuit 7
S8
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
250 400 250 400 ns max VS = +5 V; Test Circuit 9
, Settling Time
t
SETT
0.1% 1 1 µs typ R
0.01% 2.5 2.5 µs typ V
= 1 kΩ, C
L
= +5 V
S
= 35 pF;
L
ADG528F Only
, Write Pulsewidth 100 120 100 200 ns min
t
W
tS, Address, Enable Setup Time 100 100 ns min
, Address, Enable Hold Time 10 10 ns min
t
H
, Reset Pulsewidth 100 100 ns min
t
RS
Charge Injection 4 4 pC typ VS =0V,R
OFF Isolation 68 68 dB typ R
50 50 dB min V
= 1 kΩ, C
L
= 7 V rms; Test Circuit 13
S
=0Ω,C
S
L
= 1 nF; Test Circuit 12
L
= 15 pF, f = 100 kHz;
CS (OFF) 5 5 pF typ
(OFF)
C
D
ADG508F/ADG528F 50 50 pF typ
ADG509F 25 25 pF typ
POWER REQUIREMENTS
I
DD
I
SS
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
0.1 0.2 0.1 0.2 mA max VIN = 0 V or 5 V
0.1 0.1 0.1 0.1 mA max
REV. C–2–
Page 3
ADG508F/ADG509F/ADG528F
Table I. ADG508F Truth Table
A2 A1 A0 EN ON SWITCH
X X X 0 NONE
00011
00112
01013
01114
10015
10116
11017
11118
X = Don’t Care
Table III. ADG528F Truth Table
A2 A1 A0 EN WR RS SWITCH
X XXXg 1 Retains Previous Switch Condition
X XXXX0 NONE (Address and Enable Latches Cleared)
X X X 0 0 1 NONE
0 001011
0 011012
0 101013
0 111014
1 001015
1 011016
1 101017
1 111018
X = Don’t Care
Table II. ADG509F Truth Table
A1 A0 EN ON SWITCH PAIR
X X 0 NONE
0011
0112
1013
1114
X = Don’t Care
ON
TIMING DIAGRAMS (ADG528F)
3V
WR
A0, A1, A2
EN
50%
0V
3V
0V
t
W
2V
50%
t
S
t
0.8V
H
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
3V
RS
SWITCH
OUTPUT
0V
V
O
0V
50%
50%
t
RS
t
(RS)
OFF
0.8V
O
Figure 2.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, t
OFF
(RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
= tF = 20 ns.
R
REV. C
–3–
Page 4
ADG508F/ADG509F/ADG528F
WR
A0
RS
A1
S1
S2
S3
S5
S6
EN
V
SS
A2
S4 S7
D
S8
V
DD
GND
1
2
18
17
5
6
7
14
13
12
3
4
16
15
811
910
TOP VIEW
(Not to Scale)
ADG528F
EN
V
SS
S3
S1
S2
A0
WR
A1
NC
RS
1931220
4
5
8
6
7
12 1391110
18
17
14
16
15
TOP VIEW
(Not to Scale)
ADG528F
A2
GND
S6
V
DD
S5
S4
D
S7
S8
NC
NC = NO CONNECT
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(T
= +25°C unless otherwise noted)
A
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
SS
, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,
V
EN
Whichever Occurs First
V
, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V
S
V
, Analog Input Overvoltage with Power OFF
S
to V
+ 40 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package
, Thermal Impedance
θ
JA
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package
, Thermal Impedance
θ
JA
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117°C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package
, Thermal Impedance
θ
JA
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC DIP/SOIC
1
A0
2
EN
3
V
SS
ADG508F
4
S1
TOP VIEW
5
S2
(Not to Scale)
6
S3
7
S4
DS8
89
16
A1
15
A2
14
GND
13
V
DD
12
S5
11
S6
10
S7
1
A0
2
EN
3
V
SS
ADG509F
S1A
4
TOP VIEW
5
S2A
(Not to Scale)
6
S3A
7
S4A
89
DA DB
16
15
14
13
12
11
10
ADG528F PIN CONFIGURATIONS
DIP PLCC
A1
GND
V
DD
S1B
S2B
S3B
S4B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. C
Page 5
ADG508F/ADG509F/ADG528F
2000
1000
0
–15 –5 155010–10
500
1750
1500
1250
750
250
V
D
(VS) – Volts
R
ON
– V
TA = +258C
VDD = +5V
V
SS
= –5V
VDD = +10V
V
SS
= –10V
VDD = +15V
V
SS
= –15V
1m
1m
1p
–50 –30 5010–20 20
–40
1n
30 40
100m
10m
10n
100n
10p
100p
–10 0
V
IN
– INPUT VOLTAGE – Volts
I
D
– INPUT LEAKAGE – A
VDD = +15V
V
SS
= –15V
V
D
= 0V
60
OPERATING RANGE
TERMINOLOGY
V
DD
V
SS
GND Ground (0 V) reference.
R
ON
R
Drift Change in RON when temperature changes
ON
R
Match Difference between the RON of any two
ON
I
(OFF) Source leakage current when the switch is
S
I
(OFF) Drain leakage current when the switch is off.
D
I
, IS (ON) Channel leakage current when the switch is
D
V
(VS) Analog voltage on terminals D, S.
D
C
(OFF) Channel input capacitance for “OFF”
S
C
(OFF) Channel output capacitance for “OFF”
D
C
, CS (ON) “ON” switch capacitance.
D
C
IN
t
(EN) Delay time between the 50% and 90% points
ON
t
(EN) Delay time between the 50% and 90% points
OFF
t
TRANSITION
t
OPEN
V
INL
V
INH
I
(I
INL
) Input current of the digital input.
INH
Off Isolation A measure of unwanted signal coupling
Charge Injection A measure of the glitch impulse transferred
I
DD
I
SS
REV. C
Most positive power supply potential.
Most negative power supply potential.
Ohmic resistance between D and S.
by one degree Celsius.
channels.
off.
on.
condition.
condition.
Digital input capacitance.
of the digital input and switch “ON”
condition.
of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Maximum input voltage for Logic “0”.
Minimum input voltage for Logic “1”.
through an “OFF” channel.
from the digital input to the analog output
during switching.
Positive supply current.
Negative supply current.
Typical Performance Graphs
Figure 3. On Resistance as a Function of VD (VS)
1m
100m
10m
1m
100n
10n
1n
– INPUT LEAKAGE – A
S
I
100p
10p
1p
–40
–50 –30 5010–20 20
OPERATING RANGE
–10 0
V
– INPUT VOLTAGE – Volts
IN
Figure 4. Input Leakage Current as a Function of V
(Power Supplies OFF) During Overvoltage Conditions
Figure 5. Output Leakage Current as a Function of V
(Power Supplies ON) During Overvoltage Conditions
–5–
VDD = 0V
= 0V
V
SS
= 0V
V
D
30 40
60
S
S
Page 6
ADG508F/ADG509F/ADG528F
2000
1750
1500
1250
– V
1000
ON
R
750
500
250
0
–15 –5 155010–10
+85 C
V
D
(VS) – Volts
+125 C
VDD = +15V
V
= –15V
SS
+25 C
Figure 6. On Resistance as a Function of VD (VS) for
Different Temperatures
1m
100m
10m
1m
100n
10n
1n
– INPUT LEAKAGE – A
S
I
100p
10p
1p
–40
–50 –30 5010–20 20
OPERATING RANGE
–10 0
– INPUT VOLTAGE – Volts
V
IN
VDD = +15V
= –15V
V
SS
= 0V
V
D
30 40
60
Figure 7. Input Leakage Current as a Function of V
(Power Supplies ON) During Overvoltage Conditions
100
VDD = +15V
= –15V
V
10
1
0.1
LEAKAGE CURRENTS – nA
0.01
25 45 1256555 7535
V
V
SS
= +10V
D
= –10V
S
ID (OFF)
TEMPERATURE – 8C
85 95 105
IS (OFF)
ID (ON)
115
Figure 9. Leakage Currents as a Function of Temperature
260
t
OFF
VIN = +2V
(EN)
14
240
220
t
(EN)
200
180
ON
t – ns
160
140
120
100
10 1512 1311
S
Figure 10. Switching Time vs. Power Supply
t
TRANSITION
V
SUPPLY
– Volts
0.3
VDD = +15V
V
= –15V
0.2
0.1
0.0
LEAKAGE CURRENTS – nA
–0.1
–0.2
SS
T
A
–14 –6 142–2 6–10
= +258C
IS (OFF)
VS, VD – Volts
ID (OFF)
ID (ON)
10
Figure 8. Leakage Currents as a Function of VD (VS)
–6–
280
VDD = +15V
260
V
= –15V
SS
V
240
220
200
– ns
t
180
160
140
120
100
25 12565 8545
IN
= +5V
TEMPERATURE – 8C
t
ON
t
TRANSITION
(EN)
t
OFF
(EN)
105
Figure 11. Switching Time vs. Temperature
REV. C
Page 7
ADG508F/ADG509F/ADG528F
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable
of withstanding overvoltages from –40 V to +55 V, irrespective
of whether the power supplies are present or not. Each channel
of the multiplexer consists of an n-channel MOSFET, a pchannel MOSFET and an n-channel MOSFET, connected in
series. When the analog input exceeds the power supplies, one
of the MOSFETs will switch off, limiting the current to submicroamp levels, thereby preventing the overvoltage from damaging any circuitry following the multiplexer. Figure 12 illustrates
the channel architecture that enables these multiplexers to withstand continuous overvoltages.
When an analog input of V
+ 3 V to VDD – 1.5 V is applied to
SS
the ADG508F/ADG509F/ADG528F, the multiplexer behaves
as a standard multiplexer, with specifications similar to a stan-
dard multiplexer, for example, the on-resistance is 400 Ω maxi-
mum. However, when an overvoltage is applied to the device,
one of the three MOSFETs will turn off.
Figures 12 to 15 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input applied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between VDD and the
OVERVOLTAGE
+55V
n-CHANNEL
MOSFET IS
OFF
Q1 Q2 Q3
V
DD
V
SS
Figure 12. +55 V Overvoltage Input to the ON Channel
n-channel threshold voltage (VTN). When a voltage more negative than V
is applied to the multiplexer, the p-channel
SS
MOSFET will turn off since the analog input is more negative
than the difference between V
voltage (V
). Since VTN is nominally 1.5 V and VTP is typically
TP
and the p-channel threshold
SS
3 V, the analog input range to the multiplexer is limited to
–12 V to +13.5 V when a ±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the
series will remain off since the gate to source voltage applied to
this MOSFET is negative.
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from over
stresses as well as protecting the signal sources which drive the
multiplexer. Also, the other channels of the multiplexer will be
undisturbed by the overvoltage and will continue to operate
normally.
OVERVOLTAGE
+55V
n-CHANNEL
MOSFET IS
OFF
Q1 Q2 Q3
Figure 14. +55 V Overvoltage with Power OFF
OVERVOLTAGE
–40V
n-CHANNEL
MOSFET IS
ON
Q1 Q2 Q3
V
SS
V
DD
p-CHANNEL
MOSFET IS
OFF
Figure 13. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
OVERVOLTAGE
–40V
n-CHANNEL
MOSFET IS
ON
Q1 Q2 Q3
p-CHANNEL
MOSFET IS
OFF
Figure 15. –40 V Overvoltage with Power OFF
REV. C
–7–
Page 8
ADG508F/ADG509F/ADG528F
Test Circuits
I
DS
V1
S
V
S
R
= V1/I
ON
Test Circuit 1. On Resistance
V
DD
V
I
(OFF)
S
A
V
S
V
D
DD
S1
S2
S8
Test Circuit 2. IS (OFF)
V
V
S1
S2
S8
D
DS
V
SS
V
SS
D
EN
+0.8V
V
S
Test Circuit 4. ID (ON)
S1
A
S2
S8
V
S
V
DD
DD
SS
V
SS
EN
V
DD
V
V
DD
I
(ON)
D
D
A
V
D
+2.4V
V
SS
SS
D
V
EN
+0.8V
D
Test Circuit 5. Input Leakage Current
(with Overvoltage)
0V
0V
V
V
V
DD
SS
V
V
S1
S2
S8
V
S
SS
DD
I
(OFF)
D
D
A
V
EN
+0.8V
D
Test Circuit 3. ID (OFF)
V
V
V
A2
V
IN
50V
+2.4V
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
DD
DD
ADG528F
SS
V
SS
S2–S7
*
WR
ADDRESS
V
S1
S8
S1
V
S8
D
R
L
1MV
C
L
35pF
V
DRIVE (V
OUT
V
0V
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
3V
)
IN
OUT
A2
A1
A0
EN
RS
GND
50%
t
TRANSITION
V
DD
ADG528F
90%
WR
SS
A
S1
V
S
*
S8
D
50%
90%
t
TRANSITION
Test Circuit 7. Switching Time of Multiplexer, t
–8–
TRANSITION
REV. C
Page 9
ADG508F/ADG509F/ADG528F
DD
V
DD
ADG528F
V
SS
V
SS
S2–S7
*
WR
DRIVE (V
OUT
R
1kV
V
S
V
C
L
L
35pF
S1
S8
D
ADDRESS
IN
V
OUT
3V
Test Circuit 8. Break-Before-Make Delay, t
V
SS
V
SS
S2–S8
*
WR
S1
V
S
D
R
L
1kV
C
L
35pF
V
DRIVE (V
OUT
ENABLE
OUTPUT
3V
)
IN
0V
V
O
0V
)
ON
t
OPEN
O
(EN)
80%
50%
0.9V
t
OFF
O
(EN)
80%
OPEN
50%
0.9V
t
V
A2
A2
A1
A0
RS
EN
A1
A0
RS
EN
V
V
GND
DD
DD
GND
ADG528F
V
IN
50V
+2.4V
* SIMILAR CONNECTION FOR ADG508F/ADG509F
+2.4V
V
50V
IN
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 9. Enable Delay, tON (EN), t
V
V
V
A2
A1
A0
+2.4V
V
RS
EN
RS
WR
V
WR
DD
DD
ADG528F
GND
SS
V
SS
S2–S8
3V
WR
V
S1
S
D
R
L
1kV
C
L
35pF
V
OUT
OUTPUT
0V
V
O
0V
OFF
(EN)
50%
t
(WR)
ON
0.2V
O
Test Circuit 10. Write Turn-On Time, tON (WR)
REV. C
–9–
Page 10
ADG508F/ADG509F/ADG528F
V
+2.4V
V
IN
V
V
A2
A1
A0
EN
RS
GND
DD
DD
ADG528F
SS
V
SS
S2–S8
WR
V
S1
D
R
1kV
3V
RS
OFF
(RS)
50%
0.8V
O
S
RS
0V
50%
t
t
V
SWITCH
OUTPUT
O
0V
V
OUT
C
L
L
35pF
Test Circuit 11. Reset Turn-Off Time, t
V
V
V
A2
A1
R
S
V
S
V
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A0
S
EN
IN
GND
DD
DD
ADG528F
V
WR
SS
SS
RS
+2.4V
*
D
+2.4V
3V
LOGIC
C
1nF
INPUT (V
V
OUT
L
)
IN
0V
V
OUT
Test Circuit 12. Charge Injection
V
DD
V
DD
WR
S1
S8
D
V
SS
R
L
1kV
V
OUT
A2
A1
A0
ADG528F*
RS
EN
GND
OFF
(RS)
V
IN
Q
INJ
= CL x DV
OUT
DV
OUT
V
SS
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 13. OFF Isolation
–10–
REV. C
Page 11
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
16-Lead Plastic (N-16)
0.840 (21.34)
0.745 (18.92)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
9
0.070 (1.77)
0.045 (1.15)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
16-Lead SOIC (R-16N)
(Narrow Body)
0.3937 (10.00)
0.3859 (9.80)
PLANE
16 9
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.2440 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.26)
0.300 (7.62)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
x 45°
0.005 (0.13) MIN
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.0118 (0.30)
0.0040 (0.10)
16-Lead Cerdip (Q-16)
16
1
PIN 1
0.840 (21.34) MAX
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
16-Lead SOIC (R-16W)
0.4133 (10.50)
0.3977 (10.00)
16 9
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.080 (2.03) MAX
9
0.310 (7.87)
0.220 (5.59)
8
0.060 (1.52)
0.015 (0.38)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
(Wide Body)
0.2992 (7.60)
0.2914 (7.40)
SEATING
PLANE
0.4193 (10.65)
0.0125 (0.32)
0.0091 (0.23)
81
0.1043 (2.65)
0.0926 (2.35)
0.150
(3.81)
MIN
0.3937 (10.00)
0.320 (8.13)
0.290 (7.37)
15°
0°
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
8°
0°
0.0157 (0.40)
0.015 (0.38)
0.008 (0.20)
x 45°
REV. C
–11–
Page 12
ADG508F/ADG509F/ADG528F
)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
18-Lead Plastic (N-18)
0.925 (23.49
0.845 (21.47)
18
19
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
10
0.070 (1.77)
0.045 (1.15)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.048 (1.21)
0.042 (1.07)
3
4
IDENTIFIER
TOP VIEW
(PINS DOWN)
8
9
0.356 (9.04)
0.350 (8.89)
0.395 (10.02)
0.385 (9.78)
0.195 (4.95)
0.115 (2.93)
0.200 (5.08)
0.200 (5.08)
0.125 (3.18)
20-Lead PLCC (P-20A)
0.180 (4.57)
PIN 1
0.056 (1.42)
0.042 (1.07)
19
18
14
13
SQ
SQ
0.050
(1.27)
BSC
0.165 (4.19)
0.110 (2.79)
0.085 (2.16)
0.005 (0.13) MIN
18
1
PIN 1
MAX
0.023 (0.58)
0.014 (0.36)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
18-Lead Cerdip (Q-18)
0.098 (2.49) MAX
10
0.310 (7.87)
0.220 (5.59)
9
0.960 (24.38) MAX
0.100
0.070 (1.78)
(2.54)
0.030 (0.76)
BSC
0.330 (8.38)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
SEATING
PLANE
0.150
(3.81)
MIN
0.320 (8.13)
0.290 (7.37)
15°
0°
C1979c–0–8/98
0.015 (0.38)
0.008 (0.20)
PRINTED IN U.S.A.
–12–
REV. C
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