Datasheet ADG508FBRW, ADG508FBRN, ADG528FBP, ADG528FBN, ADG508FBN Datasheet (Analog Devices)
...Page 1
2. ON channel turns off while fault exists.
3. Low R
ON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDE
Model Temperature Range Package Option*
ADG508FBN –40°C to +85°C N-16
ADG508FBRN –40°C to +85°C R-16N
ADG508FBRW –40°C to +85°C R-16W
ADG509FBN –40°C to +85°C N-16
ADG509FBRN –40°C to +85°C R-16N
ADG509FBRW –40°C to +85°C R-16W
ADG528FBN –40°C to +85°C N-18
ADG528FBP –40°C to +85°C P-20A
*N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); RN = 0.15" Small
Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
A0
D
ADG508F/ADG528F
A1 A2 EN
1 OF 8
DECODER
ADG528F
ONLY
WR
RS
S1A
A0
DA
ADG509F
A1
S4A
S1B
S4B
DB
EN
1 OF 4
DECODER
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG508F/ADG509F/ADG528F*
4/8 Channel Fault-Protected
Analog Multiplexers
*Patent Pending.
GENERAL DESCRIPTION
The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differential inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
FEATURES
Low On Resistance (300 ⍀ Typ)
Fast Switching Times
t
ON
250 ns Max
t
OFF
250 ns Max
Low Power Dissipation (3.3 mW Max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped within Power
Supplies if an Overvoltage Occurs
Latch-Up Proof Construction
Break before Make Construction
TTL and CMOS Compatible Inputs
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
New Designs Requiring Multiplexer Functions
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Page 2
REV. D–2–
(V
DD
= +15 V ⴞ 10%, V
SS
= –15 V ⴞ 10%, GND = 0 V, unless otherwise noted)
Dual Supply
B Version
–40ⴗC to
Parameter +25ⴗC +85ⴗC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
+ 3 V min
VDD – 1.5 V max
R
ON
300 350 Ω typ –10 V < VS < +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = –15 V ± 10%
400 Ω max –10 V < VS < +10 V, IS = 1 mA;
V
DD
= +15 V ± 5%, VSS = –15 V ± 5%
R
ON
Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA
RON Match 5 % max VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF) ± 0.02 nA typ VD = ± 10 V, VS = ⫿10 V;
± 1 ± 50 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ± 0.04 nA typ VD = ± 10 V, VS = ⫿10 V;
ADG508F/ADG528F ± 1 ± 60 nA max Test Circuit 3
ADG509F ± 1 ± 30 nA max
Channel ON Leakage I
D
, IS (ON) ± 0.04 nA typ VS = VD = ± 10 V;
ADG508F/ADG528F ± 1 ± 60 nA max Test Circuit 4
ADG509F ± 1 ± 30 nA max
FAULT
Output Leakage Current ± 0.02 nA typ VS = ± 33 V, VD = 0 V, Test Circuit 3
(With Overvoltage) ± 2 ± 2 µA max
Input Leakage Current ± 0.005 µA typ V
S
= ± 25 V, VD = ⫿10 V, Test Circuit 5
(With Overvoltage) ± 2 µA max
Input Leakage Current ± 0.001 µA typ VS = ± 25 V, VD = VEN = A0, A1, A2 = 0 V
(With Power Supplies OFF) ± 2 µA max Test Circuit 6
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
± 1 µA max VIN = 0 or V
DD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
200 ns typ RL = 1 MΩ, CL = 35 pF;
300 400 ns max VS1 = ± 10 V, VS8 = ⫿10 V; Test Circuit 7
t
OPEN
50 ns typ RL = 1 kΩ, CL = 35 pF;
25 10 ns min VS = 5 V; Test Circuit 8
t
ON
(EN, WR) 200 ns typ RL = 1 kΩ, CL = 35 pF;
250 400 ns max V
S
= 5 V; Test Circuit 9
t
OFF
(EN, RS) 200 ns typ RL = 1 kΩ, CL = 35 pF;
250 400 ns max VS = 5 V; Test Circuit 9
t
SETT
, Settling Time
0.1% 1 µs typ RL = 1 kΩ, CL = 35 pF;
0.01% 2.5 µs typ VS = 5 V
ADG528F Only
t
W
, Write Pulsewidth 100 120 ns min
tS, Address, Enable Setup Time 100 ns min
t
H
, Address, Enable Hold Time 10 ns min
tRS, Reset Pulsewidth 100 ns min
Charge Injection 4 pC typ VS =0V,RS=0Ω,CL= 1 nF; Test Circuit 12
OFF Isolation 68 dB typ R
L
= 1 kΩ, CL = 15 pF, f = 100 kHz;
50 dB min VS = 7 V rms; Test Circuit 13
CS (OFF) 5 pF typ
C
D
(OFF)
ADG508F/ADG528F 50 pF typ
ADG509F 25 pF typ
POWER REQUIREMENTS
I
DD
0.1 0.2 mA max VIN = 0 V or 5 V
I
SS
0.1 0.1 mA max
NOTES
1
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG508F/ADG509F/ADG528F–SPECIFICATIONS
Page 3
ADG508F/ADG509F/ADG528F
REV. D
–3–
Table I. ADG508F Truth Table
A2 A1 A0 EN ON Switch
X X X 0 NONE
00011
00112
01013
01114
10015
10116
11017
11118
X = Don’t Care
Table II. ADG509F Truth Table
A1 A0 EN ON Switch Pair
X X 0 NONE
0011
0112
1013
1114
X = Don’t Care
Table III. ADG528F Truth Table
A2 A1 A0 EN WR RS ON Switch
X XXXg 1 Retains Previous Switch Condition
X XXXX0NONE (Address and Enable Latches Cleared)
X X X 0 0 1 NONE
0 001011
0 011012
0 101013
0 111014
1 001015
1 011016
1 101017
1 111018
X = Don’t Care
TIMING DIAGRAMS (ADG528F)
t
W
50%
50%
t
S
t
H
0.8V
2V
3V
WR
0V
3V
0V
A0, A1, A2
EN
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
t
RS
50%
50%
0.8V
O
3V
RS
0V
V
O
SWITCH
OUTPUT
t
OFF
(RS)
0V
Figure 2.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, t
OFF
(RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
R
= tF = 20 ns.
Page 4
REV. D
–4–
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
V
EN
, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,
Whichever Occurs First
VS, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V
to V
DD
+ 40 V
V
S
, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic Package
θ
JA
, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117°C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package
θ
JA
, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
PLCC Package
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC DIP/SOIC
A0
EN
A1
A2
S2
S3
S4
S5
S6
S7
S1
GND
V
DD
DS8
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
ADG508F
V
SS
A0
EN
A1
GND
S2A
S3A
S4A
S2B
S3B
S4B
V
SS
S1A
V
DD
S1B
DA DB
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
ADG509F
ADG528F PIN CONFIGURATIONS
DIP PLCC
WR
A0
RS
A1
S1
S2
S3
S5
S6
EN
V
SS
A2
S4 S7
D
S8
V
DD
GND
1
2
18
17
5
6
7
14
13
12
3
4
16
15
811
910
TOP VIEW
(Not to Scale)
ADG528F
EN
V
SS
S3
S1
S2
A0
WR
A1
NC
RS
1931220
4
5
8
6
7
12 1391110
18
17
14
16
15
TOP VIEW
(Not to Scale)
ADG528F
A2
GND
S6
V
DD
S5
S4
D
S7
S8
NC
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG508F/ADG509F/ADG528F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Page 5
ADG508F/ADG509F/ADG528F
REV. D
–5–
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
V
SS
Most Negative Power Supply Potential.
GND Ground (0 V) Reference.
R
ON
Ohmic Resistance between D and S.
R
ON
Drift Change in RON when temperature changes
by one degree Celsius.
R
ON
Match Difference between the RON of any two channels.
I
S
(OFF) Source leakage current when the switch is off.
I
D
(OFF) Drain leakage current when the switch is off.
I
D
, IS (ON) Channel leakage current when the switch is on.
V
D
(VS) Analog Voltage on Terminals D, S.
C
S
(OFF) Channel input capacitance for “OFF” condition.
C
D
(OFF) Channel output capacitance for “OFF” condition.
C
D
, CS (ON) “ON” Switch Capacitance.
C
IN
Digital Input Capacitance.
t
ON
(EN) Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
t
OFF
(EN) Delay time between the 50% and 90% points of
the digital input and switch “OFF” condition.
t
TRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
t
OPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for Logic “0”.
V
INH
Minimum input voltage for Logic “1”.
I
INL
(I
INH
) Input current of the digital input.
Off Isolation A measure of unwanted signal coupling
through an “OFF” channel.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
I
DD
Positive Supply Current.
I
SS
Negative Supply Current.
Typical Performance Characteristics
2000
1000
0
–15 –5 155010–10
500
1750
1500
1250
750
250
V
(V
) – V
R
ON
– ⍀
TA = 25ⴗC
VDD = +5V
V
SS
= –5V
VDD = +10V
V
SS
= –10V
VDD = +15V
V
SS
= –15V
TPC 1. On Resistance as a Function of VD (VS)
1m
1
1p
–50 –30 5010–20 20
–40
1n
30 40
100
10
10n
100n
10p
100p
–10 0
V
IN
– INPUT VOLTAGE – V
I
S
– INPUT LEAKAGE – A
VDD = 0V
V
SS
= 0V
V
D
= 0V
60
OPERATING RANGE
TPC 2. Input Leakage Current as a Function of V
S
(Power Supplies OFF) During Overvoltage Conditions
1m
1
1p
–50 –30 5010–20 20
–40
1n
30 40
100
10
10n
100n
10p
100p
–10 0
V
IN
– INPUT VOLTAGE – V
I
D
– INPUT LEAKAGE – A
VDD = +15V
V
SS
= –15V
V
D
= 0V
60
OPERATING RANGE
TPC 3. Output Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
Page 6
REV. D
–6–
ADG508F/ADG509F/ADG528F
2000
1000
0
–15 –5155010–10
500
1750
1500
1250
750
250
V
D
(V
S
)
– V
R
ON
– ⍀
25 C
VDD = +15V
V
SS
= –15V
125 C
85 C
TPC 4. On Resistance as a Function of VD (VS) for
Different Temperatures
1m
1
1p
–50 –30 5010–20 20
–40
1n
30 40
100
10
10n
100n
10p
100p
–10 0
V
IN
– INPUT VOLTAGE – V
I
S
– INPUT LEAKAGE – A
VDD = +15V
V
SS
= –15V
V
D
= 0V
60
OPERATING RANGE
TPC 5. Input Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
0.3
0.2
–0.2
–14 –6142–26–10
0.1
10
0.0
–0.1
VS, VD – V
LEAKAGE CURRENTS – nA
IS (OFF)
ID (OFF)
ID (ON)
VDD = +15V
VSS = –15V
T
A
= 25ⴗC
TPC 6. Leakage Currents as a Function of VD (VS)
100
10
0.01
25 45 1256555 7535
1
115
0.1
TEMPERATURE – ⴗC
LEAKAGE CURRENTS – nA
IS (OFF)
ID (OFF)
ID (ON)
VDD = +15V
V
SS
= –15V
V
D
= +10V
V
S
= –10V
85 95 105
TPC 7. Leakage Currents as a Function of Temperature
260
240
100
10 1512 1311
120
14
t
ON
(EN)
VIN = 2V
220
200
180
160
140
t – ns
V
– V
t
OFF
(EN)
t
TRANSITION
TPC 8. Switching Time vs. Power Supply
280
240
100
25 12565 8545
120
105
t
ON
(EN)
220
200
180
160
140
t
– ns
TEMPERATURE – ⴗC
t
OFF
(EN)
t
TRANSITION
260
VDD = +15V
V
SS
= –15V
V
IN
= +5V
TPC 9. Switching Time vs. Temperature
Page 7
ADG508F/ADG509F/ADG528F
REV. D
–7–
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable
of withstanding overvoltages from –40 V to +55 V, irrespective
of whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET, and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to submicroamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 3 illustrates the channel
architecture that enables these multiplexers to withstand
continuous overvoltages.
When an analog input of V
SS
+ 3 V to VDD – 1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves
as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 400 Ω
maximum. However, when an overvoltage is applied to the
device, one of the three MOSFETs will turn off.
Figures 3 to 6 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input applied
to an ON channel approaches the positive power supply line, the
n-channel MOSFET turns OFF since the voltage on the analog
input exceeds the difference between VDD and the n-channel
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
V
DD
V
SS
Figure 3. +55 V Overvoltage Input to the ON Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
V
DD
V
SS
p-CHANNEL
MOSFET IS
OFF
Figure 4. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
threshold voltage (VTN). When a voltage more negative than V
SS
is applied to the multiplexer, the p-channel MOSFET will turn
off since the analog input is more negative than the difference
between V
SS
and the p-channel threshold voltage (VTP). Since
V
TN
is nominally 1.5 V and VTP is typically 3 V, the analog
input range to the multiplexer is limited to –12 V to +13.5 V
when a ±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the
series will remain off since the gate to source voltage applied to
this MOSFET is negative.
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from
over stresses as well as protecting the signal sources which
drive the multiplexer. Also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue
to operate normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
Figure 5. +55 V Overvoltage with Power OFF
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
Figure 6. –40 V Overvoltage with Power OFF
Page 8
REV. D
–8–
ADG508F/ADG509F/ADG528F
Test Circuits
I
DS
S
R
ON
= V1/I
DS
V1
V
S
D
Test Circuit 1. On Resistance
V
S
I
S
(OFF)
V
D
S1
S2
S8
V
SS
V
DD
V
SS
V
DD
0.8V
D
EN
A
Test Circuit 2. IS (OFF)
V
D
S1
S2
S8
V
S
V
SS
V
DD
I
D
(OFF)
V
SS
V
DD
0.8V
D
EN
A
Test Circuit 3. ID (OFF)
I
D
(ON)
V
D
S1
S8
V
S
V
SS
V
DD
V
SS
V
DD
2.4V
D
EN
A
S2
Test Circuit 4. ID (ON)
V
D
S1
S2
S8
V
S
V
SS
V
DD
V
SS
V
DD
0.8V
D
EN
A
Test Circuit 5. Input Leakage Current
(with Overvoltage)
A2
V
S
0V
0V
V
SS
V
DD
D
0V
A
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
3V
50%
V
OUT
t
TRANSITION
90%
90%
t
TRANSITION
ADDRESS
DRIVE (V
IN
)
50%
A2
V
OUT
V
SS
V
DD
D
V
S1
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
S2–S7
V
IN
2.4V
50⍀
V
S8
R
L
1M⍀
C
L
35pF
V
SS
V
DD
Test Circuit 7. Switching Time of Multiplexer, t
TRANSITION
Page 9
ADG508F/ADG509F/ADG528F
REV. D
–9–
A2
V
OUT
V
SS
V
DD
D
V
S
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
S2–S7
V
IN
2.4V
50⍀
R
L
1k⍀
C
L
35pF
V
SS
V
DD
ADDRESS
DRIVE (V
IN
)
3V
V
OUT
t
OPEN
80%
80%
Test Circuit 8. Break-Before-Make Delay, t
OPEN
2.4V
3V
50%
OUTPUT
0.9V
O
50%
t
ON
(EN)
0.9V
O
0V
V
O
0V
t
OFF
(EN)
ENABLE
DRIVE (V
IN
)
A2
V
OUT
V
SS
V
DD
D
V
S
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
RS
GND
WR
ADG528F
*
S1
S2–S8
V
IN
50⍀
R
L
1k⍀
C
L
35pF
V
SS
V
DD
EN
Test Circuit 9. Enable Delay, tON (EN), t
OFF
(EN)
3V
OUTPUT
WR
0.2V
O
50%
t
ON
(WR)
0V
V
O
0V
A2
V
OUT
V
SS
V
DD
D
V
S
A1
A0
EN
RS
GND
ADG528F
S1
S2–S8
2.4V
R
L
1k⍀
C
L
35pF
V
SS
V
DD
WR
V
WR
V
RS
Test Circuit 10. Write Turn-On Time, tON (WR)
Page 10
REV. D
–10–
ADG508F/ADG509F/ADG528F
3V
50%
RS
SWITCH
OUTPUT
0.8V
O
50%
t
RS
t
OFF
(RS)
0V
0V
V
O
A2
V
OUT
V
SS
V
DD
D
V
S
A1
A0
EN
RS
GND
WR
ADG528F
S1
S2–S8
V
IN
2.4V
R
L
1k⍀
C
L
35pF
V
SS
V
DD
Test Circuit 11. Reset Turn-Off Time, t
OFF
(RS)
⌬V
OUT
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= CL x ⌬V
OUT
0V
A2
V
OUT
V
SS
V
DD
D
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
V
IN
2.4V
C
L
1nF
V
SS
V
DD
S
R
S
V
S
Test Circuit 12. Charge Injection
A2
V
OUT
V
SS
V
DD
D
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
2.4V
R
L
1k⍀
V
SS
V
DD
S1
V
IN
S8
Test Circuit 13. OFF Isolation
Page 11
ADG508F/ADG509F/ADG528F
REV. D
–11–
16-Lead Plastic (N-16)
16
18
9
PIN 1
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC (R-16W)
(Wide Body)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16 9
81
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
8ⴗ
0ⴗ
0.0291 (0.74)
0.0098 (0.25)
ⴛ 45ⴗ
0.0500 (1.27)
0.0157 (0.40)
16-Lead SOIC (R-16N)
(Narrow Body)
16
9
8
1
0.1574 (4.00)
0.1497 (3.80)
0.3937 (10.00)
0.3859 (9.80)
0.050 (1.27)
BSC
PIN 1
0.2440 (6.20)
0.2284 (5.80)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
8ⴗ
0ⴗ
0.0196 (0.50)
0.0099 (0.25)
ⴛ 45ⴗ
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
Page 12
REV. D
–12–
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C00035c–0–4/01(D)
PRINTED IN U.S.A.
18-Lead Plastic (N-18)
18
19
10
0.925 (23.49)
0.845 (21.47)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
20-Lead PLCC (P-20A)
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.02)
0.385 (9.78)
SQ
0.356 (9.04)
0.350 (8.89)
SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33)
0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
ADG508F/ADG509F/ADG528F–Revision History
Location Page
Data Sheet changed from REV. C to REV. D.
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MAX RATINGS changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted 16-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Deleted 18-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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