Datasheet ADG467 Datasheet (ANALOG DEVICES)

VDDV

Octal Channel Protectors

FEATURES

Fault and overvoltage protection up to ±40 V

Signal paths open circuit with power off

Signal path resistance of R 44 V supply maximum ratings Low on resistance: 62 Ω typical ±1 nA maximum path current leakage @ +25°C Low R

match (5 Ω maximum)

ON

Low power dissipation 0.8 μW typical Latch-up proof construction

APPLICATIONS

ATE equipment Sensitive measurement equipment Hot insertion rack systems

GENERAL DESCRIPTION

The ADG467 is an octal channel protector. The channel protector is placed in series with the signal path. The channel protector protects sensitive components from voltage transience in the signal path regardless if the power supplies are present or not. For this reason, the channel protectors are ideal for use in applications where correct power sequencing cannot always be guaranteed (for example, hot insertion rack systems) to protect analog inputs. This is described further, and some example circuits are given in the Applications Information section.

Each channel protector has an independent operation and consists of an N-channel MOSFET, a P-channel MOSFET, and an N-channel MOSFET, connected in series. The channel protector behaves just like a series resistor during normal operation, that is, (V

+ 1.5 V) < VIN < (VDD − 1.5 V). When a channel’s analog

SS

input exceeds the power supplies (including V one of the MOSFETs switches off, clamping the output to either V

+ 1.5 V or VDD − 1.5 V. Circuitry and signal source protec-

SS

tion is provided in the event of an overvoltage or power loss. The channel protectors can withstand overvoltage inputs from

−40 V to +40 V. See the Circuit Information section.

The ADG467 can operate off both bipolar and unipolar supplies. The channels are normally on when power is

with power on

ON

and VSS = 0 V),

DD

ADG467

FUNCTIONAL BLOCK DIAGRAM

SS

V

D1

V

D2

V

D3

V

IN

V

DD

D8

IN

ADG467

OUTPUT CLAMPED

AT V

Figure 1.

connected and open circuit when power is disconnected. With power supplies of ±15 V, the on resistance of the ADG467 is 62 Ω typical with a leakage current of ±1 nA maximum. When power is disconnected, the input leakage current is approximately ±0.5 nA typical.

The ADG467 is available in an 18-lead SOIC package and a 20-lead SSOP package.

PRODUCT HIGHLIGHTS

1. Fault Protection.

The ADG467 can withstand continuous voltage inputs from −40 V to +40 V. When a fault occurs due to the power supplies being turned off or due to an overvoltage being applied to the ADG467, the output is clamped. When power is turned off, current is limited to the microampere level.

2. Low Power Dissipation.

3. Low R

4. Trench Isolation Latch-Up Proof Construction.

A dielectric trench separates the p- and n-channel MOSFETs thereby preventing latch-up.

. 62 Ω typical.

ON

DD

V

DD

– 1.5V

S1

S2

S3

S8

V

OUT

V

OUT

08191-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG467

REVISION HISTORY

2/11—Rev. A to Rev. B

Updated Format..................................................................Universal

Deleted ADG466 ................................................................Universal

Changes to Features Section, General Description Section,

Figure 1, and Product Highlights Section ..................................... 1

Changes to Power Requirements, V

Deleted 8-Lead DIP, SOIC, and μSOIC Pin Configuration........ 3

Deleted Figure 12; Renumbered Sequentially .............................. 5

Changes to Figure 4 to Figure 6...................................................... 6

Added Figure 7; Renumbered Sequentially .................................. 6

Changes to Figure 11 to Figure 15.................................................. 7

Parameter, Table 1... 3

DD/VSS

Typical Performance Characteristics..............................................6

Test Circuits........................................................................................8

Circuit Information...........................................................................9

Overvoltage Protection.................................................................9

Trench Isolation.............................................................................. 11

Applications Information.............................................................. 12

Overvoltage and Power Supply Sequencing Protection........ 12

High Voltage Surge Suppression .............................................. 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 15

Added Test Circuits Section and Figure 16 to Figure 20..............8

Changes to Overvoltage Protection Section and Figure 23.........9

Changes to Figure 24...................................................................... 10

Change to Figure 26....................................................................... 11

Changes to Overvoltage and Power Supply Sequencing

Protection Section and Figure 27................................................. 12

Changes to High Voltage Surge Suppression Section and

Figure 28 .......................................................................................... 13

Changes to Outline Dimensions .................................................. 14

Changes to Ordering Guide.......................................................... 15

Rev. B | Page 2 of 16

ADG467

SPECIFICATIONS

DUAL SUPPLY

VDD = +15 V, VSS = −15 V, GND = 0 V, unless otherwise noted.

Table 1.

ADG467 Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments

FAULT PROTECTED CHANNEL

Fault-Free Analog Signal Range V

V

RON 62 80 Ω typ −10 V ≤ VSx ≤ +10 V, ISx = 1 mA

95 Ω max

RON Flatness 6 Ω max −5 V ≤ VSx ≤ +5 V

RON Match between Channels 5 6 Ω max VSx = ±10 V, ISx = 1 mA

LEAKAGE CURRENTS

Channel Output Leakage, I

V

S(ON)

(Without Fault Condition) ±0.04 ±0.2 nA typ

±1 ±5 nA max

Channel Input Leakage, I

V

D(ON)

(with Fault Condition) ±0.2 ±0.4 nA typ VDx = open circuit

±2 ±5 nA max

Channel Input Leakage, I

V

D(OFF)

(with Power Off and Fault) ±0.5 ±2 nA typ VSx = ±35 V

±2 ±10 nA max VDx = open circuit

Channel Input Leakage, I

V

D(OFF)

(with Power Off and Output Short Circuit) ±0.006 ±0.16 μA typ VSx = ±35 V, VDx = 0 V ±0.015 ±0.5 μA max POWER REQUIREMENTS

IDD ±0.05 μA typ ±0.5 ±8 μA max ISS ±0.05 μA typ ±0.5 ±8 μA max VDD/VSS ±4.5/±20 V min/max

+ 1.5 V typ Output open circuit

SS

− 1.5 V typ

DD

+ 1.7 V typ Output loaded, 1 mA

SS

− 1.7 V typ

DD

= VDx = ±10 V

Sx

= ±25 V

Sx

= 0 V, VSS = 0 V

DD

= 0 V, VSS = 0 V

DD

Rev. B | Page 3 of 16

ADG467

ABSOLUTE MAXIMUM RATINGS

TA = +25°C, unless otherwise noted.

Table 2.

Parameter Rating

V

to VSS +44 V

DD

VSx, VDx, Analog Input Overvoltage with

Power On

VSx, VDx, Analog Input Overvoltage with

Power Off Continuous Current, VSx, VDx 20 mA Peak Current, VSx, VDx (Pulsed at 1 ms,

10% Duty Cycle Maximum) Operating Temperature Range

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Junction Temperature +150°C SOIC Package

θJA, Thermal Impedance 160°C/W

Lead Temperature, Soldering

SSOP Package

θJA, Thermal Impedance 130°C/W

Lead Temperature, Soldering

1

Overvoltages at VSx or VDx are clamped by the channel protector; see the

Circuit Information section.

1

Vapor Phase (60 sec) +215°C Infrared (15 sec) +220°C

VSS − 20 V to VDD + 20 V

−40 V to +40 V

40 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 4 of 16

ADG467

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

V

D1

V

2

D2

V

3

D3

ADG467

4

V

D4

TOP VIEW

V

5

D5

(Not to Scale)

V

6

D6

7

V

D7

V

8

D8

9

SS

Figure 2. 18-Lead SOIC Pin Configuration

18

V

DD

V

17

S1

V

16

S2

15

V

S3

V

14

S4

V

13

S5

12

V

S6

V

11

S7

V

10

S8

8191-002

Figure 3. 20-Lead SSOP Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

SOIC SSOP Mnemonic Description

1 1 VD1 Drain Terminal 1. This pin can be an input or an output. 2 2 VD2 Drain Terminal 2. This pin can be an input or an output. 3 3 VD3 Drain Terminal 3. This pin can be an input or an output. 4 4 VD4 Drain Terminal 4. This pin can be an input or an output. 5 5 VD5 Drain Terminal 5. This pin can be an input or an output. 6 6 VD6 Drain Terminal 6. This pin can be an input or an output. 7 7 VD7 Drain Terminal 7. This pin can be an input or an output. 8 8 VD8 Drain Terminal 8. This pin can be an input or an output. 9 9 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to

ground. N/A 10 NC No Connect. 10 11 VS8 Source Terminal 1. This pin can be an input or an output. 11 12 VS7 Source Terminal 2. This pin can be an input or an output. 12 13 VS6 Source Terminal 3. This pin can be an input or an output. 13 14 VS5 Source Terminal 4. This pin can be an input or an output. 14 15 VS4 Source Terminal 5. This pin can be an input or an output. 15 16 VS3 Source Terminal 6. This pin can be an input or an output. 16 17 VS2 Source Terminal 7. This pin can be an input or an output. 17 18 VS1 Source Terminal 8. This pin can be an input or an output. 18 19 VDD Most Positive Power Supply Potential. N/A 20 NC No Connect. Do not connect to this pin.

1

D1

V

2

D2

V

3

D3

V

4

D4

V

5

D5

V

6

D6

7

V

D7

V

8

D8

V

9

SS

NC

10

NC = NO CONNECT

ADG467

TOP VIEW

(Not to Scale)

20

NC

19

V

DD

18

V

S1

17

V

S2

16

V

S3

V

15

S4

V

14

S5

V

13

S6

12

V

S7

11

V

S8

08191-003

Rev. B | Page 5 of 16

ADG467

–10V

–15V

TYPICAL PERFORMANCE CHARACTERISTICS

100

VDD, VSS = ±16.5V

, VSS = ±15V

V

90

80

70

DD

, VSS = ±13.5V

V

DD

, VSS = ±20V

V

DD

120

110

100

VDD = 20V

= 13.2V

V

DD

= 12V

V

DD

= 10.8V

V

90

DD

60

ON RESISTANCE ()

50

40

TA = 25°C

30

–17–19 –15 –13 –11 –7–9 –5 –3 –1 1 5 9 13 173 7 11 15 19

Figure 4. On Resistance as a Function of V

INPUT VOLTAGE (V)

DD

and VSx (Input Voltage),

Dual Supply

80

VDD = +15V

75

V

= –15V

SS

70

65

60

55

50

ON RESISTANCE ()

45

40

35

30

–10 –8 –6 –4 –2 0 2 4 6 8 10

+85°C +25°C –40°C +105°C

INPUT VOLTAGE (V)

Figure 5. On Resistance as a Function of Temperature and V

(Input Voltage)

Sx

80

ON RESISTANCE ()

70

60

TA = 25°C

= 0V

V

SS

50

135791113151719

08191-004

Figure 7. On Resistance as a Function of V

INPUT VOLTAGE (V)

DD

and VSx (Input Voltage),

08191-007

Single Supply

POSITIVE OVERVOLTAGE ON INPUT RL = 100k C

= 100pF

L

V

= +10V

DD

V

= –10V

SS

15V

10V

5V

0V

–5V

08191-005

CH1 5.00V CH2 5.00V M 50.0ns A CH1 500mV

–5V TO +15V

STEP INPUT

CHANNEL PROT ECTOR

OUTPUT

08191-008

Figure 8. Positive Overvoltage Transience Response

260 250 240 230 220 210 200 190 180 170 160 150 140

ON RESISTANCE ()

130 120 110 100

90

80

–4 –3 –2 –1 0 1 2 3 4

Figure 6. On Resistance as a Function of V

VDD, VSS = ±5.5V V

, VSS = ±5V

DD

V

, VSS = ±4.5V

DD

INPUT VOLTAG E (V)

DD

and VSx (Input Voltage),

5 V Dual Supply

08191-006

Rev. B | Page 6 of 16

NEGATIVE OVERVOLTAGE ON INPUT

5V

RL = 100k

= 100pF

C

L

0V

= +10V

V

DD

= –10V

V

SS

–5V

CH1 5.00V CH2 5.00V M 50.0ns

CHANNEL PROT ECTOR

OUTPUT

+5V TO –15V

STEP INPUT

Figure 9. Negative Overvoltage Transience Response

A CH1 500mV

08191-009

ADG467

0

VDD = +15V V

= –15V

–10V TO +10V INPUT

1

2

20V

OUTPUT

V

CLAMP

= 4.5V

RL = 100k

= +5V

V

DD

= –5V

V

SS

–20

–40

–60

LOSS (dB)

–80

–100

SS

T

= 25°C

A

INPUT = 0dBm

V

= 4V

CLAMP

CH1 5.00V M 100µsCH2 5.00V A CH1 500mV

Figure 10. Overvoltage Ramp

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

INSERTION LOSS (dB)

–10

VDD = +15V

–11

–12

–13

–14

= –15V

V

SS

= 25°C

T

A

INPUT = 0dBm

100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 11. Frequency Response (Magnitude)

10

0

–10

–20

–30

–40

PHASE (Degrees)

–50

VDD = +15V

–60

V

= –15V

SS

T

= 25°C

A

–70

INPUT = 0dBm

–80

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 12. Frequency Response (Phase)

–120

08191-010

10k1k 100k 1M

FREQUENCY (Hz)

10M 100M

1G

08191-013

Figure 13. Crosstalk Between Adjacent Channels

0

VDD = 0V

–10

V

= 0V

SS

T

= 25°C

A

–20

INPUT = 0dBm

–30

–40

–50

LOSS (dB)

–60

–70

–80

–90

–100

1M 10M 100M 1G

08191-011

FREQUENCY (Hz)

08191-014

Figure 14. Off Isolation

11.8 ns

1

12.2ns

2

08191-012

CH1 2.00V M 10.0nsCH2 2.00V A CH1 2. 2V

08191-015

Figure 15. Propagation Delay

Rev. B | Page 7 of 16

ADG467

V

TEST CIRCUITS

I

DS

V1

SD

V

DD

V

S

RON = V1/I

Figure 16. On Resistance

DS

08191-016

0.1µF

V

SS

0.1µF

V

DD

SS

NETWORK

ANALYZER

SD

NC

NC = NO CONNECT

Figure 17. On Leakage

ID(ON)

DD

0.1µF

NETWORK

ANALYZER

V

OUT

R

L

50

V

S

V

DD

V

S1

V

S2

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

Figure 18. Channel-to-Channel Crosstalk

IN

S

50

D

V

IN

R 50

50

L

V

S

V

OUT

A

V

D

08191-017

OFF ISOLATION = 20 log

OUT

V

08191-019

S

Figure 19. Off Isolation

SS

0.1µF

V

SS

V

R

Dx

L

50

V

OUT

V

S

08191-018

0.1µF

IN

V

IN

V

DD

SS

0.1µF

V

DD

SS

S

D

INSERTION LOSS = 20 log

NETWORK

ANALYZER

50

V

R

L

50

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

OUT

V

S

08191-020

Figure 20. Bandwidth

Rev. B | Page 8 of 16

ADG467

CIRCUIT INFORMATION

Figure 21 shows a simplified schematic of a channel protector circuit. The circuit is made up of four MOS transistors—two NMOS and two PMOS. One of the PMOS devices does not lie directly in the signal path but is used to connect the source of the second PMOS device to its backgate. This has the effect of lowering the threshold voltage and thus increasing the input signal range of the channel for normal operation. The source and backgate of the NMOS devices are connected for the same reason. During normal operation, the channel protectors have an on resistance of 62 Ω typical. The channel protectors are very low power devices, and even under fault conditions, the supply current is limited to sub microampere levels. All transistors are dielectrically isolated from each other using a trench isolation method. This makes it impossible to latch up the channel protectors. For further details, see the Trenc h I s olat i o n section.

V

SS

the output of the channel protector (no load) is clamped at these threshold voltages. However, the channel protector output clamps at a voltage value that is inside these thresholds if the output is loaded. For example, with an output load of 1 kΩ, V

=

DD

15 V, and a positive overvoltage on the input, the output clamps at V

− VTN − ΔV = 15 V − 1.5 V − 0.6 V = 12.9 V, where ΔV is

DD

due to an I × R voltage drop across the channels of the MOS devices (see Figure 23). As can be seen from Figure 23, the current during fault condition is determined by the load on the output (that is, V

CLAMP/RL

). However, if the supplies are off, the fault

current is limited to the nano-ampere level.

Figure 22, Figure 24, and Figure 25 show the operating conditions of the signal path transistors during various fault conditions. Figure 22 shows how the channel protectors operate when a positive overvoltage is applied to the channel protector.

1

– V

V

DD

TN

(+13.5V)

PMOS

NMOS

V

DD

V

PMOS

SS

NMOS

V

DD

08191-021

Figure 21. The Channel Protector Circuit

OVERVOLTAGE PROTECTION

When a fault condition occurs on the input of a channel protector, the voltage on the input has exceeded some threshold voltage set by the supply rail voltages. The threshold voltages are related to the supply rails as follows. For a positive overvoltage, the threshold voltage is given by V voltage of the NMOS transistor (1.5 V typical). In the case of a negative overvoltage, the threshold voltage is given by V where V

is the threshold voltage of the PMOS device (−1.5 V

TP

typical). If the input voltage exceeds these threshold voltages,

OVERVOLTAGE

− VTN, where VTN is the threshold

DD

V

Dx

+

N

EFFECTIVE

OPERATION

(SATURATED)

SPACE CHARGE

= 1.5V

V

T

REGION

Figure 23. Positive Overvoltages Operation of the Channel Protector

V

G

(VDD = 15V) (13.5V)(20V)

N-CHANNEL

–

P

− VTP,

SS

– VTN = 13.5V)

(V

O

V

POSITIVE

OV ERV OLTAG E

(+20V)

SATURATED NON-

1

VTN = NMOS THRESHOLD VOLTAGE (+1.5V).

NMOS PMOS NMOS

SATURATED

(+15V) VSS (–15V) VDD (+15V)

V

DD

NON-

SATURATED

08191-022

Figure 22. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of operation as the voltage on its drain exceeds the gate voltage (V

) − the threshold voltage (VTN). This situation is shown in

DD

Figure 23. The potential at the source of the NMOS device is equal to V

− VTN. The other MOS devices are in a nonsatu-

DD

rated mode of operation.

Sx

+

N

+

P

V

PMOS

NONSATURATED

OPERATION

NMOS

I

OUT

V

CLAMP

R

L

8191-023

Rev. B | Page 9 of 16

ADG467

G

A

When a negative overvoltage is applied to the channel protector circuit, the PMOS transistor enters a saturated mode of operation as the drain voltage exceeds V

− VTP (see Figure 24). As in the

SS

case of the positive overvoltage, the other MOS devices are nonsaturated.

TIVE

NE

OV ERV OLTAG E

(–20V)

NEGATIVE

OV ERV OLTAG E

(–20V)

SATURATED

1

VTP = PMOS THRESHOLD VOLTAGE (–1.5V).

NMOS PMO S NMOS

SATURATEDNON-

V

(+15V) VSS (–15V) VDD (+15V)

DD

– V

V

SS

(–13.5V)

SATURATED

1

TP

NON-

Figure 24. Negative Overvoltage on the Channel Protector

08191-024

The channel protector is also functional when the supply rails are down (for example, power failure) or momentarily unconnected (for example, rack system). This is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see the Applications Information section). When V

and VSS equal 0 V, all transistors are off and

DD

the current is limited to subnano-ampere levels (see Figure 25).

(0V)

POSITIVE OR

NEGATIVE

OV ERV OLTAG E

Figure 25. Channel Protector Supplies Equal to 0 V

NMOS PMO S NMOS

OFF OFF OFF

V

(0V) VSS (0V) VDD (0V)

DD

08191-025

Rev. B | Page 10 of 16

ADG467

V

TRENCH ISOLATION

The MOS devices that make up the channel protector are isolated from each other by an oxide layer (trench) (see Figure 26). When the NMOS and PMOS devices are not electrically isolated from each other, parasitic junctions between CMOS transistors may cause latch-up. Latch-up is caused when P-N junctions that are normally reverse biased become forward biased, causing large currents to flow, which can be destructive.

V

Sx

G

V

Dx

CMOS devices are normally isolated from each other by junction isolation. In junction isolation, the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed; the result is a latch-up-proof circuit.

V

Sx

G

V

Dx

T R

P

E N C

N

H

+

–

P-CHANNEL

BURIED OXIDE L AYER

SUBSTRATE (BACKGATE)

T

+

P

N

R E N C

P

H

+

–

N-CHANNEL

T

+

N

R E N C H

08191-026

Figure 26. Trench Isolation

Rev. B | Page 11 of 16

ADG467

–

APPLICATIONS INFORMATION

OVERVOLTAGE AND POWER SUPPLY SEQUENCING PROTECTION

The ADG467 is ideal for use in applications where input overvoltage protection is required and correct power supply sequencing cannot always be guaranteed. The overvoltage protection ensures that the output voltage of the channel protector does not exceed the threshold voltages set by the supplies (see the Circuit Information section) when there is an overvoltage on the input. When the input voltage does not exceed these threshold voltages, the channel protector behaves like a series resistor (62 Ω typical). The resistance of the channel protector does vary slightly with operating conditions (see the Typical Performance Characteristics section).

The power sequencing protection is provided by the channel protector, which becomes a high resistance device when the supplies to the channel protector are not connected. Under this condition, all transistors in the channel protector are off and the only currents that flow are leakage currents, which are at the microampere level.

EDGE

CONNECTOR

+5V

–5V

Figure 27 shows a typical application that requires overvoltage and power supply sequencing protection. The application shows a hot insertion rack system. This involves plugging a circuit board or module into a live rack via an edge connector. In this type of application, it is not possible to guarantee correct power supply sequencing. Correct power supply sequencing means that the power supplies should be connected before any external signals. Incorrect power sequencing can cause a CMOS device to latch up. This is true of most CMOS devices regardless of the functionality. RC networks are used on the supplies of the channel protector (see Figure 27) to ensure that the rest of the circuitry is powered up before the channel protectors. In this way, the outputs of the channel protectors are clamped well below V and V

until the capacitors are charged. The diodes ensure that

SS

the supplies on the channel protector never exceed the supply rails of the board when it is being disconnected. This ensures that signals on the inputs of the CMOS devices never exceed the supplies.

V

DD

V

SS

DD

ANALOG IN

2.5VTO +2.5V

LOGIC

GND

V

D1

D2

D3

D4

D5

D6

D7

D8

ADG467

V

S1

V

S2

V

S3

V

S4

V

S5

V

S6

V

S7

V

S8

ADC

CONTROL

LOGIC

Figure 27. Overvoltage and Power Supply Sequencing Protection

08191-027

Rev. B | Page 12 of 16

ADG467

V

HIGH VOLTAGE SURGE SUPPRESSION

The ADG467 is not intended for use in high voltage applications like surge suppression. The ADG467 has breakdown voltages in excess of V power supplies are connected. When the power supplies are disconnected, the breakdown voltages on the input of the channel protector are ±40 V. In applications where inputs are likely to be subject to overvoltages exceeding the breakdown voltages specified for the channel protectors, transient voltage suppressors (TVSs) should be used. These devices are commonly used to protect vulnerable circuits from electric overstress such as that caused by electrostatic discharge, inductive load switching, and induced lightning. However, TVSs can have a substantial standby (leakage) current (300 μA typical) at the reverse standoff voltage. The reverse stand-off

− 20 V and VDD + 20 V on the inputs when the

SS

= +5

DD

voltage of a TVS is the normal peak operating voltage of the circuit. Also, a TVS offers no protection against latch-up of sensitive CMOS devices when the power supplies are off. The ideal solution is to use a channel protector in conjunction with a TVS to provide the optimal leakage current specification and circuit protection.

Figure 28 shows an input protection scheme that uses both a TVS and a channel protector. The TVS is selected with a reverse standoff voltage that is much greater than the operating voltage of the circuit (TVSs with higher breakdown voltages tend to have better standby leakage current specifications) but is inside the breakdown voltage of the channel protector. This circuit protects the circuitry regardless of whether the power supplies are present.

= –5

SS

V

D1

V

D2

V

D3

V

D4

V

D5

V

D6

V

D7

V

D8

V

S1

V

S2

V

S3

V

S4

V

S5

V

S6

V

S7

V

S8

ADC

ADG467

TVSs BREAKDOWN VOLTAGE = 20V

08191-028

Figure 28. High Voltage Protection

Rev. B | Page 13 of 16

ADG467

OUTLINE DIMENSIONS

11.75 (0.4626)

11.35 (0.4469)

10

7.60 (0.2992)

7.40 (0.2913)

9

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

5

.

2

5

0

.

0

2

(

0

(

0

.

0

9

5

)

45°

9

8

)

1.27 (0.0500)

0.40 (0.0157)

060706-A

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

18

1

0.51 (0.0201)

1.27

(0.0500)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLI METER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

0.31 (0.0122)

BSC

COMPLIANT TO JEDEC STANDARDS MS-013-AB

Figure 29. 18-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-18)

Dimensions shown in millimeters and (inches)

7.50

7.20

6.90

20

1

11

5.60

5.30

8.20

5.00

7.80

10

7.40

2.00 MAX

0.05 MIN

COPLANARITY

0.10

1.85

1.75

1.65

0.38

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AE

0.22

SEATING PLANE

0.25

0.09

8° 4° 0°

0.95

0.75

0.55

060106-A

Figure 30. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

Rev. B | Page 14 of 16

ADG467

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG467BR −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BR-REEL −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BR-REEL7 −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BRZ −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BRZ-REEL −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BRZ-REEL7 −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18 ADG467BRS −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADG467BRS-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADG467BRSZ −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADG467BRSZ-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20

1

Z = RoHS Compliant Part.

Rev. B | Page 15 of 16

ADG467

NOTES

Rev. B | Page 16 of 16

Datasheet ADG467 Datasheet (ANALOG DEVICES)

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DUAL SUPPLY

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

CIRCUIT INFORMATION

OVERVOLTAGE PROTECTION

TRENCH ISOLATION

APPLICATIONS INFORMATION

OVERVOLTAGE AND POWER SUPPLY SEQUENCING PROTECTION

HIGH VOLTAGE SURGE SUPPRESSION

OUTLINE DIMENSIONS

ORDERING GUIDE