Datasheet ADG453BR, ADG453BN, ADG452BR, ADG452BN, ADG451BR Datasheet (Analog Devices)

LC2MOS

a

FEATURES
Low On Resistance (4 V)
On Resistance Flatness 0.2 V
44 V Supply Maximum Ratings
615 V Analog Signal Range
Fully Specified @ 65 V, +12 V, 615 V
Ultralow Power Dissipation (18 mW)
ESD 2 kV
Continuous Current 100 mA
Fast Switching Times

70 ns

t

O

N

60 ns

t

OFF

TTL/CMOS Compatible
Pin Compatible Upgrade for ADG411/ADG412/ADG413

and ADG431/ADG432/ADG433

APPLICATIONS
Relay Replacement
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
PBX, PABX Systems
Avionics

5 V RON SPST Switches

ADG451/ADG452/ADG453

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

ADG451

IN3

IN4

SWITCHES SHOWN FOR A LOGIC "1" INPUT

S1

D1
S2

D2
S3

D3
S4

D4

IN1

IN2

ADG453

IN3

IN4

IN1

IN2

ADG452

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

S1

D1
S2

D2
S3

D3
S4

D4

GENERAL DESCRIPTION

The ADG451, ADG452 and ADG453 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC

2

MOS process that provides
low power dissipation yet gives high switching speed and low on
resistance.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa­tion making the parts ideally suited for portable and battery
powered instruments.

The ADG451, ADG452 and ADG453 contain four indepen­dent single-pole/single-throw (SPST) switches. The ADG451
and ADG452 differ only in that the digital control logic is in­verted. The ADG451 switches are turned on with a logic low on
the appropriate control input, while a logic high is required for
the ADG452. The ADG453 has two switches with digital con­trol logic similar to that of the ADG451 while the logic is in­verted on the other two switches.

Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The ADG453 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.

PRODUCT HIGHLIGHTS

1. Low RON (5 Ω max)

2. Ultralow Power Dissipation

3. Extended Signal Range
The ADG451, ADG452 and ADG453 are fabricated on an
enhanced LC

2

MOS process giving an increased signal

range that fully extends to the supply rails.

4. Break-Before-Make Switching
This prevents channel shorting when the switches are
configured as a multiplexer. (ADG453 only.)

5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG451, ADG452 and ADG453 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5.0 V.

6. Dual Supply Operation
For applications where the analog signal is bipolar, the
ADG451, ADG452 and ADG453 can be operated from a
dual power supply ranging from ±4.5 V to ±20 V.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADG451/ADG452/ADG453–SPECIFICATIONS

1

Dual Supply

(VDD = +15 V, VSS = –15 V, VL = +5 V, GND = 0 V. All specifications T

MIN

to T

unless otherwise noted.)

MAX

B Version

T

to

Parameter +258CT

MIN
MAX

Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to V
On-Resistance (R

) 4.0 Ω typ VD = –10 V to +10 V, IS = –10 mA

ON

DD

V

57 Ω max

On-Resistance Match Between 0.1 Ω typ V

Channels (∆R

On-Resistance Flatness (R

) 0.5 0.5 Ω max

ON

FLAT(ON)

) 0.2 Ω typ VD = –5 V, 0 V, +5 V, IS = –10 mA

= ±10 V, IS = –10 mA

D

0.5 0.5 Ω max

LEAKAGE CURRENTS

2

Source OFF Leakage IS (OFF) ±0.02 nA typ VD = ±10 V, VS = ±10 V;

±0.5 ±2.5 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.02 nA typ VD = ±10 V, VS = ±10 V;

D

±0.5 ±2.5 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.04 nA typ VD = VS = ±10 V;

D

±1 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

, All Others = 2.4 V

INH

±0.5 µA max or 0.8 V Respectively

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG453 Only) 5 5 ns min V

3

70 ns typ RL = 300 Ω, CL = 35 pF;
180 220 ns max V

= ±10 V; Test Circuit 4

S

60 ns typ RL = 300 Ω, CL = 35 pF;
140 180 ns max V

D

15 ns typ RL = 300 Ω, CL = 35 pF;

= ±10 V; Test Circuit 4

S

= VS2 = +10 V;

S1

Test Circuit 5

Charge Injection 20 pC typ V

= 0 V, RS = 0 Ω, CL = 1.0 nF;

S

30 pC max Test Circuit 6

OFF Isolation 65 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk –90 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

C

(OFF) 15 pF typ f = 1 MHz

S

C

(OFF) 15 pF typ f = 1 MHz

D

CD, CS (ON) 100 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

0.0001 µA typ

0.5 5 µA max

I

SS

0.0001 µA typ

0.5 5 µA max

I

L

I

GND

3

0.0001 µA typ

0.5 5 µA max

0.0001 µA typ

0.5 5 µA max

NOTES

1

Temperature range is as follows: B Version: –40°C to +85° C.

2

T

MAX

3

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

= +70°C

.

–2–

= +16.5 V, VSS = –16.5 V

DD

Digital Inputs = 0 V or 5 V

REV. A

ADG451/ADG452/ADG453

Single Supply

(VDD = +12 V, VSS = 0 V, VL = +5 V, GND = 0 V. All specifications T

MIN

to T

unless otherwise noted.)

MAX

B Version

T

to

Parameter +258CT

MIN
MAX

Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On-Resistance (R

)6 Ω typ VD = 0 V to 10 V, IS = –10 mA

ON

DD

V

810Ω max

On-Resistance Match Between 0.1 Ω typ V

Channels (∆R

On-Resistance Flatness (R

LEAKAGE CURRENTS

) 0.5 0.5 Ω max

ON

FLAT(ON)

2, 3

) 1.0 1.0 Ω typ VD = 0 V, +5 V, IS = –10 mA

= 10 V, IS = –10 mA

D

Source OFF Leakage IS (OFF) ±0.02 nA typ VD = 0 V, 10 V, VS = 0 V, 10 V;

±0.5 ±2.5 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.02 nA typ VD = 0 V, 10 V, VS = 0 V, 10 V;

D

±0.5 ±2.5 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.04 nA typ VD = VS = 0 V, 10 V;

D

±1 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

±0.5 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG453 Only) 10 10 ns min V

4

100 ns typ RL = 300 Ω, CL = 35 pF;
220 260 ns max V

= +8 V; Test Circuit 4

S

80 ns typ RL = 300 Ω, CL = 35 pF;
160 200 ns max V
15 ns typ RL = 300 Ω, CL = 35 pF;

D

= +8 V; Test Circuit 4

S

= VS2 = +8 V;

S1

Test Circuit 5

Charge Injection 10 pC typ V

= 0 V, RS = 0 Ω, CL = 1.0 nF;

S

Test Circuit 6

Channel-to-Channel Crosstalk –90 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

C

(OFF) 15 pF typ f = 1 MHz

S

C

(OFF) 15 pF typ f = 1 MHz

D

CD, CS (ON) 100 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = +13.2 V

Digital Inputs = 0 V or 5 V

I

DD

0.0001 µA typ

0.5 5 µA max

I

L

I

GND

4

0.0001 µA typ

0.5 5 µA max V

0.0001 µA typ

= +5.5 V

L

0.5 5 µA max VL = +5.5 V

NOTES

1

Temperature range is as follows: B Version: –40 °C to +85°C.

2

T

= +70°C.

MAX

3

Tested with dual supplies.

4

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. A

–3–

ADG451/ADG452/ADG453–SPECIFICATIONS

1

Dual Supply

(VDD = +5 V, VSS = –5 V, VL = +5 V, GND = 0 V. All specifications T

MIN

to T

unless otherwise noted.)

MAX

B Version

T

to

Parameter +258CT

MIN
MAX

Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to V
On-Resistance (R

)7 Ω typ VD = –3.5 V to +3.5 V, IS = –10 mA

ON

DD

V

12 15 Ω max

On-Resistance Match Between 0.3 Ω typ V

= 3.5 V, IS = –10 mA

D

Channels (∆RON) 0.5 0.5 Ω max

LEAKAGE CURRENTS

2, 3

Source OFF Leakage IS (OFF) ±0.02 nA typ VD = ±4.5, VS = ±4.5;

±0.5 ±2.5 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.02 nA typ VD = 0 V, 5 V, VS = 0 V, 5 V;

D

±0.5 ±2.5 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.04 nA typ VD = VS = 0 V, 5 V;

D

±1 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

±0.5 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG453 Only) 5 5 ns min V

4

160 ns typ RL = 300 Ω, CL = 35 pF;
220 300 ns max V

= 3 V; Test Circuit 4

S

60 ns typ RL = 300 Ω, CL = 35 pF;
140 180 ns max V
50 ns typ RL = 300 Ω, CL = 35 pF;

D

= 3 V; Test Circuit 4

S

= VS2 = 3 V;

S1

Test Circuit 5

Charge Injection 10 pC typ V

= 0 V, RS = 0 Ω, CL = 1.0 nF;

S

Test Circuit 6

OFF Isolation 65 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk –76 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

C

(OFF) 15 pF typ f = 1 MHz

S

C

(OFF) 15 pF typ f = 1 MHz

D

CD, CS (ON) 100 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = +5.5 V

Digital Inputs = 0 V or 5 V

I

DD

0.0001 µA typ

0.5 5 µA max

I

SS

0.0001 µA typ

0.5 5 µA max

I

L

I

GND

4

0.0001 µA typ

0.5 5 µA max V

0.0001 µA typ

= +5.5 V

L

0.5 5 µA max VL = +5.5 V

NOTES

1

Temperature range is as follows: B Version: –40°C to +85° C.

2

T

= +70°C.

MAX

3

Tested with dual supplies.

4

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–4–

REV. A

ADG451/ADG452/ADG453

WARNING!

ESD SENSITIVE DEVICE

Truth Table (ADG451/ADG452)

ADG451 In ADG452 In Switch Condition

01ON
1 0 OFF

PIN CONFIGURATION

(DIP/SOIC)

1

IN1

2

D1

ADG451

3

S1

ADG452

V

4

SS

ADG453

TOP VIEW

5

GND

(Not to Scale)

6

S4

7

D4

8

IN4

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

16

IN2

15

D2

14

S2
V

13

DD

12

V

L

11

S3

10

D3

9

IN3

1

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V

SS

V

to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

L

Analog, Digital Inputs

2

. . . . . . . . . . . VSS –2 V to VDD +2 V or

30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 100 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA

(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . .470 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

Truth Table (ADG453)

Logic Switch 1, 4 Switch 2, 3

0 OFF ON
1 ON OFF

ORDERING GUIDE

Temperature Package

Model Range Options*

ADG451BN –40°C to +85°C N-16
ADG451BR –40°C to +85°C R-16A
ADG452BN –40°C to +85°C N-16
ADG452BR –40°C to +85°C R-16A
ADG453BN –40°C to +85°C N-16
ADG453BR –40°C to +85°C R-16A

*N = Plastic DIP; R = Small Outline IC (SOIC).

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG451/ADG452/ADG453 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

ADG451/ADG452/ADG453

TERMINOLOGY

V

DD

V

SS

Most positive power supply potential.

Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.

V

L

Logic power supply (+5 V).

GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R

ON

∆R

ON

R

FLAT(ON)

Ohmic resistance between D and S.

On resistance match between any two channels
i.e., R

max – RONmin.

ON

Flatness is defined as the difference between the
maximum and minimum value of on-resistance as
measured over the specified analog signal range.

I

(OFF) Source leakage current with the switch “OFF.”

S

(OFF) Drain leakage current with the switch “OFF.”

I

D

ID, IS (ON) Channel leakage current with the switch “ON.”

VD (VS) Analog voltage on terminals D, S.

(OFF) “OFF” switch source capacitance.

C

S

(OFF) “OFF” switch drain capacitance.

C

D

, CS (ON) “ON” switch capacitance.

C

D

t

ON

Delay between applying the digital control input

and the output switching on. See Test Circuit 4.

t

OFF

Delay between applying the digital control input

and the output switching off.

t

D

“OFF” time or “ON” time measured between
the 90% points of both switches, when switching
from one address state to another. See Test
Circuit 5.

Crosstalk A measure of unwanted signal coupled through

from one channel to another as a result of para­sitic capacitance.

Off Isolation A measure of unwanted signal coupling through

an “OFF” switch.

Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output dur-

ing switching.

9

8

7

6

5

– V

ON

R

4

3

2

1

0

–16.5

–13.5

–10.5

VD OR VS DRAIN OR SOURCE VOLTAGE – V

–7.5

VDD = +5V
V

SS

–4.5

= –5V

VDD = +13.5V

= –13.5V

V

SS

VDD = +15V

= –15V

V

SS

1.5

–1.5

4.5

Figure 1. On Resistance as a Function of VD (VS)

for Various Dual Supplies

TA = +258C
V

= +5V

L

VDD = +16.5V
V

= –16.5V

SS

7.5

10.5

13.5

16.5

7

6

5

4

– V

ON

3

R

2

1

0

–15

+858C

+258C

–408C

–10 –5

V

OR VS DRAIN OR SOURCE VOLTAGE – V

D

0510

VDD = +15V
V

= –15V

SS

V

= +5V

L

Figure 2. On Resistance as a Function of VD (VS)
for Different Temperatures with Dual Supplies

15

–6–

REV. A

Typical Performance Characteristics–

LEAKAGE CURRENT – nA

0.5

–15

–12

0.4

0.3

0.2

–0.2
–0.3
–0.4

–0.5

0.1

0

–0.1

ID(ON)

V

D

OR VS DRAIN OR SOURCE VOLTAGE – V

ID(OFF)

IS(OFF)

–9

–6 –3 15

12

9630

VDD = +15V
V

SS

= –15V

T

A

= +258C

V

L

= +5V

ADG451/ADG452/ADG453

16

VDD = +5V

14

V

= 0V

SS

12

10

– V

8

ON

R

6

4

2

0

0

VDD = +13.5V
V

= 0V

SS

3

V

OR VS DRAIN OR SOURCE VOLTAGE – V

D

V

= +15V

DD

V

= 0V

SS

6

9

VDD = +16.5V
V

= 0V

SS

12 15

TA = +258C
V

= +5V

L

18

Figure 3. On Resistance as a Function of VD (VS) for
Various Single Supplies

10

VDD = +15V
V

= –15V

SS

V

= +5V

L

V

= +15V

D

V

= –15V

S

1.0

ID(ON)

12
11
10

9
8
7

– V

6

ON

R

5
4
3
2
1
0

VDD = +15V
VSS = 0V
VL = +5V

0

2468

VD OR VS DRAIN OR SOURCE VOLTAGE – V

10

12 14

Figure 6. On Resistance as a Function of VD (VS)
for Different Temperatures with Single Supplies

+858C

+258C

–408C

16

Figure 4. Leakage Currents as a Function of Temperature

Figure 5. Supply Current vs. Input Switching Frequency

REV. A

0.1
ID(OFF)

LEAKAGE CURRENT – nA

0.01
25

100k

VDD = +15V
V

10k

SS

V

SS

1k

100

– mA

10

SUPPLY

I

1.0

0.1

0.01
10 100 1k 10k 100k 1M 10M

IS(OFF)

35 45 55 65 75 85

= –15V
= +5V

TEMPERATURE – 8C

I+, I

+

I

FREQUENCY – Hz

4SW

L

1SW

–7–

Figure 7. Leakage Currents as a Function of VD (VS)

70

60

50

40

30

OFF ISOLATION – dB

20

10

0

1

10

FREQUENCY – MHz

VDD = +15V
V

= –15V

SS

V

= +5V

L

100

Figure 8. Off Isolation vs. Frequency

ADG451/ADG452/ADG453

120

100

80

60

40

CROSSTALK – dB

20

0

100 10k 100k 1M 10M

1k

FREQUENCY – Hz

VDD = 115V
VSS = –15V
VL = 15V
R

= 50V

LOAD

100M

Figure 9. Crosstalk vs. Frequency

0

–0.5

–1.0

–1.5

–2.0

LOSS – dB

–2.5

–3.0

–3.5

1

10

FREQUENCY – MHz

VDD = 115V
V

= –15V

SS

V

= 15V

L

100

Figure 10. Frequency Response with Switch On

200

APPLICATION

Figure 11 illustrates a precise, fast, sample-and-hold circuit.
An AD845 is used as the input buffer while the output
operational amplifier is an AD711. During the track mode,
SW1 is closed and the output V
V

. In the hold mode, SW1 is opened and the signal is

IN

held by the hold capacitor C

+5V

+15V

SW2

D

AD845

S

S

SW1

ADG451/
452/453

D

–15V

+15V

V

IN

–15V

follows the input signal

OUT

.

H

2200pF

C

C

1000pF

R

C

75V

CH
2200pF

+15V

AD711

–15V

V

OUT

Figure 11. Fast, Accurate Sample-and-Hold Circuit

Due to switch and capacitor leakage, the voltage on the
hold capacitor will decrease with time. The ADG451/
ADG452/ADG453 minimizes this droop due to its low
leakage specifications. The droop rate is further minimized
by the use of a polystyrene hold capacitor. The droop rate
for the circuit shown is typically 30 µV/µs.

A second switch, SW2, that operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differ­ential effect on the op amp AD711, which will minimize
charge injection effects. Pedestal error is also reduced by the
compensation network R

and CC. This compensation net-

C

work reduces the hold time glitch while optimizing the ac­quisition time. Using the illustrated op amps and component
values, the pedestal error has a maximum value of 5mV over
the ±10 V input range. Both the acquisition and settling
times are 850 ns.

–8–

REV. A

Test Circuits

ADG451/ADG452/ADG453

I

DS

V

1

IS(OFF) IS(OFF)

ID(ON)

V

S

RON = V1/I

DS

Test Circuit 1. On Resistance

+15V

0.1mF

V

S

V

S

IN

V

IN

GND

DD

0.1mF

+5V

V

D

V

–15V

V

S

Test Circuit 2. Off Leakage

0.1mF

L

V

R

L

300V

SS

C

L

35pF

Test Circuit 4. Switching Times

OUT

V

D

V

S

V

D

Test Circuit 3. On Leakage

3V

ADG451

V

IN

V

IN

ADG452

V

OUT

50%

3V

50% 50%

90% 90%

t

ON

t

50%

OFF

+15V

0.1mF 0.1mF

V

IN

S1

S2

IN1, IN2

GND

V

S1

V

S2

V

DD

ADG453

0.1mF

+5V

V

V

–15V

3V

L

D1

R

D2

R

L2

300V

SS

C

L2

35pF

V

OUT2

L1

300V

C

L1

35pF

V

OUT1

V

V

V

OUT1

OUT2

IN

0V

0V

0V

50%

90%

90% 90%

t

D

50%

90%

t

D

Test Circuit 5. Break-Before-Make Time Delay

REV. A

–9–

ADG451/ADG452/ADG453

R

S

V

S

IN

+15V

V

S

GND

+5V

V

L

D

V

–15V

DD

C

L

10nF

V

OUT

Test Circuit 6. Charge Injection

3V

V

IN

V

OUT

VIN = CL 3 DV

OUT

DV

OUT

+15V

SD

V

S

IN

V

GND

IN

+5V

0.1mF0.1mF

V

DD

0.1mF

V

V

SS

–15V

L

V

OUT

R

L

50V

Test Circuit 7. Off Isolation

0.1mF

+5V+15V

V

–15V

V

IN2

D

SS

CHANNEL-TO-CHANNEL
CROSSTALK = 20 3 LOG|V

50V

NC

S/VOUT

|

0.1mF 0.1mF

SD

V

V

S

V

OUT

IN1

R

L

50V

S

GND

Test Circuit 8. Channel-to-Channel Crosstalk

–10–

REV. A

16

18

9

0.840 (21.34)

0.745 (18.92)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)
MAX

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.160 (4.06)

0.115 (2.93)

0.325 (8.26)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Plastic DIP

(N-16)

16-Lead SOIC

(R-16A)

0.3937 (10.00)

0.3859 (9.80)

16 9

0.2440 (6.20)

81

0.2284 (5.80)

ADG451/ADG452/ADG453

REV. A

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

PIN 1

0.0500
(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

–11–

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88
08

0.0500 (1.27)

0.0160 (0.41)

x 458

C3119a–0–2/98

–12–

PRINTED IN U.S.A.