Datasheet ADG438F Datasheet (ANALOG DEVICES)

High Performance, 4-/8-Channel,

Fault-Protected Analog Multiplexers

FEATURES

All switches off with power supply off
Analog output of on channel clamped within power supplies

if an overvoltage occurs
Latch-up proof construction
Fast switching times

t

250 ns maximum

ON

t

150 ns maximum

OFF

Fault and overvoltage protection: −40 V to +55 V
Break-before-make construction
TTL- and CMOS-compatible inputs

APPLICATIONS

Data acquisition systems
Industrial and process control systems
Avionics test equipment
Signal routing between systems
High reliability control systems

ADG438F/ADG439F

FUNCTIONAL BLOCK DIAGRAM

ADG438F

S1

D

S8

1 OF 8

DECODER

A0

A1 A2 EN

Figure 1.

ADG439F

S1A

S4A

DA

00468-001

GENERAL DESCRIPTION

The ADG438F and ADG439F are CMOS analog multiplexers, with
the ADG438F comprising eight single channels and the ADG439F
comprising four differential channels. These multiplexers provide
fault protection. Using a series n-channel, p-channel, and
n-channel MOSFET structure, both device and signal source
protection is provided in the event of an overvoltage or power
loss. The multiplexer can withstand continuous overvoltage
inputs from −40 V to +55 V. During fault conditions with power
supplies off, the multiplexer input (or output) appears as an open
circuit and only a few nanoamperes of leakage current flows. This
protects not only the multiplexer and the circuitry driven by the
multiplexer, but also protects the sensors or signal sources which
drive the multiplexer.

The ADG438F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines, A0, A1, and A2.
The ADG439F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines, A0 and A1. An EN input on each device is used
to enable or disable the device. When disabled, all channels are
switched off.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

S1B

EN

DB

00468-101

S4B

1 OF 4

DECODER

A1

A0

Figure 2.

PRODUCT HIGHLIGHTS

1. Fault Protection. The ADG438F and ADG439F can with-

stand continuous voltage inputs up to −40 V or +55 V.
When a fault occurs due to the power supplies being
turned off, all the channels are turned off and only a
leakage current of a few nanoamperes flows.

2. On channel saturates while fault exists.

3. Low R

4. Fast Switching Times.

5. Break-Before-Make Switching. Switches are guaranteed

break-before-make so that input signals are protected
against momentary shorting.

6. Trench Isolation Eliminates Latch-Up. A dielectric trench

separates the p-channel and n-channel MOSFETs thereby
preventing latch-up.

7. Improved Off Isolation. Trench isolation enhances the

channel-to-channel isolation of the ADG438F/ADG439F.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ON

.

ADG438F/ADG439F

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Absolute Maximum Ratings............................................................ 5

REVISION HISTORY

7/11—Rev. D to Rev. E

Updated Format..................................................................Universal

Changes to Product Highlights Section and General

Description ........................................................................................ 1

Changes to Specification Section and Table 1 .............................. 3

Changes to Table 2............................................................................ 5

Added Table 3 and Table 4; Renumbered Sequentially ............... 6

Changes to Figure 5 to Figure 10.................................................... 7

Changes to Figure 11 to Figure 13.................................................. 8

Added Figure 14 to Figure 16.......................................................... 8

Changes to Figure 18 to Figure 20, Figure 23, and Figure 24 ..... 9

Changes to Terminology Section.................................................. 12

Changes to Theory of Operation Section, Figure 29, and

Figure 30 ..........................................................................................13

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 15

2/00—Rev. C to Rev. D

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics..............................................7

Test Circuits........................................................................................9

Terminology.................................................................................... 12

Theory of Operation ...................................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 15

Rev. E | Page 2 of 16

ADG438F/ADG439F

SPECIFICATIONS

DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

B Version

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS + 1.4 V typ Output open circuit

V

V

V

− 1.4 V typ

DD

+ 2.2 V typ Output loaded, 1 mA

SS

– 2.2 V typ

DD

RON 270 Ω typ −10 V ≤ VS ≤ +10 V, IS = 1 mA

390 420 450 Ω max See Figure 17

On-Resistance Flatness, R

9 % typ −10 V ≤ VS ≤ +10 V, IS = 1 mA

FLAT (ON)

10 10 10 10 % max

RON Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA

On-Resistance Match Between

Channels, ΔR

ON

3 3 3 3 % max VS = ±10 V, IS = 1 mA

LEAKAGE CURRENTS

Source Off Leakage, IS (Off ) ±0.01 nA typ

±0.5 ±1.5 ±1.5 ±4 nA max See Figure 18

Drain Off Leakage, ID (Off ) ±0.01 nA typ

ADG438F ADG439F ±0.5 ±5 ±5 ±20 nA max See Figure 19

Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = ± 10 V

ADG438F/ADG439F ±0.5 ±5 ±5 ±20 nA max See Figure 20

FAULT

Source Leakage Current, IS (Fault) ±0.02 nA typ

(With Overvoltage) ±0.05 ±0.1 ±0.2 ±0.2 μA max

Drain Leakage Current, ID (Fault) ±0.05 nA typ

(With Overvoltage) ±0.05 ±0.1 ±0.2 ±0.2 μA max

Source Leakage Current, IS (Fault)

±30 nA typ V

(Power Supplies Off)

±0.1 ±0.2 ±0.3 1 μA max See Figure 22

DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

2.4 2.4 2.4 V min

INH

0.8 0.8 0.8 V max

INL

Input Current

I

or I

INL

±1 ±1 ±1 μA max VIN = 0 V or VDD

INH

Digital Input Capacitance, CIN 5 pF typ

DYNAMIC CHARACTERISTICS1

t

175 ns typ RL = 1 MΩ, CL = 35 pF

TRANSITION

220 300 300 330 ns max

t

90

OPEN

60 40 40 40 ns min

tON (EN) 180 ns typ RL = 1 kΩ, CL = 35 pF

230 300 300 345 ns max VS = 5 V; see Figure 27

t

(EN) 100 ns typ RL = 1 kΩ, CL = 35 pF

OFF

130 150 150 173 ns max VS = 5 V; see Figure 27

−40°C to
+105°C

−40°C to
+125°C Unit Test Conditions/Comments

V

= ±10 V, VS = 10 V

D

V

= ±10 V, VS = 10 V

D

= +55 V or −40 V, VD = 0 V;

V

S

m

m

see Figure 21

V

= ±25 V, VD = 10 V; see mFigure 19

S

= ±25 V, VD = VEN, A0, A1, A2 = 0 V

S

V

= ±10 V, VS8 = m10 V; see Figure 25

S1

= 1 kΩ, CL = 35 pF, VS = 5 V;

R

L

see Figure 26

Rev. E | Page 3 of 16

ADG438F/ADG439F

B Version

−40°C to

Parameter +25°C

Settling Time, t

SETT

+85°C

0.1% 1 1 1 μs typ RL = 1 kΩ, CL = 35 pF

0.01% 2.5 2.5 2.5 μs typ VS = 5 V

Charge Injection 15 pC typ

Off Isolation 93 dB typ

Channel-to-Channel Crosstalk 93 dB typ

CS (Off ) 3 pF typ
CD (Off )

ADG438F 22 pF typ
ADG439F 12 pF typ

POWER REQUIREMENTS

IDD 0.05 mA typ VIN = 0 V or 5 V

0.1 0.2 0.2 0.2 mA max
ISS 0.1 μA typ

1 1 1 μA max

1

Guaranteed by design, not subject to production test.

−40°C to
+105°C

−40°C to
+125°C

Unit Test Conditions/Comments

= 0 V, RS = 0 Ω, CL = 1 nF;

V

S

see Figure 28

= 1 kΩ, CL = 15 pF, f = 100 kHz,

R

L

= 7 V rms; see Figure 23

V

S

= 1 kΩ, CL = 15 pF, f = 100 kHz,

R

L

V

= 7 rms; see Figure 24

S

Rev. E | Page 4 of 16

ADG438F/ADG439F

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted.

Table 2.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Digital Input, EN, Ax −0.3 V to VDD + 0.3 V or 20 mA,

VS, Analog Input Overvoltage with

Power On (V

VS, Analog Input Overvoltage with

Power Off (V

Continuous Current, S or D 20 mA
Peak Current, S or D (Pulsed at 1 ms,

10% Duty Cycle Maximum)

Operating Temperature Range

Industrial (B Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Plastic DIP Package

θJA, Thermal Impedance 117°C/W

SOIC Package

θJA, Thermal Impedance

Narrow Body 125°C/W
Wide Body 90°C/W

= +15 V, VSS = −15 V)

DD

= 0 V, VSS = 0 V)

DD

whichever occurs first
V

− 25 V to VDD + 40 V

SS

−40 V to +55 V

40 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 5 of 16

ADG438F/ADG439F

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A0

EN

V

SS

S1

S2

S3

S4

D

1

2

3

ADG438F

4

TOP VIEW

(Not to Scale)

5

6

7

8

16

A1

15

A2

14

GND

13

V

DD

S5

12

S6

11

S7

10

S8

9

00468-004

Figure 3. ADG438F Pin Configuration

1

A0

EN

V

S1A

S2A

S3A

S4A

DA

SS

2

3

ADG439F

4

TOP VIEW

(Not to Scale)

5

6

7

8

A1

16

GND

15

14

V

DD

13

S1B

S2B

12

S3B

11

10

S4B

DB

9

00468-005

Figure 4. ADG439F Pin Configuration

Table 3. ADG438F Pin Function Description

Pin
No. Mnemonic Description

1 A0 Logic Control Input.
2 EN

Active High Digital Input. When low, the
device is disabled, and all switches are off.
When high, Ax logic inputs determine on
switches.

3 VSS

Most Negative Power Supply Potential. In
single-supply applications, this pin can be
connected to ground.

4 S1

Source Terminal 1. This pin can be an input
or an output.

5 S2

Source Terminal 2. This pin can be an input
or an output.

6 S3

Source Terminal 3. This pin can be an input
or an output.

7 S4

Source Terminal 4. This pin can be an input
or an output.

8 D

Drain Terminal. This pin can be an input or
an output.

9 S8

Source Terminal 8. This pin can be an input
or an output.

10 S7

Source Terminal 7. This pin can be an input
or an output.

11 S6

Source Terminal 6. This pin can be an input
or an output.

12 S5

Source Terminal 5. This pin can be an input

or an output.
13 VDD Most Positive Power Supply Potential.
14 GND Ground (0 V) Reference.
15 A2 Logic Control Input.
16 A1 Logic Control Input.

Table 4. ADG439F Pin Function Description

Pin
No. Mnemonic Description

1 A0 Logic Control Input.
2 EN

Active High Digital Input. When low, the
device is disabled, and all switches are off.
When high, Ax logic inputs determine on
switches.

3 VSS

Most Negative Power Supply Potential. In
single-supply applications, this pin can be
connected to ground.

4 S1A

Source Terminal 1A. This pin can be an
input or an output.

5 S2A

Source Terminal 2A. This pin can be an
input or an output.

6 S3A

Source Terminal 3A. This pin can be an
input or an output.

7 S4A

Source Terminal 4A. This pin can be an
input or an output.

8 DA

Drain Terminal A. This pin can be an input
or an output.

9 DB

Drain Terminal B. This pin can be an input
or an output.

10 S4B

Source Terminal 4B. This pin can be an
input or an output.

11 S3B

Source Terminal 3B. This pin can be an
input or an output.

12 S2B

Source Terminal 2B. This pin can be an
input or an output.

13 S1B

Source Terminal 1B. This pin can be an

input or an output.
14 VDD Most Positive Power Supply Potential.
15 GND Ground (0 V) Reference.
16 A1 Logic Control Input.

Table 5. ADG438F Truth Table1

A2 A1 A0 EN On Switch

X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8

1

X = don’t care.

Table 6. ADG439F Truth Table1

A1 A0 EN On Switch Pair

X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4

1

X = don’t care.

Rev. E | Page 6 of 16

ADG438F/ADG439F

m

m

m

TYPICAL PERFORMANCE CHARACTERISTICS

2000

1750

1500

1250

(Ω)

1000

ON

R

750

500

TA = 25°C

VDD = +5V
VSS = –5V

= +10V

V

DD

V

= –10V

SS

V

= +15V

DD

V

= –15V

SS

2000

1750

1500

1250

(Ω)

1000

ON

R

750

500

TA = 125°C
T

= 105°C

A

T

= 85°C

A

T

= 25°C

A

VDD = +15V

= –15V

V

SS

250

0

, VS(V)

V

D

Figure 5. On Resistance as a Function of V

1

100µ

10µ

1µ

100n

10n

1n

INPUT LE AKAGE (A)

S

I

100p

10p

1p

–40

–50 –30 –20 –10 0 10 20 30 40 50 60

OPERATING RANGE

V

SOURCE VOLTAGE (V)

S

V

DD

V

SS

V

D

Figu re 6. Source Input Leakage Current as a Function of V

During Overvoltage Conditions

1

100µ

10µ

1µ

100n

10n

1n

INPUT LEAKAGE (A)

D

I

100p

10p

1p

–40

–50 –30 –20 –10 0 10 20 30 40 50 60

OPERATING RANGE

V

SOURCE VOLTAGE (V)

S

V
V
V

DD
SS
D

= 0V

= –15V

Figu re 7. Drain Output Leakage Current as a Function of V

During Overvoltage Conditions

15–15 –10 –5 0 5 10

(VS)

D

= 0V
= 0V

= 0V

(Power Supplies Off)

S

= +15V

(Power Supplies On)

S

250

0

, VS(V)

00468-008

Figure 8. On Resistance as a Function of V

1

100µ

10µ

1µ

100n

10n

1n

INPUT LE AKAGE (A)

S

I

100p

10p

1p

–40

00468-009

–50 –30 –20 –10 0 10 20 30 40 50 60

Figure 9. Source Input Leakage Current as a Function of V

V

D

D

OPERATING RANGE

SOURCE VOLTAGE (V)

V

S

(VS) for Different Temperatures

= +15V

V

DD

= –15V

V

SS

= 0V

V

D

(Power Supplies On)

S

15–15 –10 –5 0 5 10

00468-011

00468-012

During Overvoltage Conditions

0.3

VDD = +15V
V

= –15V

0.2

0.1

0.0

–0.1

LEAKAGE CURRENTS ( nA)

–0.2

–0.3

00468-010

SS

V

(VD) = ±10V

S

T

= 25°C

A

ID(OFF)

IS(OFF)

ID, IS(ON)

–14 –10 –6 –2 2 6 10 14

Figure 10. Leakage Currents as a Function of V

V

S,VD

(V)

D

(VS)

00468-013

Rev. E | Page 7 of 16

ADG438F/ADG439F

A

A

100

VDD = +15V

= –15V

V

SS

= +10V

V

D

10

0.1

LEAKAGE CURRENTS (n A)

= –10V

V

S

1

ID(ON)

ID(OFF)

IS(OFF)

TION (dB)

OFF ISOL

–20

–40

–60

–80

–100

0

TA = 25°C

= +15V

V

DD

= –15V

V

SS

0.01
45 5525 65 75 85 95 10535

TEMPERAT URE (°C)

Figure 11. Leakage Currents as a Function of Temperature

260

240

220

200

180

160

SWITCHING TIME (ns)

140

120

100

10 11 12 13 14 15

t

TRANSITION

t

(EN)

ON

t

(EN)

OFF

POWER SUPPLY (V)

Figure 12. Switching Time vs. Dual Power Supply

300

VDD = +15V
V

= –15V

SS

250

200

150

100

SWITCHI NG TIME (ns)

t

(EN)

ON

t

TRANSITION

t

OFF

115 125

(EN)

–120

00468-014

10k 100k 1M 10M 100M 1G1k

FREQUENCY (Hz)

00468-113

Figure 14. Off Isolation vs. Frequency, ±15 V Dual Supply

40

TA = 25°C

= +15V

V

35

DD

= –15V

V

SS

30

25

20

PACITANCE (pF)

15

PIN C

10

5

0
–15 –10 –5 0 5 10 15

00468-015

DRAIN OFF

SOURCE OFF

VS (V)

00468-114

Figure 15. Capacitance vs. Source Voltage

30

VDD = +15V
V

= –15V

SS

T

= 25°C

20

A

10

(pC)

0

INJ

Q

–10

50

0
–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 13. Switching Time vs. Temperature

00468-016

–20

–30

–15 –10 –5 0 5 10 15

VS (V)

Figure 16. Charge Injection vs. Source Voltage

00468-115

Rev. E | Page 8 of 16

ADG438F/ADG439F

V

V

VDDV

V

VDDV

V0V

V

V

V

TEST CIRCUITS

I

DS

V

DDVSS

DD

DD

V

DD

V

V

SS

D

0.8VEN
V

D

00468-026

0

V

SS

V

A

S1

S8

D

S

00468-027

S1

S8

D

R

SS

SS

50Ω

V

IN

V

OUT

L

00468-034

V1

S1

A

S

S

R

ON

Figure 17. On Resistance

= V1/I

D

DS

00468-021

Figure 21. Input Leakage Current (with Overvoltage)

S2

S8

S

V

DDVSS

V

IS (OFF)

A

V

S

V

D

DDVSS

S1

S2

S8

Figure 18. I

(Off)

S

D

0.8VEN

00468-022

0V

*SIMILAR CONNECTION FORADG439F.

Figure 22. Input Leakage Current (with Power Supplies Off)

V

A2

A1

ADG438F*

A0

EN

GND

SS

V

DDVSS

S1

S2

S8

S

Figure 19. I

(Off)

D

D

ID (OFF)

A

0.8VEN

V

D

00468-023

*SIMILAR CONNECTIO N FOR ADG439F.

A2

A1

A0

ADG438F*

GND

Figure 23. Off Isolation

SD

NC

NC = NO CONNECT

Figure 20. I

DD

0.1µF

NETWORK

ANALYZER

V

OUT

R

L

50Ω

V

S

ID (ON)

A

CHANNEL-TO-CHANNEL CROSS TALK = 20 l og

Figure 24. Channel-to-Channel Crosstalk

(On)

D

V

D

00468-025

V

S1

S2

SS

0.1µF

V

DD

GND

SS

D

R
50Ω

V

OUT

V

S

00468-200

Rev. E | Page 9 of 16

ADG438F/ADG439F

VSSV

VSSV

VSSV

DD

ADDRESS

DRIVE (V

3V

50%

t

TRANSITION

90%

00468-024

t

TRANSITION

TRANSITION

50%

90%

)

IN

V

OUT

V

DD

A2

V

50Ω

IN

2.4V

*SIMIL AR CONNECTI ON FOR ADG439F.

A1

A0

ADG438F*

EN

GND

S2 TO S7

V

SS

V

S1

S1

V

S8

S8

D

R

L

1MΩ

C

L

35pF

V

OUT

Figure 25. Switching Time of Multiplexer, t

DD

V

DD

A2

50Ω

V

IN

A1

S2 TO S7

A0

ADG438F*

2.4V

*

*SIMILAR CONNECTION FOR ADG439F.

EN

GND

V

SS

S1

S8

D

R
1kΩ

V

S

V

OUT

C

L

L

35pF

Figure 26. Break-Before-Make Delay, t

ADDRESS

DRIVE (V

3V

)

IN

t

OPEN

80%

00468-029

OPEN

80%

V

OUT

DD

V

V

A2

A1

A0

DD

SS

S2 TO S8

ADG438F*

EN

V

IN

*SIMIL AR CONNECTI ON FOR ADG439 F.

50Ω

GND

R
1kΩ

V

S

V

OUT

C

L

L

35pF

S1

D

Figure 27. Enable Delay, t

ENABLE

DRIVE (V

V

OUTPUT

OUT

3V

)

IN

0V

0.9V

0V

(EN), t

OFF

(EN)

ON

50%50%

OUT

0.1V

OUT

t

t

(EN)

ON

OFF

(EN)

00468-030

Rev. E | Page 10 of 16

ADG438F/ADG439F

V

V

DD

V

DD

A2

A1

R

S

V

S

V

*SIMILAR CONNECTION FOR ADG439F.

A0

S

EN

IN

GND

SS

V

SS

ADG438F*

3V

LOGIC

INPUT (V

D

C
1nF

V

OUT

L

)

IN

0V

OUT

∆V

OUT

00468-033

V

OUT

Q

= CL × ∆V

INJ

Figure 28. Charge Injection

Rev. E | Page 11 of 16

ADG438F/ADG439F

TERMINOLOGY

C

(Off)

VDD

Most positive power supply potential.

V

SS

Most negative power supply potential.

GND

Ground (0 V) reference.

R

ON

Ohmic resistance between D and S.

ΔR

ON

ΔR

represents the difference between the RON of any two

ON

channels as a percentage of the maximum R

of those two

ON

channels.

R

FLAT (ON)

Flatness is defined as the difference between the maximum and
minimum value of the on resistance measured over the specified
analog signal range and is represented by R

FLAT (ON)

.

Flatness is calculated by

((R

− R

) / R

MAX

Drift

R

ON

Change in R

(Off)

I

S

MIN

when temperature changes by one degree Celsius.

ON

MAX

× 100)

Source leakage current when the switch is off.

I

(Off)

D

Drain leakage current when the switch is off.

I

, IS (On)

D

Channel leakage current when the switch is on.

V

(VS)

D

Analog voltage on Terminal D and Terminal S.

I

(Fault—Power Supplies On)

S

Source leakage current when exposed to an overvoltage
condition.

I

(Fault—Power Supplies On)

D

Drain leakage current when exposed to an overvoltage
condition.

I

(Fault—Power Supplies Off)

S

Source leakage current with power supplies off.

S

Channel input capacitance for off condition.

C

(Off)

D

Channel output capacitance for off condition.

C

, CS (On)

D

On switch capacitance.

C

IN

Digital input capacitance.

t

(EN)

ON

Delay time between the 50% and 90% points of the digital input
and switch on condition.

t

(EN)

OFF

Delay time between the 50% and 90% points of the digital input
and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

t

OPEN

Off time measured between 80% points of both switches when
switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

I

(I

)

INL

INH

Input current of the digital input.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

I

DD

Positive supply current.

I

SS

Negative supply current.

Rev. E | Page 12 of 16

ADG438F/ADG439F

THEORY OF OPERATION

The ADG438F/ADG439F multiplexers are capable of withstanding
overvoltages from −40 V to +55 V, irrespective of whether the
power supplies are present or not. Each channel of the multiplexer
consists of an n-channel MOSFET, a p-channel MOSFET, and
an n-channel MOSFET, connected in series. When the analog
input exceeds the power supplies, one of the MOSFETs saturates,
limiting the current. The current during a fault condition is
determined by the load on the output. Figure 31 illustrates the
channel architecture that enables these multiplexers to with­stand continuous overvoltages.

When an analog input of V

+ 2.2 V to VDD – 2.2 V (output loaded,

SS

1 mA) is applied to the ADG438F/ADG439F, the multiplexer
behaves as a standard multiplexer, with specifications similar to
a standard multiplexer, for example, the on-resistance is 270 Ω
typically. However, when an overvoltage is applied to the device,
one of the three MOSFETs saturates.

Figure 29 to Figure 32 show the conditions of the three
MOSFETs for the various overvoltage situations. When the
analog input applied to an on channel approaches the positive
power supply line, the n-channel MOSFET saturates because
the voltage on the analog input exceeds the difference between
V

and the n-channel threshold voltage (VTN). When a voltage

DD

more negative than V

is applied to the multiplexer, the p-channel

SS

MOSFET saturates because the analog input is more negative
than the difference between V
voltage (V

). Because VTN is nominally 1.4 V and VTP − 1.4 V,

TP

the analog input range to the multiplexer is limited to V
to V

− 1.4 V (output open circuit) when a ±15 V power supply

DD

and the p-channel threshold

SS

+ 1.4 V

SS

is used.

When the power supplies are present but the channel is off, again
either the p-channel MOSFET or one of the n-channel MOSFETs
remains off when an overvoltage occurs.

Finally, when the power supplies are off, the gate of each MOSFET
is at ground. A negative overvoltage switches on the first n-channel
MOSFET, but the bias produced by the overvoltage causes the
p-channel MOSFET to remain turned off. With a positive over­voltage, the first MOSFET in the series remains off because the
gate to source voltage applied to this MOSFET is negative.

During fault conditions (power supplies off), the leakage current
into and out of the ADG438F/ADG439F is limited to a few
microamps. This limit protects the multiplexer and succeeding
circuitry from over stresses as well as protects the signal sources
that drive the multiplexer. Also, the other channels of the multi­plexer are undisturbed by the overvoltage and continue to operate
normally.

OVERVOLTAGE

+55V

n-CHANNEL

MOSFET

SATURATES

Figure 29. +55 V Overvoltage Input to the On Channel

OVERVOLTAGE

Figure 30. −40 V Overvoltage on an Off Channel with Multiplexer Power On

–40V

n-CHANNEL

MOSFET

IS ON

OVERVOLTAGE

+55V

n-CHANNE L

MOSFET IS

OFF

Figure 31. +55 V Overvoltage with Power Off

OV ERV OLTAG E

–40V

n-CHANNEL

MOSFET IS

ON

Figure 32. –40 V Overvoltage with Power Off

Q1 Q2 Q3

V

DD

V

SS

V

SS

Q1 Q2 Q3

p-CHANNEL

V

DD

SATURATES

Q1 Q2 Q3

Q1 Q2 Q3

p-CHANNEL

MOSFET IS

MOSFET

OFF

00468-017

00468-018

00468-019

00468-020

Rev. E | Page 13 of 16

ADG438F/ADG439F

OUTLINE DIMENSIONS

0.800 (20.32)

0.790 (20.07)

0.780 (19.81)

16

1

0.100 (2.54)
BSC

0.210 (5.33)
MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTROLLING DIMENSIONS ARE IN INCHES ; MILLIMETER DI MENSIONS
(IN PARENTHESES) ARE RO UNDED-OFF INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE I N DESIGN.
CORNER LEADS M AY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 33. 16-Lead Plastic Dual In-Line Package [PDIP]

10.00 (0.3937)

9.80 (0.3858)

9

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

8

0.060 (1.52)

0.015
(0.38)

0.015 (0.38)

MIN

SEATING
PLANE

0.005 (0.13)
MIN

COMPLI ANT TO JEDEC STANDARDS MS-001- AB

GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

MAX

0.430 (10.92)

Narrow Body

(N-16)

Dimensions shown in inches and (millimeters)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

073106-B

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

COMPLIANT TO JEDEC STANDARDS MS-012-AC

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; I NCH DIMENSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

060606-A

Figure 34. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-16)

Dimensions shown in millimeters and (inches)

Rev. E | Page 14 of 16

ADG438F/ADG439F

C

10.50 (0.4134)

10.10 (0.3976)

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

2

9

5

(

5

0

.

(

5

0

.

)

0

45°

)

0

0

9

8

1.27 (0.0500)

0.40 (0.0157)

03-27-2007-B

0

.

7
2

0

.

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 35. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG438FBN −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG438FBNZ −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG438FBR −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG438FBR-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG438FBRZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG438FBRZ-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG439FBN −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG439FBNZ −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG439FBR −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG439FBR-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG439FBRW −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADG439FBRWZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADG439FBRWZ-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADG439FBRZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG439FBRZ-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

1

Z = RoHS Compliant Part.

Rev. E | Page 15 of 16

ADG438F/ADG439F

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00468-0-7/11(E)

Rev. E | Page 16 of 16