Datasheet ADG432, ADG431, ADG433 Datasheet (Analog Devices)

LC2MOS

a

FEATURES
44 V Supply Maximum Ratings
ⴞ15 V Analog Signal Range
Low On Resistance (<24 ⍀)
Ultralow Power Dissipation (3.9 ␮W)
Low Leakage (<0.25 nA)
Fast Switching Times

t

<165 ns

ON

t

<130 ns

OFF

Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413

APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems

GENERAL DESCRIPTION

The ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
low power dissipation yet gives high switching speed and low on
resistance.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa­tion making the parts ideally suited for portable and battery
powered instruments.

The ADG431, ADG432 and ADG433 contain four indepen­dent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.

Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.

2

MOS process which provides

Precision Quad SPST Switches

ADG431/ADG432/ADG433

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

ADG433

IN1

IN2

ADG432

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

IN1

IN2

ADG431

IN3

IN4

SWITCHES SHOWN FOR A LOGIC "1" INPUT

PRODUCT HIGHLIGHTS

1. Extended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC

2

MOS process giving an increased signal range

which extends fully to the supply rails.

2. Ultralow Power Dissipation

3. Low R

ON

4. Break-Before-Make Switching
This prevents channel shorting when the switches are config­ured as a multiplexer.

5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432 and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.

S1

D1
S2

D2
S3

D3
S4

D4

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADG431/ADG432/ADG433–SPECIFICATIONS

1

Dual Supply

(VDD = +15 V ⴞ 10%, VSS = –15 V ⴞ 10%, VL = +5 V ⴞ 10%, GND = O V, unless otherwise noted)

B Versions T Versions

–40ⴗC to –55ⴗC to

Parameter +25ⴗC +85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V
R

ON

17 17 Ω typ VD = ±8.5 V, I
24 26 24 27 Ω max V

vs. VD (VS) 15 15 % typ

R

ON

Drift 0.5 0.5 %/°C typ

R

ON

DD

to V

SS

VDD to VSSV

= –10 mA;

= +13.5 V, VSS = –13.5 V

DD

S

RON Match 5 5 % typ VD = 0 V, IS = –10 mA

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.05 ±0.05 nA typ VD = ±15.5 V, V

S

= +16.5 V, VSS = –16.5 V

DD

= ⫿15.5 V;

S

±0.25 ±2 ±0.25 ±15 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.05 ±0.05 nA typ VD = ±15.5 V, V

D

= ⫿15.5 V;

S

±0.25 ±2 ±0.25 ±15 nA max Test Circuit 2

Channel ON Leakage I

(ON) ±0.1 ±0.1 nA typ V

D

S

= V

D

= ±15.5 V;

S

, I

±0.35 ±3 ±0.35 ±17 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 2.4 V min

0.8 0.8 V max

Input Current

I

INL

or I

INH

0.005 0.005 µA typ V

IN

= V

INL

or V

INH

±0.02 ±0.02 µA max

CIN Digital Input Capacitance 9 9 pF typ

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t
(ADG433 Only) V

2

90 90 ns typ R

165 175 ns max V

60 60 ns typ R

130 145 ns max V

25 25 ns typ R

D

VDD = +15 V, VSS = –15 V

= 300 Ω, C

L

= ±10 V; Test Circuit 4

S

= 300 Ω, C

L

= ±10 V; Test Circuit 4

S

= 300 Ω, C

L

= VS2 = +10 V;

S1

= 35 pF;

L

= 35 pF;

L

= 35 pF;

L

Test Circuit 5

Charge Injection 5 5 pC typ V

= 0 V, R

S

= 0 Ω, C

S

= 10 nF;

L

Test Circuit 6

OFF Isolation 68 68 dB typ R

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 85 85 dB typ R

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 8

(OFF) 9 9 pF typ f = 1 MHz

C

S

(OFF) 9 9 pF typ f = 1 MHz

C

D

CD, CS (ON) 35 35 pF typ f = 1 MHz

POWER REQUIREMENTS V

= +16.5 V, VSS = –16.5 V

DD

Digital Inputs = 0 V or 5 V

I

DD

0.0001 0.0001 µA typ

0.1 0.2 0.1 0.2 µA max

I

SS

0.0001 0.0001 µA typ

0.1 0.2 0.1 0.2 µA max

I

L

0.0001 0.0001 µA typ

0.1 0.2 0.1 0.2 µA max

Power Dissipation 7.7 7.7 µW max

NOTES

1

Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. B–2–

ADG431/ADG432/ADG433

Single Supply

(VDD = +12 V ⴞ 10%, VSS = O V, VL = +5 V ⴞ 10%, GND = O V, unless otherwise noted)

B Versions T Versions

–40ⴗC to –55ⴗC to

Parameter +25ⴗC +85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
R

ON

28 28 Ω typ 0 < V

DD

42 45 42 45 Ω max V

vs. VD (VS) 20 20 % typ

R

ON

Drift 0.5 0.5 %/°C typ

R

ON

0 V to VDDV

< 8.5 V, IS = –10 mA;

D

= +10.8 V

DD

RON Match 5 5 % typ VD = 0 V, IS = –10 mA

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.04 ±0.04 nA typ V

S

= +13.2 V

DD

= 12.2/1 V, VS = 1/12.2 V;

D

±0.25 ±2 ±0.25 ±15 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.04 ±0.04 nA typ V

D

= 12.2/1 V, VS = 1/12.2 V;

D

±0.25 ±2 ±0.25 ±15 nA max Test Circuit 2

Channel ON Leakage I

, Is (ON) ±0.01 ±0.01 nA typ V

D

= VS = +12.2 V/+1 V;

D

±0.3 ±3 ±0.3 ±17 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 2.4 V min

0.8 0.8 V max

Input Current

I

INL

or I

INH

0.005 0.005 µA typ V

IN

= V

INL

or V

INH

±0.01 ±0.01 µA max

CIN Digital Input Capacitance 9 9 pF typ

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t
(ADG433 Only) V

2

165 165 ns typ R

240 240 ns max V

60 60 ns typ R

115 115 ns max V

25 25 ns typ R

D

VDD = +12 V, VSS = 0 V

= 300 Ω, C

L

= +8 V; Test Circuit 4

S

= 300 Ω, C

L

= +8 V; Test Circuit 4

S

= 300 Ω, C

L

= VS2 = +10 V;

S1

= 35 pF;

L

= 35 pF;

L

= 35 pF;

L

Test Circuit 5

Charge Injection 25 25 pC typ V

= 0 V, R

S

= 0 Ω, C

S

= 10 nF;

L

Test Circuit 6

OFF Isolation 68 68 dB typ R

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 85 85 dB typ R

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 8

(OFF) 9 9 pF typ f = 1 MHz

C

S

(OFF) 9 9 pF typ f = 1 MHz

C

D

CD, CS (ON) 35 35 pF typ f = 1 MHz

POWER REQUIREMENTS V

= +13.2 V

DD

Digital Inputs = 0 V or 5 V

I

DD

0.0001 0.0001 µA typ

0.03 0.1 0.03 0.1 µA max

I

L

0.0001 0.0001 µA typ

0.03 0.1 0.03 0.1 µA max V

= +5.25 V

L

Power Dissipation 1.9 1.9 µW max

NOTES

1

Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

Truth Table (ADG431/ADG432)

Truth Table (ADG433)

ADG431 In ADG432 In Switch Condition

01ON
1 0 OFF

REV. B

Logic Switch 1, 4 Switch 2, 3

0 OFF ON
1 ON OFF

–3–

ADG431/ADG432/ADG433

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

V

SS

to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

L

Analog, Digital Inputs

2

. . . . . . . . . . V

– 2 V to VDD + 2 V or

SS

30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma­nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

(DIP/SOIC)

IN1

D1
S1

V

GND

S4
D4

IN4

1

2

3

4

SS

5

6

7

8

ADG431
ADG432
ADG433

TOP VIEW

(Not to Scale)

IN2

16

D2

15

S2

14

V

13

DD

V

12

L

S3

11

D3

10

IN3

9

1

Model

ADG431BN –40°C to +85°C N-16
ADG431BR –40°C to +85°C R-16A
ADG431TQ –55°C to +125°C Q-16
ADG431ABR –40°C to +85°C R-16A

ADG432BN –40°C to +85°C N-16
ADG432BR –40°C to +85°C R-16A
ADG432TQ –55°C to +125°C Q-16
ADG432ABR –40°C to +85°C R-16A

ADG433BN –40°C to +85°C N-16

ORDERING GUIDE

Temperature Range Package Options

ADG433BR –40°C to +85°C R-16A
ADG433ABR –40°C to +85°C R-16A

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.

2

N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.

3

Trench isolated, latch-up proof parts. See Trench Isolation section.

2

3

3

3

V

DD

V

SS

Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.

V

L

Logic power supply (+5 V).
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R

ON

vs. VD (VS) The variation in RON due to a change in the ana-

R

ON

Ohmic resistance between D and S.

log input voltage with a constant load current.

Drift Change in RON vs. temperature.

R

ON

Match Difference between the RON of any two switches.

R

ON

(OFF) Source leakage current with the switch “OFF.”

I

S

(OFF) Drain leakage current with the switch “OFF.”

I

D

, IS (ON) Channel leakage current with the switch “ON.”

I

D

VD (VS) Analog voltage on terminals D, S.

TERMINOLOGY

CS (OFF) “OFF” switch source capacitance.

(OFF) “OFF” switch drain capacitance.

C

D

, CS (ON) “ON” switch capacitance.

C

D

C

IN

t

ON

t

OFF

t

D

Crosstalk A measure of unwanted signal which is coupled

Off Isolation A measure of unwanted signal coupling through an

Charge A measure of the glitch impulse transferred from the
Injection digital input to the analog output during switching.

Input Capacitance to ground of a digital input.
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.

through from one channel to another as a result
of parasitic capacitance.

“OFF” switch.

REV. B–4–

Typical Performance Graphs

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

50

40

10

05

R

ON

– V

10 15 20

30

20

TA = +258C
VL = +5V

0

VDD = +15V
V

SS

= 0V

V

DD

= +10V

V

SS

= 0V

VDD = +12V
V

SS

= 0V

VDD = +5V
V

SS

= 0V

FREQUENCY – Hz

100mA

100nA

10

10M100

I

SUPPLY

1k 10k 100k 1M

10mA

1mA

100mA

10mA

1mA

VDD = +15V 4 SW
V

SS

= –15V

VL = +5V

1 SW

I+, I–

I

L

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

0.04

0.02

–0.04

–20 –10

LEAKAGE CURRENT – nA

01020

0.00

–0.02

VDD = +15V
V

SS

= –15V

T

A

= +258C

VL = +5V

ID (ON)

I

S

(OFF)

ID (OFF)

ADG431/ADG432/ADG433

50

40

30

– V

ON

R

20

10

VDD = +15V
V

= –15V

SS

0
–20 –10

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

VDD = +5V
V

SS

VDD = +10V
V

= –10V

SS

= –5V

01020

TA = +258C
VL = +5V

VDD = +12V
V

= –12V

SS

Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies

50

VDD = +15V
V

= –15V

SS

40

30

– V

ON

R

20

10

VL = +5V

+1258C

+858C
+258C

Figure 4. On Resistance as a Function of VD (VS) Single
Supply

Figure 3. Leakage Currents as a Function of Temperature

REV. B –5–

0
–20 –10

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

01020

Figure 2. On Resistance as a Function of
V

(VS) for Different Temperatures

D

10

VDD = +15V
V

= –15V

SS

VL = +5V

1

VS = 615V
V

= 615V

D

0.1

LEAKAGE CURRENT – nA

0.01

0.001
20 12040

(OFF)

I

S

I

(OFF)

D

ID (ON)

60 80 100

TEMPERATURE – 8C

Figure 5. Supply Current vs. Input Switching Frequency

140

Figure 6. Leakage Currents as a Function of VD (VS)

ADG431/ADG432/ADG433

120

100

80

OFF ISOLATION – dB

60

40

100 10M1k

10k 100k 1M

FREQUENCY – Hz

Figure 7. Off Isolation vs. Frequency

110

100

90

80

CROSSTALK – dB

70

60

100 10M1k

10k 100k 1M

FREQUENCY – Hz

Figure 8. Crosstalk vs. Frequency

VDD = +15V
V

= –15V

SS

VL = +5V

VDD = +15V
VSS = –15V
V

= +5V

L

V

G

V

S

+

P

–

N

P-CHANNEL

T
R
E
N
C
H

V

D

T

+

P

R
E
N
C
H

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

V

N

P

S

+

–

V

G

N-CHANNEL

V

D

T

+

N

R
E
N
C
H

Figure 9. Trench Isolation

APPLICATION

Figure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V

follows the input signal VIN. In the hold

OUT

mode, SW1 is opened and the signal is held by the hold capaci-

.

tor C

H

Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica­tions. The droop rate is further minimized by the use of a poly­styrene hold capacitor. The droop rate for the circuit shown is

typically 30 µV/µs.

A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen­tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa­tion network R

and CC. This compensation network also

C

reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the

pedestal error has a maximum value of 5 mV over the ±10 V

input range. Both the acquisition and settling times are 850 ns.

TRENCH ISOLATION

In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.

+15V +5V

+15V

V

IN

AD845

–15V

SW2

S

SW1

S

ADG431
ADG432
ADG433

–15V

2200pF

D

R

C

75V

D

2200pF

Figure 10. Fast, Accurate Sample-and-Hold

C

C

1000pF

C

H

+15V

AD711

–15V

V

OUT

REV. B–6–

Test Circuits

SD

V

S

V

D

A

ID (ON)

V

S

I

DS

V1

SD

RON = V1/I

DS

ADG431/ADG432/ADG433

I

IS (OFF)

V

S

A

SD

(OFF)

D

A

V

D

Test Circuit 1. On Resistance

0.1mF 0.1mF

V

S

0.1mF 0.1mF

V

S1

V

S2

S1 D1

S2

IN1, IN2

V

IN

GND

+15V +5V

V

DDVL

V

0.1mF
–15V

IN

SS

Test Circuit 2. Off Leakage

+15V +5V

3V

V

DDVL

SD

V

GND

SS

0.1mF
–15V

R

L

300V

C

L

35pF

V

OUT

V

ADG431

IN

V

IN

V

OUT

3V

ADG432

t

Test Circuit 4. Switching Times

3V

V

IN

0V

V

OUT1

V

V

OUT1

OUT2

0V

90%

0V

R

C

L1

V

C

L2

35pF

OUT2

300V

D2

R

L2

300V

L1

35pF

Test Circuit 5. Break-Before-Make Time Delay

50% 50%

50% 50%

90% 90%

ON

t

OFF

50% 50%

90%

t

D

Test Circuit 3. On Leakage

90%

90%

t

D

+15V +5V

V

DDVL

C

L

10nF

V

OUT

R

S

V

S

SD

IN

GND

V

SS

–15V

3V

V

IN

V

OUT

Q

INJ

= CL 3 DV

OUT

DV

OUT

Test Circuit 6. Charge Injection

REV. B –7–

ADG431/ADG432/ADG433

SD

+15V +5V

0.1mF 0.1mF

V

DDVL

V

S

GND

V

SS

50V

NC

0.1mF
–15V

V

IN1

V

IN2

S

D

R

L

50V

V

OUT

CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG VS/V

OUT

+15V +5V

0.1mF 0.1mF

V

DDVL

SD

V

S

IN

V

IN

V

GND

SS

R
50V

V

OUT

L

0.005 (0.13) MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.1mF
–15V

Test Circuit 7. Off Isolation

16-Lead Cerdip

(Q-16)

0.080 (2.03) MAX

16

1

0.840 (21.34) MAX

0.023 (0.58)

0.014 (0.36)

PIN 1

0.100

(2.54)

BSC

9

8

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

15°

0.008 (0.20)

0°

Test Circuit 8. Channel-to-Channel Crosstalk

16-Lead SOIC

(R-16A)

0.3937 (10.00)

0.3859 (9.80)

PLANE

0.0500
(1.27)

16 9

PIN 1

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.2440 (6.20)

81

0.2284 (5.80)

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88
08

0.0500 (1.27)

0.0160 (0.41)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

C1826b–0–11/98

x 458

16-Lead Plastic DIP (Narrow)

(N-16)

0.840 (21.34)

0.745 (18.92)

16

18

PIN 1

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

SEATING
PLANE

0.325 (8.26)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

PRINTED IN U.S.A.

REV. B–8–