Page 1
LC2MOS Latchable 4-/8-Channel
ADG428
DECODERS/DRIVERS
LATCHES
WR
S1
S8
RS
D
A2 A1 A0 EN
DA
S1A
S4A
ADG429
DECODERS/DRIVERS
A1 A0 EN
DB
S1B
S4B
LATCHES
WR
RS
a
FEATURES
44 V Supply Maximum Ratings
V
to VDD Analog Signal Range
SS
Low On Resistance (60 ⍀ typ)
Low Power Consumption (1.6 mW max)
Low Charge Injection (<4 pC typ)
Fast Switching
Break-Before-Make Switching Action
Plug-In Replacement for DG428/DG429
APPLICATIONS
Automatic Test Equipment
Data Acquisition Systems
Communication Systems
Avionics and Military Systems
Microprocessor Controlled Analog Systems
Medical Instrumentation
High Performance Analog Multiplexers
ADG428/ADG429
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG428 and ADG429 are monolithic CMOS analog
multiplexers comprising eight single channels and four differential channels respectively. On-chip address and control latches
facilitate microprocessor interfacing. The ADG428 switches one
of eight inputs to a common output as determined by the 3-bit
binary address lines A0, A1 and A2. The ADG429 switches one
of four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched OFF. All the control
inputs, address and enable inputs are TTL compatible over the
full specified operating temperature range. This makes the part
suitable for bus-controlled systems such as data acquisition systems, process controls, avionics and ATEs because the TTLcompatible address latches simplify the digital interface design
and reduce the board space required.
2
The ADG428/ADG429 are designed on an enhanced LC
MOS
process that provides low power dissipation yet gives high switching
speed and low on resistance. Each channel conducts equally well
in both directions when ON and has an input signal range that
extends to the supplies. In the OFF condition, signal levels up to
the supplies are blocked. All channels exhibit break-before-make
switching action, preventing momentary shorting when switching
channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
The ADG428/ADG429 are improved replacements for the
DG428/DG429 Analog Multiplexers.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG428/ADG429 are fabricated on an enhanced
2
MOS process, giving an increased signal range that ex-
LC
tends to the supply rails.
2. Low Power Dissipation
3. Low R
ON
4. Single/Dual Supply Operation
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG428/ADG429 can be operated from a single rail power
supply. The parts are fully specified with a single +12 V
power supply and will remain functional with single supplies
as low as +5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
ADG428/ADG429–SPECIFICATIONS
1
DUAL SUPPLY
Parameter +25ⴗC +85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
R
ON
∆R
ON
LEAKAGE CURRENTS
Source OFF Leakage I
Drain OFF Leakage I
ADG428 ±0.07 ±0.7 ±0.07 ±0.7 nA typ Test Circuit 3
ADG429 ±0.05 ±0.5 ±0.05 ±0.5 nA typ
Channel ON Leakage I
ADG428 ±1 ±100 ±1 ±100 nA max Test Circuit 4
ADG429 ±1 ±50 ±1 ±50 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
CIN, Digital Input Capacitance 8 8 pF typ f = 1 MHz
DYNAMIC CHARACTERISTICS
t
TRANSITION
t
OPEN
t
ON
t
OFF
, Write Pulsewidth 100 100 ns min
t
W
, Address, Enable Setup Time 100 100 ns min
t
S
, Address, Enable Hold Time 10 10 ns min
t
H
t
RS
Charge Injection 4 4 pC typ V
OFF Isolation –75 –75 dB typ R
Channel-to-Channel Crosstalk 85 85 dB typ R
C
S
C
D
ADG428 40 40 pF typ
ADG429 20 20 pF typ
C
D
ADG428 54 54 pF typ
ADG429 34 34 pF typ
POWER REQUIREMENTS V
I
DD
I
SS
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
INH
(EN, WR) 115 115 ns typ R
(EN, RS) 105 105 ns typ R
, Reset Pulsewidth 100 100 ns min VS = +5 V
(OFF) 11 11 pF typ f = 1 MHz
(OFF) f = 1 MHz
, CS (ON) f = 1 MHz
(VDD = +15 V, VSS = –15 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
B Version T Version
–40ⴗC to –55ⴗC to
SS
to V
DD
VSS to VDDV
60 60 Ω typ VD = ±10 V, I
100 125 100 125 Ω max
10 10 % max –10 V < VS < 10 V, IS = –1 mA
(OFF) ±0.03 ±0.3 ±0.03 ±0.3 nA typ VD = ±10 V, V
S
±0.5 ±50 ±0.5 ±50 nA max Test Circuit 2
(OFF) V
D
= ±10 V, V
D
±1 ±100 ±1 ±100 nA max
±1 ±50 ±1 ±50 nA max
, IS (ON) VS = V
D
INH
INL
±0.1 ±1 ±0.1 ±1 µA max V
2
110 110 ns typ R
250 300 250 300 ns max V
2.4 2.4 V min
0.8 0.8 V max
= 0 or V
IN
= 1 MΩ, C
L
= ±10 V, V
S1
Test Circuit 5
10 10 ns min R
150 225 150 225 ns max V
150 300 150 300 ns max V
= 1 kΩ, C
L
= +5 V; Test Circuit 6
V
S
= 1 kΩ, C
L
= +5 V; Test Circuit 7
S
= 1 kΩ, C
L
= +5 V; Test Circuit 7
S
= 0 V, R
S
Test Circuit 10
= 1 kΩ, C
L
–60 –60 dB min V
= 7 V rms, VEN = 0 V; Test Circuit 11
S
= 1 kΩ, C
L
Test Circuit 12
= 0 V, VEN = 0 V
IN
20 20 µA typ
100 100 µA max
0.001 0.001 µA typ
55µA max
= –1 mA
S
= ⫿10 V;
S
= ⫿10 V;
S
= ±10 V;
D
DD
= 35 pF;
L
= ⫿10 V;
S8
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 15 pF, f = 100 kHz;
L
= 15 pF, f = 100 kHz;
L
= 10 nF;
L
REV. C–2–
Page 3
ADG428/ADG429
1
SINGLE SUPPLY
Parameter +25ⴗC +85ⴗC +25ⴗC +125ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V
R
ON
∆R
ON
LEAKAGE CURRENTS
Source OFF Leakage I
Drain OFF Leakage I
ADG428 ±0.015 ±0.015 nA typ Test Circuit 3
ADG429 ±0.008 ±0.008 nA typ
Channel ON Leakage I
ADG428 ±0.02 ±0.02 nA typ Test Circuit 4
ADG429 ±0.01 ±0.01 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
CIN, Digital Input Capacitance 8 8 pF typ f = 1 MHz
DYNAMIC CHARACTERISTICS
t
TRANSITION
t
OPEN
t
ON
t
OFF
, Write Pulsewidth 100 100 ns min
t
W
, Address, Enable Setup Time 100 100 ns min
t
S
, Address, Enable Hold Time 10 10 ns min
t
H
t
RS
Charge Injection 4 4 pC typ V
OFF Isolation –75 –75 dB typ R
Channel-to-Channel Crosstalk 85 85 dB typ R
C
S
C
D
ADG428 40 40 pF typ
ADG429 20 20 pF typ
C
D
ADG428 54 54 pF typ
ADG429 34 34 pF typ
POWER REQUIREMENTS V
I
DD
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
INH
(EN, WR) 200 200 ns typ R
(EN, RS) 80 80 ns typ R
, Reset Pulsewidth 100 100 ns min VS = +5 V
(OFF) 11 11 pF typ f = 1 MHz
(OFF) f = 1 MHz
, CS (ON) f = 1 MHz
(VDD = +12 V, VSS = 0 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
B Version T Version
–40ⴗC to –55ⴗC to
DD
0 to V
90 90 Ω typ V
DD
V
= +10 V, I
D
= –500 µA
S
200 200 Ω max
10 10 % max 0 V < VS < 10 V, IS = –1 mA
(OFF) ±0.005 ±0.005 nA typ V
S
= 10 V/0 V, VS = 0 V/10 V;
D
±0.5 ±50 ±0.5 ±50 nA max Test Circuit 2
(OFF) VD = 10 V/0 V, VS = 0 V/10 V;
D
±1 ±100 ±1 ±100 nA max
±1 ±50 ±1 ±50 nA max
, IS (ON) VS = VD = 10 V/0 V;
D
±1 ±100 ±1 ±100 nA max
±1 ±50 ±1 ±50 nA max
INH
INL
2
250 250 ns typ R
350 450 350 450 ns max V
2.4 2.4 V min
0.8 0.8 V max
±1 ±1 µA max V
= 0 or V
IN
= 1 MΩ, C
L
= 10 V/0 V, VS8 = 0 V/10 V;
S1
DD
= 35 pF;
L
Test Circuit 5
25 10 25 10 ns min R
300 400 300 400 ns max V
300 400 300 400 ns max V
= 1 kΩ, C
L
= +5 V; Test Circuit 6
V
S
= 1 kΩ, C
L
= +5 V; Test Circuit 7
S
= 1 kΩ, C
L
= +5 V; Test Circuit 7
S
= 6 V, R
S
= 35 pF;
L
= 35 pF;
L
= 35 pF;
L
= 0 Ω, C
S
= 10 nF;
L
Test Circuit 10
–60 –60 dB min V
= 1 kΩ, C
L
= 7 V rms, VEN = 0 V; Test Circuit 11
S
= 1 kΩ, C
L
= 15 pF, f = 100 kHz;
L
= 15 pF, f = 100 kHz;
L
Test Circuit 12
= 0 V, VEN = 0 V
IN
20 20 µA typ
100 100 µA max
REV. C –3–
Page 4
ADG428/ADG429
WARNING!
ESD SENSITIVE DEVICE
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG428
D
S4
WR
A0
EN
V
SS
S3
S2
S1
S8
S7
RS
A1
A2
GND
S6
S5
V
DD
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1
S2
S3
A2
GND
V
DD
S5
S6
ADG428
A0WRNCRSA1
S4
D
NC
S8
S7
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG429
DA
S4A
WR
A0
EN
V
SS
S3A
S2A
S1A
DB
S4B
RS
A1
GND
V
DD
S3B
S2B
S1B
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1A
S2A
S3A
GND
V
DD
S1B
S2B
S3B
ADG429
A0WRNCRSA1
S4A
DANCDB
S4B
ABSOLUTE MAXIMUM RATINGS
(T
= +25°C unless otherwise noted.)
A
1
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
V
SS
Analog, Digital Inputs
2
. . . . . . . . . . VSS – 2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73°C/W
θ
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
θ
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, WR, RS , S or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
ADG428 PIN CONFIGURATIONS
DIP/SOIC PLCC
ADG429 PIN CONFIGURATIONS
DIP PLCC
ORDERING GUIDE
Model
1
Temperature Range Package Options
2
ADG428BN –40°C to +85°C N-18
ADG428BP –40°C to +85°C P-20A
ADG428BR –40°C to +85°C R-18
ADG428TQ –55°C to +125°CQ-18
ADG429BN –40°C to +85°C N-18
ADG429BP –40°C to +85°C P-20A
ADG429TQ –55°C to +125°CQ-18
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
R = Small Outline IC (SOIC).
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
Page 5
ADG428/ADG429
TERMINOLOGY
V
DD
V
SS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
GND Ground (0 V) reference.
R
∆R
ON
ON
Ohmic resistance between D and S.
Difference between the RON of any two
channels.
I
(OFF) Source leakage current when the switch is off.
S
I
(OFF) Drain leakage current when the switch is off.
D
I
, IS (ON) Channel leakage current when the switch is
D
on.
V
(VS) Analog voltage on terminals D, S.
D
C
(OFF) Channel input capacitance for “OFF”
S
condition.
C
(OFF) Channel output capacitance for “OFF”
D
condition.
C
, CS (ON) “ON” switch capacitance.
D
C
IN
t
(EN) Delay time between the 50% and 90% points
ON
Digital input capacitance.
of the digital input and switch “ON”
condition.
t
(EN) Delay time between the 50% and 90% points
OFF
of the digital input and switch “OFF”
condition.
t
TRANSITlON
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
t
OPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
V
V
I
INL
INH
INL
(I
) Input current of the digital input.
INH
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Crosstalk A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” channel.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
I
DD
I
SS
Positive supply current.
Negative supply current.
ADG428 Truth Table
A2 A1 A0 EN WR RS ON SWITCH
Latching
XXXX
g
1 Maintains Previous
Switch Condition
Reset
XXXXX0 NONE
(Latches Cleared)
Transparent Operation
X X X 0 0 1 NONE
000101 1
001101 2
010101 3
011101 4
100101 5
101101 6
110101 7
111101 8
ADG429 Truth Table
A1 A0 EN WR RS ON SWITCH PAIR
Latching
XXX
g
1 Maintains Previous
Switch Condition
Reset
XXXX0 NONE
(Latches Cleared)
Transparent Operation
X X 0 0 1 NONE
001011
011012
101013
111014
REV. C
–5–
Page 6
ADG428/ADG429
50% 50%
3V
RS
0V
V
O
SWITCH
OUTPUT
0V
0.8V
O
t
RS
t
OFF
(RS)
VD (VS) – Volts
600
550
100
01536912
400
250
200
150
500
450
300
350
R
ON
– V
50
0
TA = +258C
VDD = +12V
V
SS
= 0V
VDD = +10V
V
SS
= 0V
VDD = +5V
V
SS
= 0V
VDD = +15V
V
SS
= 0V
VD (VS) – Volts
160
60
0152
R
ON
– V
46810
150
120
90
80
70
140
130
110
100
VDD = +12V
V
SS
= 0V
+1258C
+258C
+858C
TIMING DIAGRAMS
3V
WR
A0, A1, (A2)
EN
0V
3V
0V
50% 50%
t
W
t
S t
2V
H
0.8V
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Typical Characteristics
140
130
120
110
100
– V
90
ON
R
80
VDD = +15V
V
70
60
50
40
–15 15–10
SS
= –15V
VDD = +12V
V
= –12V
SS
–5 0 5 10
VD (VS) – Volts
VDD = +5V
V
= –5V
SS
TA = +258C
VDD = +10V
= –10V
V
SS
Figure 2.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff
OFF
, (RS).
Time, t
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tr = tf = 20 ns.
Figure 3. RON as a Function of VD (VS): Dual Supply
Voltage
80
75
70
65
– V
60
ON
R
55
50
45
40
–15 15–10
Figure 4. RON as a Function of VD (VS) for Different
Temperatures
+1258C
+858C
+258C
–5
VD (VS) – Volts
VDD = +15V
V
= –15V
SS
0510
Figure 5. RON as a Function of VD (VS): Single Supply
Voltage
Figure 6. RON as a Function of VD (VS) for Different
Temperatures
–6–
REV. C
Page 7
6000
VDD = +15V
V
SS
= –15V
SWITCHING FREQUENCY – Hz
1000
100
0.1
10 10M100
I
SS
– mA
1k 10k 100k 1M
10
1
EN = 2.4V
EN = 0V
VIN – Volts
200
40
t – ns
180
120
100
80
60
160
140
113357911
t
OFF
(EN)
t
TRANSITION
tON (EN)
VDD = +12V
V
SS
= 0V
V
SUPPLY
– Volts
500
200
0
5156
t – ns
7 8 9 10 11 12 13 14
450
250
150
50
350
300
100
400
VIN = +5V
tON (EN)
t
TRANSITION
t
OFF
(EN)
VDD = +15V
5500
V
= –15V
SS
5000
4500
4000
3500
3000
– mA
DD
I
2500
2000
1500
1000
500
0
10
1k 10k 100k 1M
SWITCHING FREQUENCY – Hz
EN = 2.4V
EN = 0V
10M100
Figure 7. Positive Supply Current vs. Switching Frequency
130
VDD = +15V
V
= –15V
SS
120
110
100
t
TRANSITION
tON (EN)
ADG428/ADG429
Figure 10. Negative Supply Current vs. Switching
Frequency
90
t – ns
80
70
t
60
50
1153 5 7 9 11 13
OFF
Figure 8. Switching Time vs. VIN (Bipolar Supply)
300
275
250
225
200
175
150
t – ns
125
100
75
REV. C
50
25
0
65 61567 69 611 613
V
Figure 9. Switching Time vs. Bipolar Supply
(EN)
VIN – Volts
t
SUPPLY
t
(EN)
OFF
– Volts
Figure 11. Switching Time vs. VIN (Single Supply)
VIN = +5V
tON (EN)
TRANSITION
Figure 12. Switching Time vs. Single Supply
–7–
Page 8
ADG428/ADG429
FREQUENCY – Hz
110
105
60
1k 10k 100k
90
75
70
65
100
95
80
85
CROSSTALK – dB
55
50
VDD = +15V
V
SS
= –15V
1M 10M
VD (VS) – Volts
0.04
–0.04
LEAKAGE CURRENT – nA
0.03
0
–0.01
–0.02
–0.03
0.02
0.01
012246810
VDD = +12V
V
SS
= 0V
T
A
= +258C
ID (OFF)
IS (OFF)
ID (ON)
100
95
90
85
80
75
70
65
60
OFF ISOLATION – dB
55
50
45
40
100 10M1k 10k 100k 1M
FREQUENCY – Hz
Figure 13. OFF Isolation vs. Frequency
0.2
VDD = +15V
V
= –15V
SS
= +258C
T
A
0.1
ID (ON)
VDD = +15V
V
= –15V
SS
Figure 15. Crosstalk vs. Frequency
0
LEAKAGE CURRENT – nA
–0.1
–15 15–10
ID (OFF)
–5 0 5 10
VD (VS) – Volts
Figure 14. Leakage Currents as a Function of VD (VS)
IS (OFF)
–8–
Figure 16. Leakage Currents as a Function of VD (VS)
REV. C
Page 9
TEST CIRCUITS
S1
D
S2
S8
A
EN
GND
V
DD
V
SS
V
DD
V
SS
+0.8V
V
D
V
S
ID (OFF)
Test Circuit 1. On Resistance
IS (OFF)
V
S
I
DS
V1
SD
V
S
RON = V1/I
DS
V
DD
V
DD
S1
A
S2
S8
V
D
GND
ADG428/ADG429
Test Circuit 3. ID (OFF)
V
SS
V
SS
D
+0.8V
EN
V
S
V
V
DD
SS
V
V
DD
SS
S1
S8
GND
EN
D
2.4V
ID (ON)
A
V
D
Test Circuit 4. ID (ON)
V
V
DD
SS
V
V
DD
SS
A0
A1
A2
ADG428*
EN
RS
GND
TRANSITION
V
DD
V
DD
A0
A1
A2
WR
V
V
S2–S7
SS
SS
S2–S7
S1
S8
D
S1
OUTPUT
1MV
V
S1
V
S8
35pF
V
S
ENABLE
DRIVE – V
OUTPUT
ADDRESS
DRIVE – V
Test Circuit 2. IS (OFF)
3V
IN
IN
0V
3V
0V
t
TRANSITION
50% 50%
90%
t
TRANSITION
90%
V
50V
IN
2.4V
*SIMILAR CONNECTION FOR ADG429
Test Circuit 5. Switching Time of Multiplexer, t
V
50V
IN
ADG428*
WR
S8
D
OUTPUT
1kV
35pF
2.4V
REV. C
OUTPUT
80%
t
OPEN
Test Circuit 6. Break-Before-Make Delay, t
80%
*SIMILAR CONNECTION FOR ADG429
–9–
EN
RS
GND
OPEN
Page 10
ADG428/ADG429
3V
ENABLE DRIVE
–V
IN
0V
V
O
OUTPUT (VO)
0V
3V
WR
0V
V
O
OUTPUT
0V
50% 50%
t
(EN) t
ON
0.9V
O
Test Circuit 7. Enable Delay, tON (EN), t
50%
t
(WR)
ON
0.9V
OFF
O
(EN)
0.2V
V
V
DD
SS
V
V
DD
SS
A0
A1
A2
S2–S8
V
S1
S
ADG428*
2.4V
RS
EN
V
O
50V
IN
*SIMILAR CONNECTION FOR ADG429
2.4V
VRSV
OFF
(EN)
WR
GND
V
V
A0
A1
A2
EN
RS
WR
DD
DD
ADG428*
GND
WR
V
SS
V
SS
S2–S8
D
S1
D
OUTPUT
1kV
OUTPUT
V
S
1kV
35pF
35pF
RS
OUTPUT
*SIMILAR CONNECTION FOR ADG429
Test Circuit 8. Write Turn-On Time, tON
3V
50%
0V
t
(RS)
OFF
V
O
0.8V
O
0V
Test Circuit 9. Reset Turn-Off Time, t
(WR
)
V
V
DD
SS
V
V
DD
ADG428*
GND
WR
SS
S2–S8
A0
A1
A2
2.4V
EN
RS
V
IN
*SIMILAR CONNECTION FOR ADG429
(RS)
OFF
S1
D
V
OUTPUT
1kV
S
35pF
–10–
REV. C
Page 11
ADG428/ADG429
V
DD
V
SS
V
DD
V
SS
2.4V
ADG428
A0
A1
A2
D
RS
EN
1kV
S1
V
OUT
S2
S8
GND
WR
1kV
V
S
V
V
DD
SS
V
3V
EN
DV
V
OUT
Q
= CL 3 DV
INJ
OUT
OUT
R
S
V
S
A0
A1
A2
S
EN
DD
ADG428*
V
SS
2.4V
RS
D
C
L
10nF
V
OUT
V
V
DD
SS
V
V
DD
ADG428
GND
SS
WR
A0
A1
A2
S1
V
S
S8
EN
0V
Test Circuit 11. OFF Isolation
RS
V
IN
*SIMILAR CONNECTION FOR ADG429
GND
WR
Test Circuit 10. Charge Injection
2.4V
1kV
V
OUT
D
Test Circuit 12. Crosstalk
–11–
REV. C
Page 12
ADG428/ADG429
)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25)
x 45°
18 10
91
0.4625 (11.75)
0.4469 (11.35)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.048 (1.21)
0.042 (1.07)
0.175 (4.45)
0.120 (3.05)
0.020 (0.508)
0.015 (0.381)
PLCC (P-20A)
0.180 (4.57)
0.050
(1.27)
BSC
0.165 (4.19)
0.110 (2.79)
0.085 (2.16)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
3
4
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
8
9
0.356 (9.04)
0.350 (8.89)
0.395 (10.02)
0.385 (9.78)
0.056 (1.42)
0.042 (1.07)
19
18
14
13
SQ
SQ
Plastic DIP (N-18)
0.910 (23.12
0.890 (22.61)
18
19
PIN 1
0.105 (2.67)
0.095 (2.42)
10
0.065 (1.66)
0.045 (1.15)
0.260 (6.61)
0.240 (6.10)
0.180
(4.48)
MAX
SEATING
PLANE
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.306 (7.78)
0.294 (7.47)
0.120 (0.305)
0.008 (0.203)
0.330 (8.38)
0.290 (7.37)
0.140 (3.56)
0.120 (3.05)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
18
1
0.022 (0.58)
0.014 (0.36)
PIN 1
0.840 (21.34) MAX
0.100
(2.54)
BSC
Cerdip (Q-18)
10
0.310 (7.87)
0.220 (5.59)
9
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
SOIC (R-18)
0.320 (8.13)
0.290 (7.37)
C1825c–0–5/99
0.015 (0.381)
0.008 (0.204)
–12–
PRINTED IN U.S.A.
REV. C
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