Datasheet ADG413BR, ADG413BN, ADG412TQ, ADG412BR, ADG412BN Datasheet (Analog Devices)

LC2MOS

a

FEATURES
44 V Supply Maximum Ratings
615 V Analog Signal Range
Low On Resistance (<35 V)
Ultralow Power Dissipation (35 mW)
Fast Switching Times

t

<175 ns

ON

t

<145 ns

OFF

TTL/CMOS Compatible
Plug-In Replacement for DG411/DG412/DG413

APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems

GENERAL DESCRIPTION

The ADG411, ADG412 and ADG413 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
low power dissipation yet gives high switching speed and low on
resistance.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa­tion making the parts ideally suited for portable and battery
powered instruments.

The ADG411, ADG412 and ADG413 contain four indepen­dent SPST switches. The ADG411 and ADG412 differ only in
that the digital control logic is inverted. The ADG411 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. The ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.

Each switch conducts equally well in both directions when ON
and each has an input signal range that extends to the supplies.
In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching ac­tion for use in multiplexer applications. Inherent in the design is
low charge injection for minimum transients when switching the
digital inputs.

2

MOS process which provides

Precision Quad SPST Switches

ADG411/ADG412/ADG413

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

ADG413

IN1

IN2

ADG412

IN3

IN4

S1

D1
S2

D2
S3

D3
S4

D4

IN1

IN2

ADG411

IN3

IN4

SWITCHES SHOWN FOR A LOGIC "1" INPUT

PRODUCT HIGHLIGHTS

1. Extended Signal Range
The ADG411, ADG412 and ADG413 are fabricated on an
enhanced LC

2

MOS, giving an increased signal range which

extends fully to the supply rails.

2. Ultralow Power Dissipation

3. Low R

ON

4. Break-Before-Make Switching
This prevents channel shorting when the switches are
configured as a multiplexer.

5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG411, ADG412 and ADG413 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.

S1

D1
S2

D2
S3

D3
S4

D4

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADG411/ADG412/ADG413–SPECIFICATIONS

1

Dual Supply

(VDD = +15 V 6 10%, VSS = –15 V 6 10%, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)

B Version T Version

–408C to –558C to

Parameter +258C +858C +258C +1258C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V
R

ON

25 25 Ω typ VD = ±8.5 V, IS = –10 mA;
35 45 35 45 Ω max VDD = +13.5 V, V

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.1 ±0.1 nA typ VD = ±15.5 V, VS = 715.5 V;

S

DD

to V

SS

VDD to VSSV

= –13.5 V

SS

= +16.5 V, VSS = –16.5 V

DD

±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.1 ±0.1 nA typ VD = ±15.5 V, VS = 715.5 V;

D

±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.1 ±0.1 nA typ VD = VS = ±15.5 V;

D

±0.4 ±10 ±0.4 ±40 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 2.4 V min

0.8 0.8 V max

Input Current

I

INL

or I

INH

0.005 0.005 µA typ VIN = V

INL

or V

INH

±0.5 ±0.5 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG413 Only) V

2

110 110 ns typ RL = 300 Ω, CL = 35 pF;

175 175 ns max V

= ±10 V; Test Circuit 4

S

100 100 ns typ RL = 300 Ω, CL = 35 pF;

145 145 ns max V

25 25 ns typ RL = 300 Ω, CL = 35 pF;

D

= ±10 V; Test Circuit 4

S

= VS2 = +10 V;

S1

Test Circuit 5

Charge Injection 5 5 pC typ V

= 0 V, RS = 0 Ω, CL = 10 nF;

S

Test Circuit 6

OFF Isolation 68 68 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 85 85 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

(OFF) 9 9 pF typ f = 1 MHz

C

S

(OFF) 9 9 pF typ f = 1 MHz

C

D

CD, CS (ON) 35 35 pF typ f = 1 MHz

POWER REQUIREMENTS V

= +16.5 V, VSS = –16.5 V

DD

Digital Inputs = 0 V or 5 V

I

DD

0.0001 0.0001 µA typ
15 1 5 µA max

I

SS

0.0001 0.0001 µA typ
15 1 5 µA max

I

L

0.0001 0.0001 µA typ
15 1 5 µA max

NOTES

1

Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. A–2–

ADG411/ADG412/ADG413

Single Supply

(VDD = +12 V 6 10%, VSS = 0 V, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)

B Version T Version

–408C to –558C to

Parameter +258C +858C +258C +1258C Units Test Conditions/Comments

ANALOG SIGNAL RANGE 0 V to V

R

ON

40 40 Ω typ 0 < VD = 8.5 V, IS = –10 mA;

DD

0 V to VDDV

80 100 80 100 Ω max VDD = +10.8 V

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.1 ±0.1 nA typ VD = 12.2/1 V, VS = 1/12.2 V;

S

= +13.2 V

DD

±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ±0.1 ±0.1 nA typ VD = 12.2/1 V, VS = 1/12.2 V;

D

±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.1 ±0.1 nA typ VD = VS = +12.2 V/+1 V;

D

±0.4 ±10 ±0.4 ±40 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 2.4 V min

0.8 0.8 V max

Input Current

I

INL

or I

INH

0.005 0.005 µA typ VIN = V

INL

or V

INH

±0.5 ±0.5 µA max

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Time Delay, t

(ADG413 Only) V

2

175 175 ns typ RL = 300 Ω, CL = 35 pF;

250 250 ns max V

= +8 V; Test Circuit 4

S

95 95 ns typ RL = 300 Ω, CL = 35 pF;

125 125 ns max V

25 25 ns typ RL = 300 Ω, CL = 35 pF;

D

= +8 V; Test Circuit 4

S

= VS2 = +10 V;

S1

Test Circuit 5

Charge Injection 25 25 pC typ V

= 0 V, RS = 0 Ω, CL = 10 nF;

S

Test Circuit 6

OFF Isolation 68 68 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 7

Channel-to-Channel Crosstalk 85 85 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

(OFF) 9 9 pF typ f = 1 MHz

C

S

(OFF) 9 9 pF typ f = 1 MHz

C

D

CD, CS (ON) 35 35 pF typ f = 1 MHz

POWER REQUIREMENTS V

= +13.2 V

DD

Digital Inputs = 0 V or 5 V

I

DD

0.0001 0.0001 µA typ
15 1 5 µA max

I

L

0.0001 0.0001 µA typ
15 1 5 µA max VL = +5.25 V

NOTES

1

Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

Truth Table (ADG411/ADG412)

ADG411 In ADG412 In Switch Condition

01ON
1 0 OFF

REV. A

Truth Table (ADG413)

Logic Switch 1, 4 Switch 2, 3

0 OFF ON
1 ON OFF

–3–

ADG411/ADG412/ADG413

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

IN1

D1
S1

V

SS

GND

S4
D4

IN4

IN2
D2
S2
V

DD

V

L

S3
D3
IN3

ADG411
ADG412
ADG413

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V

V

SS

to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

L

Analog, Digital Inputs

2

. . . . . . . . . . . VSS –2 V to VDD +2 V or

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .900 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W

θ

JA

TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 115°C/W

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 35°C/W

θ

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

ORDERING GUIDE

l

Model

Temperature Range Package Option

ADG411BN –40°C to +85° C N-16
ADG411BR –40°C to +85°C R-16A
ADG411TQ –55°C to +125°C Q-16
ADG411BRU –40°C to +85°C RU-16
ADG412BN –40 °C to +85°C N-16
ADG412BR –40°C to +85°C R-16A
ADG412TQ –55°C to +125°C Q-16
ADG413BN –40 °C to +85°C N-16
ADG413BR –40°C to +85°C R-16A

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.

2

N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); RU= Thin Shrink Small
Outline (TSSOP); Q = Cerdip.

1

30 mA, Whichever Occurs First

2

TERMINOLOGY

V

DD

V

SS

Most positive power supply potential.
Most negative power supply potential in dual

supplies. In single supply applications, it may
be connected to GND.

V

L

Logic power supply (+5 V).
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R

ON

I

(OFF) Source leakage current with the switch “OFF.”

S

I

(OFF) Drain leakage current with the switch “OFF.”

D

I

, IS (ON) Channel leakage current with the switch “ON.”

D

V

) Analog voltage on terminals D, S.

D (VS

C

(OFF) “OFF” switch source capacitance.

S

C

(OFF) “OFF” switch drain capacitance.

D

C

, CS (ON) “ON” switch capacitance.

D

t

ON

Ohmic resistance between D and S.

Delay between applying the digital control

input and the output switching on.
t

OFF

Delay between applying the digital control

input and the output switching off.
t

D

“OFF” time or “ON” time measured between

the 90% points of both switches, when switching

from one address state to another.
Crosstalk A measure of unwanted signal which is coupled

through from one channel to another as a result

of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling

through an “OFF” switch.
Charge A measure of the glitch impulse transferred

Injection from the digital input to the analog output

during switching.

PIN CONFIGURATION

(DIP/SOIC)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG411/ADG412/ADG413 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A–4–

Typical Performance Graphs

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

0.04

0.02

–0.04

–20 –10

LEAKAGE CURRENT – nA

01020

0.00

–0.02

VDD = +15V
V

SS

= –15V
TA = +258C
VL = +5V

ID (ON)

I

S

(OFF)

ID (OFF)

ADG411/ADG412/ADG413

50

40

30

– V

ON

R

20

10

VDD = +15V
V

= –15V

SS

0

–20 –10

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

VDD = +5V
V

SS

VDD = +10V
V

= –10V

SS

= –5V

01020

TA = +258C
VL = +5V

VDD = +12V
V

= –12V

SS

Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies

50

VDD = +15V
V

= –15V

SS

40

30

– V

ON

R

20

10

VL = +5V

+1258C

+858C
+258C

50

40

30

– V

ON

R

20

10

0

05

VDD = +5V
V

SS

V
V

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

= 0V

= +10V

DD

= 0V

SS

VDD = +12V
V

= 0V

SS

VDD = +15V
V

= 0V

SS

10 15 20

TA = +258C
VL = +5V

Figure 4. On Resistance as a Function of VD (VS) Single
Supply

100mA

VDD = +15V 4 SW
V

10mA

100mA

SUPPLY

I

10mA

1mA

1mA

= –15V

SS

VL = +5V

1 SW

I+, I–

I

L

Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures

Figure 3. Leakage Currents as a Function of Temperature

REV. A –5–

0

–20 –10

VD OR VS – DRAIN OR SOURCE VOLTAGE – V

10

VDD = +15V
V

= –15V

SS

VL = +5V

1

VS = 615V
V

= 615V

D

0.1

LEAKAGE CURRENT – nA

0.01

0.001
100 10M1k

ID (ON)

01020

IS (OFF)

I

(OFF)

D

10k 100k 1M

FREQUENCY – Hz

10M

100nA

10

1k 10k 100k 1M

FREQUENCY – Hz

10M100

Figure 5. Supply Current vs. Input Switching Frequency

Figure 6. Leakage Currents as a Function of VD (VS)

ADG411/ADG412/ADG413

+15V

–15V

2200pF

R

C

75V

C

C

1000pF

C

H

2200pF

V

OUT

ADG411
ADG412
ADG413

SW2

SW1

S

S

D

D

+15V +5V

–15V

AD845

+15V

–15V

V

IN

AD711

120

100

80

OFF ISOLATION – dB

60

40

100 10M1k

10k 100k 1M

FREQUENCY – Hz

Figure 7. Off Isolation vs. Frequency

110

100

90

VDD = +15V
V

= –15V

SS

VL = +5V

VDD = +15V
V

= –15V

SS

VL = +5V

APPLICATION

Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V

follows the input signal VIN. In the hold

OUT

mode, SW1 is opened and the signal is held by the hold capaci-

.

tor C

H

Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica­tions. The droop rate is further minimized by the use of a poly­styrene hold capacitor. The droop rate for the circuit shown is
typically 30 µV/µs.

A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen­tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa­tion network R

and CC. This compensation network also re-

C

duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes­tal error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.

80

CROSSTALK – dB

70

60

100 10M1k

10k 100k 1M

FREQUENCY – Hz

Figure 8. Crosstalk vs. Frequency

Figure 9. Fast, Accurate Sample-and-Hold

REV. A–6–

SD

V

S

V

D

A

I

D

(ON)

Test Circuits

V

S

I

DS

V1

SD

RON = V1/I

DS

V

S

I

(OFF)

S

A

SD

I

D

(OFF)

A

V

D

ADG411/ADG412/ADG413

Test Circuit 1. On Resistance

0.1mF 0.1mF

V

S

0.1mF 0.1mF

V

S1

V

S2

S1 D1

S2

IN1, IN2

V

IN

GND

+15V +5V

V

DDVL

V

0.1mF
–15V

IN

SS

Test Circuit 2. Off Leakage

+15V +5V

3V

V

DDVL

SD

V

GND

SS

0.1mF
–15V

R

L

300V

C

L

35pF

V

OUT

V

ADG411

IN

V

IN

V

OUT

3V

ADG412

t

Test Circuit 4. Switching Times

3V

V

IN

0V

V

OUT1

V

V

OUT1

OUT2

0V

90%

0V

R

C

L1

V

C

L2

35pF

OUT2

300V

D2

R

L2

300V

L1

35pF

Test Circuit 5. Break-Before-Make Time Delay

50% 50%

50% 50%

90% 90%

ON

t

OFF

50% 50%

90%

t

D

Test Circuit 3. On Leakage

90%

90%

t

D

+15V +5V

V

DDVL

C

L

10nF

V

OUT

R

S

V

S

SD

IN

GND

V

SS

–15V

Test Circuit 6. Charge Injection

REV. A –7–

3V

V

IN

V

OUT

Q

INJ

= CL 3 DV

OUT

DV

OUT

ADG411/ADG412/ADG413

V

S

0.005 (0.13) MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

+15V +5V

0.1mF 0.1mF

V

DDVL

SD

IN

V

IN

GND

0.1mF
–15V

Test Circuit 7. Off Isolation

16-Lead Cerdip

(Q-16)

0.080 (2.03) MAX

16

1

0.840 (21.34) MAX

0.023 (0.58)

0.014 (0.36)

PIN 1

0.100

(2.54)

BSC

9

8

0.070 (1.78)

0.030 (0.76)

V

SS

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

0.150
(3.81)
MIN

V

OUT

R

L

50V

V

S

V

OUT

Test Circuit 8. Channel-to-Channel Crosstalk

MECHANICAL INFORMATION

Dimensions are shown in inches and (mm).

0.1574 (4.00)

0.1497 (3.80)

0.320 (8.13)

0.290 (7.37)

0.0098 (0.25)

0.0040 (0.10)

15°

0.015 (0.38)

0.008 (0.20)

0°

SEATING

PLANE

0.1mF 0.1mF

V

IN1

R

L

50V

0.3937 (10.00)

0.3859 (9.80)

16 9

PIN 1

0.0500
(1.27)

BSC

+15V +5V

V

DDVL

SD

DS

V

GND

SS

0.1mF
–15V

16-Lead SOIC

(R-16A)

0.2440 (6.20)

81

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

50V

V

IN2

NC

CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG V

0.0196 (0.50)

0.0099 (0.25)

88
08

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

C1748a–3–2/98

S/VOUT

x 458

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

16-Lead Plastic DIP (Narrow)

(N-16)

0.840 (21.34)

0.745 (18.92)

16

18

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.26)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.177 (4.50)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.201 (5.10)

0.193 (4.90)

16

0.169 (4.30)

1

PIN 1

0.0256
(0.65)

BSC

16-Lead TSSOP

(RU-16)

9

0.256 (6.50)

8

0.0433
(1.10)

0.0118 (0.30)

0.0075 (0.19)

MAX

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8°
0°

0.028 (0.70)

0.020 (0.50)

PRINTED IN U.S.A.

REV. A–8–