Page 1
FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG411
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG412
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG413
SWITCHES SHOWN FOR A LOGIC "1" INPUT
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC2MOS
Precision Quad SPST Switches
ADG411/ADG412/ADG413
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
FEATURES
44 V Supply Maximum Ratings
615 V Analog Signal Range
Low On Resistance (<35 V)
Ultralow Power Dissipation (35 mW)
Fast Switching Times
t
ON
<175 ns
t
OFF
<145 ns
TTL/CMOS Compatible
Plug-In Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG411, ADG412 and ADG413 are fabricated on an
enhanced LC
2
MOS, giving an increased signal range which
extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low R
ON
4. Break-Before-Make Switching
This prevents channel shorting when the switches are
configured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG411, ADG412 and ADG413 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
GENERAL DESCRIPTION
The ADG411, ADG412 and ADG413 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
2
MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery
powered instruments.
The ADG411, ADG412 and ADG413 contain four independent SPST switches. The ADG411 and ADG412 differ only in
that the digital control logic is inverted. The ADG411 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. The ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and each has an input signal range that extends to the supplies.
In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is
low charge injection for minimum transients when switching the
digital inputs.
Page 2
ADG411/ADG412/ADG413–SPECIFICATIONS
1
Dual Supply
B Version T Version
–408C to –558C to
Parameter +258C +858C +258C +1258C Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
DD
to V
SS
VDD to VSSV
R
ON
25 25 Ω typ VD = ±8.5 V, IS = –10 mA;
35 45 35 45 Ω max VDD = +13.5 V, V
SS
= –13.5 V
LEAKAGE CURRENTS V
DD
= +16.5 V, VSS = –16.5 V
Source OFF Leakage I
S
(OFF) ±0.1 ±0.1 nA typ VD = ±15.5 V, VS = 715.5 V;
±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.1 ±0.1 nA typ VD = ±15.5 V, VS = 715.5 V;
±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2
Channel ON Leakage I
D
, IS (ON) ±0.1 ±0.1 nA typ VD = VS = ±15.5 V;
±0.4 ±10 ±0.4 ±40 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
INL
or I
INH
0.005 0.005 µA typ VIN = V
INL
or V
INH
±0.5 ±0.5 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
110 110 ns typ RL = 300 Ω, CL = 35 pF;
175 175 ns max V
S
= ±10 V; Test Circuit 4
t
OFF
100 100 ns typ RL = 300 Ω, CL = 35 pF;
145 145 ns max V
S
= ±10 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
25 25 ns typ RL = 300 Ω, CL = 35 pF;
(ADG413 Only) V
S1
= VS2 = +10 V;
Test Circuit 5
Charge Injection 5 5 pC typ V
S
= 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
OFF Isolation 68 68 dB typ R
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk 85 85 dB typ R
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF) 9 9 pF typ f = 1 MHz
C
D
(OFF) 9 9 pF typ f = 1 MHz
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= +16.5 V, VSS = –16.5 V
Digital Inputs = 0 V or 5 V
I
DD
0.0001 0.0001 µA typ
15 1 5 µA max
I
SS
0.0001 0.0001 µA typ
15 1 5 µA max
I
L
0.0001 0.0001 µA typ
15 1 5 µA max
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. A–2–
(VDD = +15 V 6 10%, VSS = –15 V 6 10%, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)
Page 3
Truth Table (ADG411/ADG412)
ADG411 In ADG412 In Switch Condition
01ON
1 0 OFF
ADG411/ADG412/ADG413
REV. A
–3–
Single Supply
B Version T Version
–408C to –558C to
Parameter +258C +858C +258C +1258C Units Test Conditions/Comments
ANALOG SIGNAL RANGE 0 V to V
DD
0 V to VDDV
R
ON
40 40 Ω typ 0 < VD = 8.5 V, IS = –10 mA;
80 100 80 100 Ω max VDD = +10.8 V
LEAKAGE CURRENTS V
DD
= +13.2 V
Source OFF Leakage I
S
(OFF) ±0.1 ±0.1 nA typ VD = 12.2/1 V, VS = 1/12.2 V;
±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.1 ±0.1 nA typ VD = 12.2/1 V, VS = 1/12.2 V;
±0.25 ± 5 ±0.25 ±20 nA max Test Circuit 2
Channel ON Leakage I
D
, IS (ON) ±0.1 ±0.1 nA typ VD = VS = +12.2 V/+1 V;
±0.4 ±10 ±0.4 ±40 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
INL
or I
INH
0.005 0.005 µA typ VIN = V
INL
or V
INH
±0.5 ±0.5 µA max
DYNAMIC CHARACTERISTICS
2
t
ON
175 175 ns typ RL = 300 Ω, CL = 35 pF;
250 250 ns max V
S
= +8 V; Test Circuit 4
t
OFF
95 95 ns typ RL = 300 Ω, CL = 35 pF;
125 125 ns max V
S
= +8 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
25 25 ns typ RL = 300 Ω, CL = 35 pF;
(ADG413 Only) V
S1
= VS2 = +10 V;
Test Circuit 5
Charge Injection 25 25 pC typ V
S
= 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
OFF Isolation 68 68 dB typ R
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk 85 85 dB typ R
L
= 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF) 9 9 pF typ f = 1 MHz
C
D
(OFF) 9 9 pF typ f = 1 MHz
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= +13.2 V
Digital Inputs = 0 V or 5 V
I
DD
0.0001 0.0001 µA typ
15 1 5 µA max
I
L
0.0001 0.0001 µA typ
15 1 5 µA max VL = +5.25 V
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +12 V 6 10%, VSS = 0 V, VL = +5 V 6 10%, GND = 0 V, unless otherwise noted)
Truth Table (ADG413)
Logic Switch 1, 4 Switch 2, 3
0 OFF ON
1 ON OFF
Page 4
ADG411/ADG412/ADG413
REV. A–4–
ORDERING GUIDE
Model
l
Temperature Range Package Option
2
ADG411BN –40 °C to +85°C N-16
ADG411BR –40°C to +85°C R-16A
ADG411TQ –55°C to +125°C Q-16
ADG411BRU –40°C to +85°C RU-16
ADG412BN –40 °C to +85°C N-16
ADG412BR –40°C to +85°C R-16A
ADG412TQ –55°C to +125°C Q-16
ADG413BN –40 °C to +85°C N-16
ADG413BR –40°C to +85°C R-16A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); RU= Thin Shrink Small
Outline (TSSOP); Q = Cerdip.
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog, Digital Inputs
2
. . . . . . . . . . . VSS –2 V to VDD +2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .900 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W
TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 115°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 35°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to GND.
V
L
Logic power supply (+5 V).
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
Ohmic resistance between D and S.
I
S
(OFF) Source leakage current with the switch “OFF.”
I
D
(OFF) Drain leakage current with the switch “OFF.”
I
D
, IS (ON) Channel leakage current with the switch “ON.”
V
D (VS
) Analog voltage on terminals D, S.
C
S
(OFF) “OFF” switch source capacitance.
C
D
(OFF) “OFF” switch drain capacitance.
C
D
, CS (ON) “ON” switch capacitance.
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
D
“OFF” time or “ON” time measured between
the 90% points of both switches, when switching
from one address state to another.
Crosstalk A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” switch.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
PIN CONFIGURATION
(DIP/SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN2
D2
S2
V
DD
V
L
S3
D3
IN3
ADG411
ADG412
ADG413
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG411/ADG412/ADG413 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Page 5
ADG411/ADG412/ADG413
REV. A –5–
Typical Performance Graphs
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
50
40
10
–20 –10
R
ON
– V
01020
30
20
TA = +258C
VL = +5V
0
VDD = +15V
V
SS
= –15V
VDD = +10V
V
SS
= –10V
VDD = +12V
V
SS
= –12V
VDD = +5V
V
SS
= –5V
Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
50
40
10
–20 –10
R
ON
– V
01020
30
20
0
VDD = +15V
V
SS
= –15V
VL = +5V
+1258C
+858C
+258C
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures
FREQUENCY – Hz
10
0.001
100 10M1k
LEAKAGE CURRENT – nA
10k 100k 1M
1
0.1
0.01
VDD = +15V
V
SS
= –15V
VL = +5V
10M
VS = 615V
V
D
= 615V
IS (OFF)
I
D
(OFF)
ID (ON)
Figure 3. Leakage Currents as a Function of Temperature
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
50
40
10
05
R
ON
– V
10 15 20
30
20
TA = +258C
VL = +5V
0
VDD = +15V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V
VDD = +12V
V
SS
= 0V
VDD = +5V
V
SS
= 0V
Figure 4. On Resistance as a Function of VD (VS) Single
Supply
FREQUENCY – Hz
100mA
100nA
10
10M100
I
SUPPLY
1k 10k 100k 1M
10mA
1mA
100mA
10mA
1mA
VDD = +15V 4 SW
V
SS
= –15V
VL = +5V
1 SW
I+, I–
I
L
Figure 5. Supply Current vs. Input Switching Frequency
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
0.04
0.02
–0.04
–20 –10
LEAKAGE CURRENT – nA
01020
0.00
–0.02
VDD = +15V
V
SS
= –15V
TA = +258C
VL = +5V
ID (ON)
I
S
(OFF)
ID (OFF)
Figure 6. Leakage Currents as a Function of VD (VS)
Page 6
ADG411/ADG412/ADG413
REV. A–6–
FREQUENCY – Hz
120
100
40
100 10M1k
OFF ISOLATION – dB
10k 100k 1M
80
60
VDD = +15V
V
SS
= –15V
VL = +5V
Figure 7. Off Isolation vs. Frequency
FREQUENCY – Hz
110
100
60
100 10M1k
CROSSTALK – dB
10k 100k 1M
90
80
70
VDD = +15V
V
SS
= –15V
VL = +5V
Figure 8. Crosstalk vs. Frequency
APPLICATION
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
OUT
follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold capacitor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is
typically 30 µV/µs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differential effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation network R
C
and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
+15V
–15V
2200pF
R
C
75V
C
C
1000pF
C
H
2200pF
V
OUT
ADG411
ADG412
ADG413
SW2
SW1
S
S
D
D
+15V +5V
–15V
AD845
+15V
–15V
V
IN
AD711
Figure 9. Fast, Accurate Sample-and-Hold
Page 7
ADG411/ADG412/ADG413
REV. A –7–
I
DS
V1
SD
V
S
RON = V1/I
DS
Test Circuit 1. On Resistance
SD
V
S
V
D
A
ID (ON)
Test Circuit 3. On Leakage
Test Circuits
SD
V
S
A
V
D
A
IS (OFF)
I
D
(OFF)
Test Circuit 2. Off Leakage
SD
+15V +5V
0.1mF 0.1mF
V
DDVL
IN
V
S
GND
V
SS
R
L
300V
C
L
35pF
V
OUT
0.1mF
–15V
t
ON
t
OFF
3V
50% 50%
50% 50%
3V
90% 90%
V
IN
V
IN
V
OUT
ADG411
ADG412
Test Circuit 4. Switching Times
S1 D1
+15V +5V
0.1mF 0.1mF
V
DDVL
IN1, IN2
V
S1
GND
V
SS
R
L1
300V
C
L1
35pF
V
OUT1
0.1mF
–15V
V
S2
V
OUT2
R
L2
300V
C
L2
35pF
S2
V
IN
D2
t
D
t
D
3V
50% 50%
90%
V
IN
V
OUT1
V
OUT2
90%
90%
90%
0V
0V
0V
Test Circuit 5. Break-Before-Make Time Delay
SD
+15V +5V
V
DDVL
IN
V
S
GND
V
SS
C
L
10nF
V
OUT
–15V
R
S
3V
V
IN
V
OUT
DV
OUT
Q
INJ
= CL 3 DV
OUT
Test Circuit 6. Charge Injection
Page 8
ADG411/ADG412/ADG413
REV. A–8–
C1748a–3–2/98
SD
+15V +5V
0.1mF 0.1mF
V
DDVL
V
S
GND
V
SS
50V
NC
0.1mF
–15V
V
IN1
V
IN2
DS
R
L
50V
V
OUT
CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG V
S/VOUT
Test Circuit 8. Channel-to-Channel Crosstalk
SD
+15V +5V
0.1mF 0.1mF
V
DDVL
IN
V
S
GND
V
SS
R
L
50V
V
OUT
0.1mF
–15V
V
IN
Test Circuit 7. Off Isolation
PRINTED IN U.S.A.
16-Lead Cerdip
(Q-16)
16
1
8
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.080 (2.03) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
16-Lead Plastic DIP (Narrow)
(N-16)
16
18
9
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
MECHANICAL INFORMATION
Dimensions are shown in inches and (mm).
16-Lead SOIC
(R-16A)
16 9
81
0.3937 (10.00)
0.3859 (9.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
88
08
0.0196 (0.50)
0.0099 (0.25)
x 458
16-Lead TSSOP
(RU-16)
16
9
8
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
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