Datasheet ADG333ABRS, ADG333ABR, ADG333ABN Datasheet (Analog Devices)

S1A

D1

S1B

IN1

IN2

S2B

D2

S2A

S3A

D3

S3B

IN3

IN4

S4B

D2

S4A

ADG333A

SWITCHES SHOWN FOR A LOGIC “1” INPUT

a

Quad SPDT Switch

ADG333A

FEATURES
44 V Supply Maximum Ratings
VSS to VDD Analog Signal Range
Low On Resistance (45 V max)
Low ∆R
Low R

(5 V max)

ON

Match (4 V max)

ON

Low Power Dissipation
Fast Switching Times

< 175 ns

t

ON

< 145 ns

t

OFF

Low Leakage Currents (5 nA max)
Low Charge Injection (10 pC max)
Break-Before-Make Switching Action

APPLICATIONS
Audio and Video Switching
Battery Powered Systems
Test Equipment
Communication Systems

GENERAL DESCRIPTION

The ADG333A is a monolithic CMOS device comprising four
independently selectable SPDT switches. It is designed on an

2

LC

MOS process which provides low power dissipation yet

achieves a high switching speed and a low on resistance.
The on resistance profile is very flat over the full analog input

range ensuring good linearity and low distortion when switching
audio signals. High switching speed also makes the part suitable
for video signal switching. CMOS construction ensures ultralow
power dissipation making the part ideally suited for portable,
battery powered instruments.

When they are ON, each switch conducts equally well in both
directions and has an input signal range which extends to the
power supplies. In the OFF condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent in
the design is low charge injection for minimum transients when
switching the digital inputs.

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Extended Signal Range
The ADG333A is fabricated on an enhanced LC

2

MOS
process, giving an increased signal range which extends
to the supply rails.

2. Low Power Dissipation

3. Low R

ON

4. Single Supply Operation
For applications where the analog signal is unipolar,
the ADG333A can be operated from a single rail power
supply. The part is fully specified with a single +12 V
supply.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADG333A–SPECIFICA TIONS

1

DUAL SUPPLY

(VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted)

–408C to

Parameter +258C +858C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V
R

ON

20 Ω typ VD = ±10 V, IS = –1 mA

SS

to V

DD

V

45 45 Ω max

∆R

ON

5 Ω max VD = ±5 V, IS = –10 mA

RON Match 4 Ω max VD = ±10 V, IS = –10 mA

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.1 nA typ VD = ±15.5 V, VS = +15.5 V

S

= +16.5 V, VSS = –16.5 V

DD

±0.25 ±3 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.1 nA typ VS = VD = ±15.5 V

D

±0.4 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max
Input Current
I

INL

or I

INH

±0.005 µA typ VIN = 0 V or V

DD

±0.5 µA max

OPEN

2

90 ns typ RL = 300 Ω, CL = 35 pF;

175 ns max V

= ±10 V; Test Circuit 4

S

80 ns typ RL = 300 Ω, CL = 35 pF;

145 ns max V

= ±10 V; Test Circuit 4

S

10 ns min RL = 300 Ω, CL = 35 pF;

V

= +5 V; Test Circuit 5

S

= 0 V, RD = 0 Ω, CL = 10 nF;

10 pC max V

D

= +15 V, VSS = –15 V; Test Circuit 6

DD

= 75 Ω, CL = 5 pF, f = 1 MHz;

L

V

= 2.3 V rms, Test Circuit 7

S

= 75 Ω, CL = 5 pF, f = 1 MHz;

L

V

= 2.3 V rms, Test Circuit 8

S

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Delay, t
Charge Injection 2 pC typ V
OFF Isolation 72 dB typ R
Channel-to-Channel Crosstalk 85 dB typ R
C

(OFF) 5 pF typ

S

CD, CS (ON) 20 pF typ

POWER REQUIREMENTS

I

DD

0.05 mA typ Digital Inputs = 0 V or 5 V

0.25 0.35 mA max

I

SS

0.01 µA typ
15µA max

VDD/V

SS

NOTES

1

Temperature range is as follows: B Version: –40°C to +85 °C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

±3/±20 V min/V max |VDD| = |VSS|

–2–

REV. 0

ADG333A

SINGLE SUPPLY

(VDD = +12 V, VSS = 0 V 6 10%, GND = 0 V, unless otherwise noted)

–408C to

Parameter +258C +858C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to V
R

ON

35 Ω typ VD = +1 V, +10 V, IS = –1 mA

DD

V

75 Ω max

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.1 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V

S

= +13.2 V

DD

±0.25 ±3 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.1 nA typ VS = VD = 12.2 V/1 V

D

±0.4 ±5 nA max Test Circuit 3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max
Input Current
I

INL

or I

INH

±0.005 µA typ VIN = 0 V or V

DD

±0.5 µA max

OPEN

2

110 ns typ RL = 300 Ω, CL = 35 pF;

200 ns max V

= +8 V; Test Circuit 4

S

100 ns typ RL = 300 Ω, CL = 35 pF;

180 ns max V

= +8 V; Test Circuit 4

S

10 ns min RL = 300 Ω , CL = 35 pF;

ns min V

= +5 V; Test Circuit 5

S

= 6 V, RD = 0 Ω, CL = 10 nF;

D

V

= +12 V, VSS = –0 V; Test Circuit 6

DD

= 75 Ω, CL = 5 pF, f = 1 MHz;

L

V

= 1.15 V rms, Test Circuit 7

S

= 75 Ω, CL = 5 pF, f = 1 MHz;

L

V

= 1.15 V rms, Test Circuit 8

S

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-Before-Make Delay, t
Charge Injection 5 pC typ V
OFF Isolation 72 dB typ R
Channel-to-Channel Crosstalk 85 dB typ R
C

(OFF) 5 pF typ

S

CD, CS (ON) 20 pF typ

POWER REQUIREMENTS V

I

DD

0.05 mA typ Digital Inputs = 0 V or 5 V

0.25 0.35 mA max

V

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85 °C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. 0

+3/+30 V min/V max

–3–

= +13.5 V

DD

ADG333A

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –30 V

SS

Analog, Digital Inputs

2

. . . . . . . . . . . .VSS – 2 V to VDD + 2 V

. . . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 20 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic Package

θ

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 103°C/W

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C

1

SOIC Package

θ

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SSOP Package

θ

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Only one absolute maximum rating may be applied at any one time.

2

Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG333A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Option*

ADG333ABN –40°C to +85°C N-20
ADG333ABR –40°C to +85°C R-20
ADG333ABRS –40°C to +85°C RS-20

*N = Plastic DIP, R = Small Outline IC (SOIC). RS = Shrink Small Outline

Package (SSOP).

Table I. Truth Table

Logic Switch A Switch B

0 OFF ON
1 ON OFF

–4–

REV. 0

ADG333A

TERMINOLOGY

S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
R
∆R

ON

ON

Ohmic resistance between D and S.
RON variation due to a change in the analog

input voltage with a constant load current.

R

Match Difference between the RON of any two

ON

channels.

IS (OFF) Source leakage current with the switch

“OFF.”

I

(OFF) Drain leakage current with the switch

D

“OFF.”

I

, IS (ON) Channel leakage current with the switch

D

“ON.”
VD (VS) Analog voltage on terminals D, S.
C

(OFF) “OFF” Switch Source Capacitance.

S

(OFF) “OFF” Switch Drain Capacitance.

C

D

PIN CONFIGURATION

DIP/SOIC/SSOP

C

, CS (ON) “ON” Switch Capacitance.

D

t

ON

Delay between applying the digital control in­put and the output switching on.

t

OFF

Delay between applying the digital control in­put and the output switching off.

t

OPEN

Break Before Make delay when switches are

configured as a multiplexer.
V
V
I

INL
INH

INL

(I

) Input current of the digital input.

INH

Maximum input voltage for logic “0.”

Minimum input voltage for logic “1.”

Crosstalk A measure of unwanted signal which is

coupled through from one channel to another

as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling

through an “OFF” switch.
Charge Injection A measure of the glitch impulse transferred

from the digital input to the analog output

during switching.

1

IN1

2

S1A

3

D1

4

S1B

V

5

ADG333A

SS

GND

6

(Not to Scale)

S2B

7

D2

8

S2A

9

10

IN2

NC = NO CONNECT

TOP VIEW

20

IN4

19

S4A

18

D4

17

S4B

16

V

DD

15

NC

14

S3B
D3

13

S3A

12

IN3

11

REV. 0

–5–

SWITCHING TIME – ns

160

140

60

05 20

10 15

120

100

80

V

DD

– Volts

VD = +2V
V

S

= –2V

SWITCHING FREQUENCY – kHz

I

DD

– mA

1

0.8

0

0 200 1000

400 600 800

0.6

0.4

0.2

VDD = +16.5V
V

SS

= –16.5V

T

A

= +25°C

ADG333A–

Typical Performance Graphs

60

TA = +25°C

50

40

– Ω

ON

R

30

20

10

–15 –10 15

VDD = +5V

= –5V

V

SS

VDD = +10V

= –10V

V

SS

VDD = +15V

= –15V

V

SS

–5 0 5 10

VD, VS – Volts

Figure 1. RON as a Function of V
(VS): Dual Supply

100

90

80

70

– Ω

60

ON

R

50

40

30

20

03 15

VDD = +5V
VSS = 0V

VDD = +10V
VSS = 0V

6912

VD, VS – Volts

TA = +25°C

VDD = +15V
VSS = 0V

60

VDD = +15V

= 0V

V

SS

50

40

– Ω

ON

R

30

20

10

D

Figure 4. RON as a Function of VD (VS)
for Different Temperatures: Single

+125°C

–40°C

03 15

V

D

+85°C

+25°C

6912

, VS – Volts

20

CL = 10nF

15

10

5

VDD = +16.5V

0

Q – pC

–5

–10

–15

–20

= –16.5V

V

SS

–15 –10 15

–5 0 5 10

VS – Volts

VDD = +12V

= –0V

V

SS

Figure 7. Charge Injection as a
Function of V

S

Supply

0.004
VDD = +16.5V

0.002

–0.002

–0.004

–0.006

LEAKAGE CURRENT – nA

–0.008

–0.01

= –16.5V

V

SS

T

= +25°C

A

0

IS (ON)

–15 –10 15

IS (OFF)

ID (ON)

–5 0 5 10

V

, VS – Volts

D

Figure 2. RON as a Function of VD (VS):
Single Power Supply

45

VDD = +15V

40

= –15V

V

SS

35

30

– Ω

ON

25

R

20

15

10

Figure 3. RON as a Function of VD (VS)
for Different Temperatures: Dual
Supply

+125°C

+85°C

–15 –10 15

–5 0 5 10

VD, VS – Volts

Figure 5. Leakage Currents as a
Function of V

0.001

0

VDD = +16.5V
V
T

–0.001

–0.002

LEAKAGE CURRENT – nA

+25°C –40°C

–0.003

–0.004

03 12

(VS): Dual Supply

D

= –16.5V

SS

= +25°C

A

ID (ON)

VD, VS – Volts

IS (OFF)

IS (ON)

69

Figure 6. Leakage Currents as a
Function of V

(VS): Single Supply

D

Figure 8. Switching Time as a
Function of V

DD

Figure 9. IDD as a Function of
Switching Frequency

–6–

REV. 0

SD

V

IN1

S

D

75Ω

V

IN2

NC

20 x LOG

|

VS/V

OUT

|

CHANNEL TO CHANNEL
CROSSTALK

R

L

75Ω

V

OUT

GND

V

SS

V

DD

V

DD

0.1µF

0.1µF
V

SS

V

S

= V1/I

V

D

SD

A

V

S

IS (OFF)

R

ON

I

DS

V

1

SD

DS

ADG333A

(ON)

I

D

V

D

NC

SD

A

V

D

Test Circuit 1. On Resistance

V

DD

0.1µF

V

DD

–10V

V

S

+10V

V

S

SB
SA

D

IN

GND

V

SS

0.1µF
V

SS

V

DD

0.1µF

V

DD

SB
SA

D

IN

GND

V

SS

0.1µF
V

SS

Test Circuit 2. Off Leakage

V

R

L

300Ω

C

L

35pF

OUT

+10V

–10V

Test Circuit 4. Switching Times

V

R

L

300Ω

C

L

35pF

OUT

Test Circuit 3. On Leakage

3V

V

IN

0V

V

S

0V

3V

0V

V

S

50%

50% 50%

t

ON

V

IN

V

OUT

50% 50%

t

OPEN

50%

t

OFF

REV. 0

V

D

V

S

V

DD

V

R

D

IN

DD

DSA

GND

V

V

V

IN

0.1µF

SD

GND

0.1µF

Test Circuit 7. Off Isolation

Test Circuit 5. Break-Before-Make Delay, t

OPEN

3V

V

V

OUT

C

L

10nF

SS

SS

IN

0V

V

OUT

0V

Q

INJ

= CL x ∆V

OUT

∆V

OUT

Test Circuit 6. Charge Injection

V

DD

V

DD

V

OUT

R

L

75Ω

V

SS

V

SS

Test Circuit 8. Channel-to-Channel Crosstalk

–7–

ADG333A

APPLICATIONS INFORMATION

ADG333A Supply Voltages

The ADG333A can operate off a dual or signal supply. V

SS

should be connected to GND when operating with a single
supply. When using a dual supply the ADG333A can also oper­ate with unbalanced supplies, for example V

= 20 V and V

DD

SS

= –5 V. The only restrictions are that VDD to GND must not
exceed 30 V, V

to GND must not drop below –30 V and V

SS

DD

to VSS must not exceed +44 V. It is important to remember that
the ADG333A supply voltage directly affects the input signal
range, the switch ON resistance and the switching times of the
part. The effects of the power supplies on these characteristics

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Pin Plastic DIP (N-20)

1.060 (26.90)

0.925 (23.50)

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

20

110

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

11

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.130
(3.30)

MIN
SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

can be clearly seen from the characteristic curves in this data
sheet.

Power Supply Sequencing

When using CMOS devices care must be taken to ensure
correct power-supply sequencing. Incorrect power-supply
sequencing can result in the device being subjected to stresses
beyond those maximum ratings listed in the data sheet. This is
also true for the ADG333A. Always sequence V
followed by V

and the logic signals. An external signal within

SS

on first

DD

the maximum specified ratings can then be safely presented to
the source or drain of the switch

20-Pin SOIC (R-20)

0.5118 (13.00)

0.4961 (12.60)

20 11

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8°
0°

0.0157 (0.40)

x 45°

0.0118 (0.30)

0.0040 (0.10)

PIN 1

0.0500
(1.27)

BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

101

SEATING
PLANE

C2076–18–10/95

20-Pin SSOP (RS-20)

0.295 (7.50)

0.271 (6.90)

20 11

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.0256
(0.65)

LEADS WILL BE EITHER TIN PLATED OR SOLDIER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

BSC

101

0.07 (1.78)

0.066 (1.67)

SEATING

PLANE

0.212 (5.38)

0.205 (5.21)

0.009 (0.229)

0.005 (0.127)

–8–

8°
0°

0.037 (0.94)

0.022 (0.559)

PRINTED IN U.S.A.

REV. 0