Datasheet ADG3308 Datasheet (Analog Devices)

Low Voltage, 1.15 V to 5.5 V, 8-Channel

FEATURES

Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 µA
No direction pin

APPLICATIONS

Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces

GENERAL DESCRIPTION

The ADG3308 is a bidirectional logic level translator that con­tains eight bidirectional channels. It can be used in multivoltage
digital system applications such as data transfer between a low
voltage DSP controller and a higher voltage device. The internal
architecture allows the device to perform bidirectional logic
level translation without an additional signal to set the direction
in which the translation takes place.

The voltage applied to V
the device, while V
operation, V

CCY

must always be less than V

CCA

patible logic signals applied to the A side of the device appear as

-compatible levels on the Y side. Similarly, V

V

CCY

logic levels applied to the Y side of the device appear as V
compatible logic levels on the A side.

sets the logic levels on the A side of

CCA

sets the levels on the Y side. For proper

CCY

. The V

-com-

CCA

-compatible

CCY

CCA

-

Bidirectional Logic Level Translator

ADG3308

FUNCTIONAL BLOCK DIAGRAM

V

CCA

A1

A2

A3

A4

A5 Y5

A6 Y6

A7

A8

EN

The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. The EN pin is referred to the V
driven high for normal operation.

The ADG3308 is available in compact 20-lead TSSOP and
20-lead LFCSP packages. It is guaranteed to operate over the

1.15 V to 5.5 V supply voltage range and the extended −40°C to
+85°C temperature range.

PRODUCT HIGHLIGHTS

1. Bidirectional level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

GND

Figure 1.

V

CCY

Y1

Y2

Y3

Y4

Y7

Y8

supply voltage and

CCY

04865-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

4. 20-lead TSSOP and 20-lead LFCSP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

ADG3308

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Test C ir c uit s ..................................................................................... 12

Te r mi n ol o g y .................................................................................... 15

Theory of Operation ...................................................................... 16

Level Translator Architecture ................................................... 16

REVISION HISTORY

1/05—Revision 0: Initial Version

Input Driving Requirements..................................................... 16

Output Load Requirements ...................................................... 16

Enable Operation ....................................................................... 16

Power Supplies ............................................................................ 16

Data Rate ..................................................................................... 17

Applications..................................................................................... 18

Layout Guidelines....................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG3308

CCA

≤ V

≤ V

CCA

3

3

3

3

3

CCY

1

= 1.15 V to V

3

, V

= 5 V ± 0.5 V

CCY

, V

= 3.3 V ± 0.3 V

CCY

CCY

, GND = 0 V. All specifications T

CCY

V

IHA

IHA

V

ILA

OHA

OLA

C

A

LA, HiZ

V

IHY

ILY

OHY

OLY

LY, HiZ

V

IHEN

V

ILEN

LEN

C

EN

t

EN

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V V

CCA

0.4 V

VY = V

VY = 0 V, IOL = 20 µA, Figure 28 0.4 V

f = 1 MHz, EN = 0, Figure 33 9 pF
VA = 0 V/V

V

0.4 V
VA = V
VA = 0 V, IOL = 20 µA, Figure 29 0.4 V
f = 1 MHz, EN = 0, Figure 34 6 pF
VY = 0 V/V

V

0.4 V
VEN = 0 V/V

3 pF
RS = RT = 50 Ω, VA = 0 V/V

V

= 0 V/V

Y

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

= RT = 50 Ω, CL = 50 pF, Figure 36

S

6 10 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 4 ns
3 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

4 7 ns
1 3 ns

3 7 ns
50 Mbps
2 3.5 ns
2 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

8 11 ns
2 5 ns
2 5 ns
50 Mbps
2 4 ns
4 ns

to T

MIN

, IOH = 20 µA, Figure 28 V

CCY

, EN = 0, Figure 30 ±1 µA

CCA

, IOH = 20 µA, Figure 29 V

CCA

, EN = 0, Figure 31 ±1 µA

CCY

, VA = 0 V, Figure 32 ±1

CCY

(Y→A), Figure 35

CCY

, unless otherwise noted.

MAX

(A→Y),

CCA

1 1.8 µs

− 0.3 V

CCA

− 0.4

CCA

− 0.4 V

CCA

− 0.4 V

CCY

− 0.4 V

CCY

− 0.4

CCY

µA

SPECIFICATIONS

V

= 1.65 V to 5.5 V, V

CCY

Table 1.

Parameter Symbol Conditions Min Typ2Max Unit

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage
V
Input Low Voltage
Output High Voltage V
Output Low Voltage V
Capacitance
Leakage Current I

Y Side

Input Low Voltage
Input High Voltage3 V
Output High Voltage V
Output Low Voltage V
Capacitance3 CY
Leakage Current I

Enable (EN)

Input High Voltage
Input Low Voltage
Leakage Current I

Capacitance
Enable Time

SWITCHING CHARACTERISTICS

3.3 V ± 0.3 V ≤ V
A→Y Level Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Level Translation

Propagation Delay t
Rise Time t

Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.8 V ± 0.15 V ≤ V
A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

3

3

3

CCA

Rev. 0 | Page 3 of 20

ADG3308

Parameter Symbol Conditions Min Typ2Max Unit

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V ≤ V

CCA

≤ V

, V

= 3.3 V ± 0.3 V

CCY

CCY

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V ≤ V

CCA

≤ V

, V

= 1.8 V ± 0.3 V

CCY

CCY

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

2.5 V ± 0.2 V ≤ V

CCA

≤ V

, V

= 3.3 V ± 0.3 V

CCY

CCY

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 8 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 3 ns
3 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

9 18 ns
3 5 ns
2 5 ns
40 Mbps
2 5 ns
10 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 9 ns
2 4 ns
2 4 ns
40 Mbps
2 4 ns
4 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

12 25 ns
7 12 ns
3 5 ns
25 Mbps
2 5 ns
15 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

14 35 ns
5 16 ns

2.5 6.5 ns
25 Mbps
3 6.5 ns

23.5 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

7 10 ns

2.5 4 ns
2 5 ns
60 Mbps

1.5 2 ns
4 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 8 ns
1 4 ns
3 5 ns
60 Mbps
2 3 ns
3 ns

Rev. 0 | Page 4 of 20

ADG3308

Parameter Symbol Conditions Min Typ2Max Unit

POWER REQUIREMENTS

Power Supply Voltages V

V
Quiescent Power Supply Current I

I

Three-State Mode Power Supply Current I

I

1

Temperature range is as follows: B version: −40°C to +85°C.

2

All typical values are at TA = 25°C, unless otherwise noted.

3

Guaranteed by design; not subject to production test.

CCA

CCY

CCA

CCY

HiZA

HiZY

V

≤ V

CCA

CCY

1.65 5.5 V
VA = 0 V/V

= V

V

CCA

VA = 0 V/V
V

= V

CCA

V

= V

CCA

V

= V

CCA

, VY = 0 V/V

CCA

= 5.5 V, EN = V

CCY

, VY = 0 V/V

CCA

= 5.5 V, EN = V

CCY

= 5.5 V, EN = 0 0.1 1 µA

CCY

= 5.5 V, EN = 0 0.1 1 µA

CCY

CCY

CCY

,

CCY

,

CCY

1.15 5.5 V

0.17 1 µA

0.27 1 µA

Rev. 0 | Page 5 of 20

ADG3308

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

V

to GND −0.3 V to +7 V

CCA

V

to GND V

CCY

Digital Inputs (A) −0.3 V to (V
Digital Inputs (Y) −0.3 V to (V
EN to GND −0.3 V to +7 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

20-Lead TSSOP 78°C/W

20-Lead LFCSP 30.4°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (< 20 sec) 260°C

to +7 V

CCA

+ 0.3 V)

CCA

+ 0.3 V)

CCY

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

ADG3308

A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

CCA

2

A1

3

A2

ADG3308

4

A3
A4
A5
A6
A7
A8
EN

(Not to Scale)

5

6

7

8

9

10

TOP VIEW

20

V

CCY

19

Y1

18

Y2

17

Y3

16

Y4

15

Y5

14

Y6

13

Y7

12

Y8

11

GND

04865-002

Figure 2. 20-Lead TSSOP Figure 3. 20-Lead LFCSP

Table 3. Pin Function Descriptions

Pin. No.

TSSOP LFCSP Mnemonic Description

1 19 V
2 20 A1

Power Supply Voltage Input for the A1 to A8 I/O Pins (1.15 V ≤ V

CCA

Input/Output A1. Referenced to V
3 1 A2 Input/Output A2. Referenced to V
4 2 A3 Input/Output A3. Referenced to V
5 3 A4 Input/Output A4. Referenced to V
6 4 A5 Input/Output A5. Referenced to V
7 5 A6 Input/Output A6. Referenced to V
8 6 A7 Input/Output A7. Referenced to V
9 7 A8 Input/Output A8. Referenced to V
10 8 EN Active High Enable Input.
11 9 GND Ground.
12 10 Y8 Input/Output Y8. Referenced to V
13 11 Y7 Input/Output Y7. Referenced to V
14 12 Y6 Input/Output Y6. Referenced to V
15 13 Y5 Input/Output Y5. Referenced to V
16 14 Y4 Input/Output Y4. Referenced to V
17 15 Y3 Input/Output Y3. Referenced to V
18 16 Y2 Input/Output Y2. Referenced to V
19 17 Y1
20 18 V

Power Supply Voltage Input for the Y1 to Y8 I/O Pins (1.65 V ≤ V

CCY

Input/Output Y1. Referenced to V

Y
C

C

1A2
2A3
3A4
4A5
5A6

1
A

0
2

ADG3308

TOP VIEW

(Not to Scale)

6
7

A

1

C

C

V

V

Y
7

9

8

1

1

1

PIN 1
INDICATOR

9

8

7
8

N

D

A

E

N
G

2
Y

6
1

15 Y3
14 Y4
13 Y5
12 Y6
11 Y7

0
1

8
Y

04865-003

The exposed pad can be tied to GND or it can be left floating.

or V

CCA

CCY

.

CCY

).

CCA

CCA

CCA

CCA

CCA

CCA

CCA

CCA

CCY

CCY

CCY

CCY

CCY

CCY

CCY

CCY

Do not tie it to V

< V

CCA

.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
.

≤ 5.5 V).

CCY

Rev. 0 | Page 7 of 20

ADG3308

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
TA = 25°C

1 CHANNEL

0.9

= 50pF

C

L

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 4. I

10

TA = 25°C
1 CHANNEL

9

= 50pF

C

L

8

7

6

(mA)

5

CCY

I

4

3

2

1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 5. I

3.0
TA = 25°C

1 CHANNEL
C

= 15pF

L

2.5

2.0

(mA)

1.5

CCA

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 6. I

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

= 1.8V

CCY

CCY

V

= 3.3V, V

CCA

V

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCY

CCA

= 5V

CCY

V

= 1.2V, V

CCA

= 1.8V, V

= 1.8V

CCY

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (Y→A Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

CCY

CCY

= 3.3V

= 3.3V

= 3.3V

04865-004

04865-005

04865-006

3.0
TA = 25°C

1 CHANNEL
C

= 15pF

L

2.5

2.0

V

= 3.3V, V

CCA

(mA)

1.5

CCY

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 7. I

vs. Data Rate (Y→A Level Translation)

CCY

V

DATA RATE (Mbps)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

1.6
TA =25°C

1 CHANNEL

1.4

V

= 1.2V

CCA

= 1.8V

V

CCY

1.2

1.0

(mA)

0.8

CCY

I

0.6

0.4

0.2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 8. I

vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V)

CCY

20Mbps

10Mbps

5Mbps

1Mbps

Level Translation

1.0
TA = 25°C

1 CHANNEL

0.9
V

= 1.2V

CCA

V

=1.8V

CCY

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

0

13 23 33 43 53

Figure 9. I

vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V)

CCA

CAPACITIVE LOAD (pF)

20Mbps

10Mbps
5Mbps

1Mbps

Level Translation

CCY

= 3.3V

04865-007

04865-012

04865-013

Rev. 0 | Page 8 of 20

ADG3308

9

TA = 25°C
1 CHANNEL

8

V

= 1.8V

CCA

V

= 3.3V

CCY

7

6

5

(mA)

4

CCY

I

3

2

1

0

13 23 33 43 53 63 73

Figure 10. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V)

CCY

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

Level Translation

5.0

TA = 25°C
1 CHANNEL

4.5

4.0

3.5

3.0

2.5

(mA)

CCA

I

2.0

1.5

1.0

0.5

Figure 11. I

= 1.8V

V

CCA

= 3.3V

V

CCY

0

13 23 33 43 53

CCA

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V)

Level Translation

12

TA = 25°C
1 CHANNEL

V

= 3.3V

CCA

10

= 5V

V

CCY

8

6

(mA)

CCY

I

4

2

0

13 23 33 43 53 63 73

Figure 12. I

CCY

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V)

Level Translation

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

04865-016

04865-017

04865-020

7

TA = 25°C
1 CHANNEL

= 3.3V

V

6

CCA

= 5V

V

CCY

5

4

(mA)

3

CCA

I

2

1

0

13 23 33 43 53

Figure 13. I

CCA

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V)

50Mbps

30Mbps
20Mbps

10Mbps

5Mbps

04865-021

Level Translation

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME(ns)

3

2

1

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

= 1.8V, V

CCA

V

= 3.3V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

CCY

CCY

= 3.3V

= 5V

04865-023

Figure 14. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

4.0
TA = 25°C

1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 1.8V

CCY

= 1.8V, V

= 3.3V, V

CCY

CCY

= 3.3V

= 5V

04865-024

Figure 15. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

Rev. 0 | Page 9 of 20

ADG3308

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME (ns)

3

2

1

0

13 18 23 28 33 38 43 48 53

Figure 16. Rise Time vs. Capacitive Load at Pin A ( Y→A Level Translation)

4.0

3.5

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 18 23 28 33 38 43 48 53

Figure 17. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)

14

12

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63

V

CCA

= 1.2V, V

= 1.8V

CCY

V

= 1.8V, V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 3.3V, V

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

V

CCA

= 1.2V, V

= 1.8V

CCY

CAPACITIVE LOAD (pF)

V

CCA

= 1.8V, V

V

CCA

= 3.3V, V

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

V

CCA

CAPACITIVE LOAD (pF)

Figure 18. Propagation Delay (t

= 1.8V, V

CCY

V

V

CCA

CCA

= 1.2V, V

= 3.3V

= 3.3V, V

) vs.

PLH

Capacitive Load at Pin Y (A→Y Level Translation)

CCY

CCY

CCY

CCY

= 3.3V

CCY

= 3.3V

CCY

= 1.8V

= 5V

= 5V

= 5V

73

04865-025

04865-026

04865-027

12

DATA RATE = 50kbps

A

= 25°C

T
1 CHANNEL

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 19. Propagation Delay (t

V

CCA

V

= 1.2V, V

CCA

V

CCA

= 1.8V, V

= 3.3V, V

) vs.

PHL

CCY

Capacitive Load at Pin Y (A→Y Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

3

V

= 1.8V, V

PROPAGATION DELAY (ns)

CCA

2

1

0

13 18 23 28 33 38 43 48 53

= 3.3V

CCY

CAPACITIVE LOAD (pF)

Figure 20. Propagation Delay (t

V

V

CCA

CCA

= 1.2V, V

= 3.3V, V

PLH

CCY

CCY

) vs.

Capacitive Load at Pin A (Y→A Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

V

3

PROPAGATION DELAY (ns)

2

1

0

13 18 23 28 33 38 43 48 53

CCA

CAPACITIVE LOAD (pF)

Figure 21. Propagation Delay (t

= 1.8V, V

V

CCA

V

CCA

= 3.3V

CCY

= 3.3V, V

= 1.2V, V

= 5V

CCY

PHL

CCY

) vs.

Capacitive Load at Pin A (Y→A Level Translation)

= 1.8V

CCY

CCY

= 1.8V

= 5V

= 1.8V

= 3.3V

= 5V

04865-028

04865-029

04865-030

Rev. 0 | Page 10 of 20

ADG3308

TA = 25°C
DATA RATE = 25Mbps

= 50pF

C

L

1 CHANNEL

TA = 25°C
DATA RATE = 50Mbps

= 15pF

C

L

1 CHANNEL

400mV/DIV

5ns/DIV

04860-037

Figure 22. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps)

200mV/DIV

TA = 25°C
DATA RATE = 25Mbps

5ns/DIV

= 50pF

C

L

1 CHANNEL

04860-038

Figure 23. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 50Mbps

= 50pF

C

L

1 CHANNEL

400mV/DIV

3ns/DIV

04860-040

Figure 25. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL

1V/DIV

3ns/DIV

04860-041

Figure 26. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
C

= 15pF

L

1 CHANNEL

500mV/DIV

3ns/DIV

04860-039

Figure 24. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps)

Rev. 0 | Page 11 of 20

800mV/DIV

3ns/DIV

04860-042

Figure 27. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps)

ADG3308

TEST CIRCUITS

V

CCA

0.1µF

A

K1

ADG3308

GND

EN
V

CCY

0.1µF

Y

V

CCA

K2

0.1µF

A

ADG3308

EN
V

Y

CCY

0.1µF

A

K

I

OH

K2

0.1µF

0.1µF

I

OL

Figure 28. V

V

CCA

A

Figure 29. V

V

CCA

Voltages at Pin A

OH/VOL

ADG3308

GND

Voltages at Pin Y

OH/VOL

ADG3308

EN
V

Y

I

CCY

OH

EN
V

CCY

0.1µF

K1

0.1µF

GND

04865-043

04865-046

Figure 31. Three-State Leakage Current at Pin Y

V

CCA

0.1µF

A

I

OL

04865-044

ADG3308

GND

V

Y

EN

CCY

0.1µF

K

A

04865-047

Figure 32. EN Pin Leakage Current

V

CCA

ADG3308

EN

V

CCY

A

K

A

GND

Y

CAPACITANCE

METER

04865-045

Figure 30. Three-State Leakage Current at Pin A

A

GND

Figure 33. Capacitance at Pin A

Y

04865-048

Rev. 0 | Page 12 of 20

ADG3308

V

CCA

A

ADG3308

GND

EN
V

CCY

Y

CAPACITANCE

METER

04865-049

Figure 34. Capacitance at Pin Y

A–Y DIRECTION

SIGNAL SOURCE

R

S

50Ω

0.1µF

+

10µF

K1

Z0 = 50Ω

V

CCA

V

A

V

EN

R

T

50Ω

ADG3308

A

EN

GND

V

Y

50pF

CCY

0.1µF

+

10µF

1MΩ

V

Y

K2

1MΩ

Y–A DIRECTION

V

+

0.1µF

SIGNAL SOURCE

R

S

50Ω

VY/V

10µF

1MΩ

K1

1MΩ

= 50Ω

Z

0

V

EN

VA/V

Y

90%
VY/V

A

V

EN

VA/V

Y

A

10%

NOTES

1. t

IS WHICHEVER IS LARGER BETWEEN

EN

IN BOTH A-Y AND Y-A DIRECTIONS.

CCA

V

A

15pF

V

EN

R

T

50Ω

t

EN1

t

EN2

Figure 35. Enable Time

ADG3308

A

EN

GND

t

AND

t

EN1

EN2

V

CCY

0.1µF

Y

V

CCY

0V
V

CCA/VCCY

0V
V

CCY/VCCA

0V

V

CCY

0V

V

CCA/VCCY

0V
V

CCY/VCCA

0V

+

10µF

V

Y

K2

04860-050

Rev. 0 | Page 13 of 20

ADG3308

ADG3308

A

GND

t

F,A-Y

SIGNAL

SOURCE

R

50Ω

V

50%

V

90%

50%

10%

S

A

Y

Z0 = 50Ω

0.1µF

V

50Ω

V

CCA

+

10µF

A

R

T

t

P,A-Y

Figure 36. Switching Characteristics (A→Y Level Translation)

t

P,A-Y

t

EN
V

0.1µF

R,A-Y

Y

CCY

V

Y

50pF

+

10µF

04865-051

ADG3308

GND

t

P,Y-A

0.1µF

50%

90%

50%

10%

15pF

V

Y

V

A

V

CCA

+

10µF

V

A

Figure 37. Switching Characteristics (Y→

t

F,Y-A

EN

V

CCY

+

V
R

50Ω

Y

T

t

10µF

Z0 = 50Ω

P,Y-A

0.1µF

YA

t

R,Y-A

SIGNAL

SOURCE

R

S

50Ω

04865-052

A Level Translation)

Rev. 0 | Page 14 of 20

ADG3308

TERMINOLOGY

Table 4.

Symbol Description

V

IHA

V

ILA

V

OHA

V

OLA

C

A

I

LA, HiZ

V

IHY

V

ILY

V

OHY

V

OLY

C

Y

I

LY, HiZ

V

IHEN

V

ILEN

C

EN

I

LEN

t

EN

t

P, A-Y

t

R, A-Y

t

F, A-Y

D

MAX, A-Y

t

SKEW, A-Y

t

PPSKEW, A-Y

t

P, Y-A

t

R, Y-A

t

F, Y-A

D

MAX, Y-A

t

SKEW, Y-A

t

PPSKEW, Y-A

V

CCA

V

CCY

I

CCA

I

CCY

I

HiZA

I

HiZY

Logic input high voltage at Pins A1 to A8.
Logic input low voltage at Pins A1 to A8.
Logic output high voltage at Pins A1 to A8.
Logic output low voltage at Pins A1 to A8.
Capacitance measured at Pins A1 to A8 (EN = 0).
Leakage current at Pins A1 to A8 when EN = 0 (high impedance state at Pins A1 to A8).
Logic input high voltage at Pins Y1 to Y8.
Logic input low voltage at Pins Y1 to Y8.
Logic output high voltage at Pins Y1 to Y8.
Logic output low voltage at Pins Y1 to Y8.
Capacitance measured at Pins Y1 to Y8 (EN = 0).
Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).
Logic input high voltage at the EN pin.
Logic input low voltage at the EN pin.
Capacitance measured at EN pin.
Enable (EN) pin leakage current.
Three-state enable time for Pins A1 to A8 /Y1 to Y8.
Propagation delay when translating logic levels in the A→Y direction.
Rise time when translating logic levels in the A→Y direction.
Fall time when translating logic levels in the A→Y direction.
Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the A→Y direction.
Difference in propagation delay between any one channel and the same channel on a different part (under same

driving/loading conditions) when translating in the A

→Y direction.

Propagation delay when translating logic levels in the Y→A direction.
Rise time when translating logic levels in the Y→A direction.
Fall time when translating logic levels in the Y→A direction.
Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the Y→A direction.
Difference in propagation delay between any one channel and the same channel on a different part (under same

driving/loading conditions) when translating in the Y
V

supply voltage.

CCA

V

supply voltage.

CCY

V

supply current.

CCA

V

supply current.

CCY

V

supply current during three-state mode (EN = 0).

CCA

V

supply current during three-state mode (EN = 0).

CCY

→A direction.

Rev. 0 | Page 15 of 20

ADG3308

THEORY OF OPERATION

The ADG3308 level translator allows the level shifting
necessary for data transfer in a system where multiple supply

CCY

and

CCA

-

CCY

T2T1

Y

T3T4

04865-053

voltages are used. The device requires two supplies, V

(V

≤ V

V

CCY

CCA

). These supplies set the logic levels on each

CCY

side of the device. When driving the A pins, the device translates
the V

-compatible logic levels to V

CCA

-compatible logic levels

CCY

available at the Y pins. Similarly, since the device is capable of
bidirectional translation, when driving the Y pins the V
compatible logic levels are translated to the V

-compatible

CCA

logic levels available at the A pins. When EN = 0, the A1 to A8
and Y1 to Y8 pins are three-stated. When EN is driven high, the
ADG3308 goes into normal operation mode and performs level
translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3308 consists of eight bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics Figure 38 shows a
simplified block diagram of a bidirectional channel.

V

CCA

6kΩ

U2

U1

P

A

Figure 38. Simplified Block Diagram of an ADG3308 Channel

ONE-SHOT GENERATOR

U4

6kΩ

U3

The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y

→A direction is performed using the inverters

U3 and U4. The one-shot generator detects a rising or falling
edge present on either the A side or the Y side of the channel. It
sends a short pulse that turns on the PMOS transistors (T1–T2)
for a rising edge, or the NMOS transistors (T3–T4) for a falling
edge. This charges/discharges the capacitive load faster, which
results in fast rise and fall times.

V

N

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3308, the circuit that
drives the input of the ADG3308 channels should have an
output impedance of less than or equal to 150 Ω and a
minimum current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3308 level translator is designed to drive CMOS­compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3308 outputs
and the load.

ENABLE OPERATION

The ADG3308 provides three-state operation at the A and Y
I/O pins by using the enable (EN) pin, as shown in Table 5.

Table 5. Truth Table

EN

0 Hi-Z
1 Normal operation2Normal operation

1

High impedance state.

2

In normal operation, the ADG3308 performs level translation.

Y I/O Pins A I/O Pins

1

Hi-Z

1

2

While EN = 0, the ADG3308 enters into three-state mode. In
this mode the current consumption from both the V

supplies is reduced, allowing the user to save power, which

V

CCY

CCA

and

is critical, especially on battery-operated systems. The EN input
pin can be driven with V

-compatible logic levels only.

CCY

POWER SUPPLIES

For proper operation of the ADG3308, the voltage applied to
the V
V
sequence is V
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, V
significant increase in the current taken from the V
For optimum performance, the V
decoupled to GND as close as possible to the device.

must be always less than or equal the voltage applied to

CCA

. To meet this condition, the recommended power-up

CCY

first and then V

CCY

might be greater than V

CCA

. The ADG3308 operates

CCA

due to a

CCY

CCA

and V

pins should be

CCY

supply.

CCA

The inputs of the unused channels (A or Y) should be tied to
their corresponding V

rail (V

CC

CCA

or V

) or to GND.

CCY

Rev. 0 | Page 16 of 20

ADG3308

DATA RATE

The maximum data rate at which the device is guaranteed to
operate is a function of the V

CCA

and V
combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to the
device, which meets the V

and VOL levels at the output and

OH

does not exceed the maximum junction temperature (see the

Absolute Maximum Ratings section). Table 6 shows the
guaranteed data rates at which the ADG3308 can operate in
both directions (A
and V

supply combinations.

CCY

→Y or Y→A level translation) for various V

Table 6. Guaranteed Data Rate (Mbps)

V

CCA

1.2 V (1.15 V to 1.3 V)

1.8 V (1.65 V to 1.95 V)

2.5 V (2.3 V to 2.7 V)

3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)

1

The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.

supply voltage

CCY

1

1.8 V

(1.65 V to 1.95 V)

25 30 40 40

- 45 50 50

- - 60 50

- - - 50

- - - -

CCA

2.5 V

(2.3 V to 2.7 V)

V

CCY

3.3 V

(3.0 V to 3.6 V)

5 V

(4.5 V to 5.5 V)

Rev. 0 | Page 17 of 20

ADG3308

APPLICATIONS

The ADG3308 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals to the Y pins. The
ADG3308 can provide level translation in both directions from

→Y or Y→A on all eight channels, eliminating the need for a

A
level translator IC for each direction. The internal architecture
allows the ADG3308 to perform bidirectional level translation
without an additional signal to set the direction in which the
translation is made. It also allows simultaneous data flow in
both directions on the same part, for example, when two
channels translate in A→Y direction while the other two
translate in Y→A direction. This simplifies the design by
eliminating the timing requirements for the direction signal
and reduces the number of ICs used for level translation.

Figure 39 shows an application where a 3.3 V microprocessor
can read or write data to and from a 1.8 V peripheral device
using an 8-bit bus.

100nF

V

3.3V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

I/OH1

I/O

I/O

I/OH4

I/OH5

I/O

I/OH7

I/OH8

2

H

3

H

6

H

CCY

Y1

Y2

Y3

Y4

ADG3308

Y5

Y6

Y7

EN GND

Figure 39. 1.8 V to 3.3 V 8-Bit Level Translation Circuit

When the application requires level translation between a
microprocessor and multiple peripheral devices, the ADG3308
I/O pins can be three-stated by setting EN = 0. This feature

100nF

V

CCA

A1

A2

A3

A4

A5

A6

A7

A8Y8

I/OL1

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

2

L

3

L

4

L

PERIPHERAL

5

L

6

L

7

L

8

L

1.8V

DEVICE

allows the ADG3308 to share the data buses with other devices
without causing contention issues. Figure 40 shows an application
where a 3.3 V microprocessor is connected to 1.8 V peripheral
devices using the three-state feature.

100nF 100nF

V

V

CCY

ADG3308

CCY

ADG3308

V

GND

CCA

A1
A2
A3
A4
A5
A6
A7
A8

CCA

A1
A2
A3
A4
A5
A6
A7
A8

I/OL1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

I/OL1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

2

L

3

L

4

L

5

L

6

L

7

L

8

L

2

L

3

L

4

L

5

L

6

L

7

L

8

L

1.8V

PERIPHERAL

DEVICE 1

1.8V

PERIPHERAL

DEVICE 2

04860-055

3.3V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

CS

1

I/O

H

I/OH2
I/O

3

H

I/O

4

H

I/O

5

H

6

I/O

H

7

I/O

H

8

I/O

H

100nF 100nF

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN GND

V
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN

Figure 40. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board
layout is important in the circuit overall performance. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V

) should be bypassed using low effective series resistance

V

CCY

pin (V

CC

(ESR) and effective series inductance (ESI) capacitors placed as

04860-055

close as possible to the V

CCA

and V

pins. The parasitic induc-

CCY

tance of the high speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.

CCA

and

Rev. 0 | Page 18 of 20

ADG3308

OUTLINE DIMENSIONS

6.60

6.50

6.40

0.60

MAX

0.60

MAX

0.75

0.55

0.35

COPLANARITY

0.08

16

15

11

10

EXPOSED

(BOTTOM VIEW)

PIN 1

INDICATOR

20

PAD

5

6

0.30

0.23

0.18

1

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

0.15

0.05

COPLANARITY

0.10

20

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

Figure 41. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

4.00

BSC SQ

PIN 1

INDICATOR

1.00

8°
0°

0.75

0.60

0.45

0.85

0.80

SEATING

PLANE

TOP

VIEW

12° MAX

0.80 MAX

0.65 TYP

0.50
BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

0.20
REF

3.75

BCS SQ

0.05 MAX

0.02 NOM

Figure 42. 20-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3308BRUZ
ADG3308BRUZ-REEL
ADG3308BRUZ-REEL7
ADG3308BCPZ
ADG3308BCPZ-REEL
ADG3308BCPZ-REEL7

1

Z = Pb-free part.

1

1

1

1

1

1

−40°C to +85°C 20-Lead Thin Shrink Small Outline Package RU-20

−40°C to +85°C 20-Lead Thin Shrink Small Outline Package RU-20

−40°C to +85°C 20-Lead Thin Shrink Small Outline Package RU-20

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package CP-20

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package CP-20

−40°C to +85°C 20-Lead Lead Frame Chip Scale Package CP-20

Rev. 0 | Page 19 of 20

ADG3308

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04865–0–1/05(0)

Rev. 0 | Page 20 of 20