Datasheet ADG3304 Datasheet (Analog Devices)

Low Voltage, 1.15 V to 5.5 V, 4-Channel

FEATURES

Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 µA
No direction pin

APPLICATIONS

SPI®, MICROWIRE™ level translation
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces

GENERAL DESCRIPTION

The ADG3304 is a bidirectional logic level translator that con­tains four bidirectional channels. It can be used in multivoltage
digital system applications such as data transfer between a low
voltage DSP/controller and a higher voltage device using SPI
and MICROWIRE interfaces. The internal architecture allows
the device to perform bidirectional logic level translation
without an additional signal to set the direction in which the
translation takes place.

The voltage applied to V
the device, while V
operation, V

CCY

must always be less than V

CCA

patible logic signals applied to the A side of the device appear as

-compatible levels on the Y side. Similarly, V

V

CCY

logic levels applied to the Y side of the device appear as V
compatible logic levels on the A side.

sets the logic levels on the A side of

CCA

sets the levels on the Y side. For proper

CCY

. The V

-com-

CCA

-compatible

CCY

CCA

-

Bidirectional Logic Level Translator

ADG3304

FUNCTIONAL BLOCK DIAGRAM

V

CCA

A1

A2

A3

A4

EN

The enable pin (EN) provides three-state operation on both the
A-side and the Y-side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. The EN pin is referred to the V
driven high for normal operation.

The ADG3304 is available in compact 14-lead TSSOP and
12-bump WLCSP packages. It is guaranteed to operate over
the 1.15 V to 5.5 V supply voltage range and the extended

−40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

1. Bidirectional level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

GND

Figure 1.

V

CCY

Y1

Y2

Y3

Y4

supply voltage and

CCA

04860-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

4. 14-lead TSSOP and 12-bump WLCSP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

ADG3304

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Test C ir c ui t s .....................................................................................12

Te r mi n ol o g y .................................................................................... 15

Theory of Operation ...................................................................... 16

Level Translator Architecture ................................................... 16

REVISION HISTORY

1/05—Revision 0: Initial Version

Input Driving Requirements..................................................... 16

Output Load Requirements ...................................................... 16

Enable Operation ....................................................................... 16

Power Supplies ............................................................................ 16

Data Rate ..................................................................................... 17

Applications..................................................................................... 18

Layout Guidelines....................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG3304

CCA

≤ V

≤ V

CCA

3

3

3

3

3

CCY

1

= 1.15 V to V

3

, V

= 5 V ± 0.5 V

CCY

, V

= 3.3 V ± 0.3 V

CCY

CCY

, GND = 0 V. All specifications T

CCY

V

IHA

IHA

V

ILA

OHA

OLA

C

A

LA, HiZ

V

IHY

ILY

OHY

OLY

CY

LY, HiZ

V

IHEN

IHEN

V

ILEN

LEN

C

EN

t

EN

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V V

CCA

0.4 V

VY = V

VY = 0 V, IOL = 20 µA, Figure 28 0.4 V

f = 1 MHz, EN = 0, Figure 33 9 pF
VA = 0 V/V

V

0.4 V
VA = V
VA = 0 V, IOL = 20 µA, Figure 29 0.4 V
f = 1 MHz, EN = 0, Figure 34 6 pF
VY = 0 V/V

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V V

CCA

0.4 V
VEN = 0 V/V

3 pF
RS = RT = 50 Ω, VA = 0 V/V

V

= 0 V/V

Y

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

= RT = 50 Ω, CL = 50 pF, Figure 36

S

6 10 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 4 ns
3 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

4 7 ns
1 3 ns

3 7 ns
50 Mbps
2 3.5 ns
2 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

8 11 ns
2 5 ns
2 5 ns
50 Mbps
2 4 ns
4 ns

to T

MIN

, IOH = 20 µA, Figure 28 V

CCY

, EN = 0, Figure 30 ±1 µA

CCA

, IOH = 20 µA, Figure 29 V

CCA

, EN = 0, Figure 31 ±1 µA

CCY

, VA = 0 V, Figure 32 ±1

CCA

(Y→A), Figure 35

CCY

, unless otherwise noted.

MAX

(A→Y),

CCA

1 1.8 µs

− 0.3 V

CCA

− 0.4

CCA

− 0.4 V

CCA

− 0.4 V

CCY

− 0.4 V

CCY

− 0.3 V

CCA

− 0.4 V

CCA

µA

SPECIFICATIONS

V

= 1.65 V to 5.5 V, V

CCY

Table 1.

Parameter Symbol Conditions Min Typ2Max Unit

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage
V
Input Low Voltage
Output High Voltage V
Output Low Voltage V
Capacitance
Leakage Current I

Y Side

Input Low Voltage
Input High Voltage3 V
Output High Voltage V
Output Low Voltage V
Capacitance
Leakage Current I

Enable (EN)

Input High Voltage
V
Input Low Voltage
Leakage Current I

Capacitance
Enable Time

SWITCHING CHARACTERISTICS

3.3 V ± 0.3 V ≤ V
A→Y Level Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Level Translation

Propagation Delay t
Rise Time t

Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.8 V ± 0.15 V ≤ V
A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

3

3

3

3

CCA

Rev. 0 | Page 3 of 20

ADG3304

Parameter Symbol Conditions Min Typ2Max Unit

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V ≤ V

CCA

≤ V

, V

= 3.3 V ± 0.3 V

CCY

CCY

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V ≤ V

CCA

≤ V

, V

= 1.8 V ± 0.3 V

CCY

CCY

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

2.5 V ± 0.2 V ≤ V

CCA

≤ V

CCY

, V

CCY

= 3.3 V ± 0.3 V

A→Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y→A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 8 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 3 ns
3 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

9 18 ns
3 5 ns
2 5 ns
40 Mbps
2 5 ns
10 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 9 ns
2 4 ns
2 4 ns
40 Mbps
2 4 ns
4 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

12 25 ns
7 12 ns
3 5 ns
25 Mbps
2 5 ns
15 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

14 35 ns
5 16 ns

2.5 6.5 ns
25 Mbps
3 6.5 ns

23.5 ns

= RT = 50 Ω, CL = 50 pF, Figure 36

S

7 10 ns

2.5 4 ns
2 5 ns
60 Mbps

1.5 2 ns
4 ns

= RT = 50 Ω, CL = 15 pF, Figure 37

S

5 8 ns
1 4 ns
3 5 ns
60 Mbps
2 3 ns
3 ns

Rev. 0 | Page 4 of 20

ADG3304

Parameter Symbol Conditions Min Typ2Max Unit

POWER REQUIREMENTS

Power Supply Voltages V

V
Quiescent Power Supply Current I

I

Three-State Mode Power Supply Current I
I

1

Temperature range is as follows: B version: −40°C to +85°C.

2

All typical values are at TA = 25°C, unless otherwise noted.

3

Guaranteed by design; not subject to production test.

CCA

CCY

CCA

CCY

HiZA

HiZY

V

≤ V

CCA

CCY

1.65 5.5 V
VA = 0 V/V

= V

V

CCA

VA = 0 V/V
V

= V

CCA

V

= V

CCA

V

= V

CCA

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

= 5.5 V, EN = 0 0.1 1 µA

CCY

= 5.5 V, EN = 0 0.1 1 µA

CCY

CCY

CCY

,

,

1.15 5.5 V

0.17 1 µA

0.27 1 µA

Rev. 0 | Page 5 of 20

ADG3304

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

V

to GND −0.3 V to +7 V

CCA

V

to GND V

CCY

Digital Inputs (A) −0.3 V to (V
Digital Inputs (Y) −0.3 V to (V
EN to GND −0.3 V to +7 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (4-Layer Board)

14-Lead TSSOP 89.21°C/W

12-Bump WLCSP 1200C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (< 20 sec) 260°C

to +7 V

CCA

+ 0.3 V)

CCA

+ 0.3 V)

CCY

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

ADG3304

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BUMP a1
INDICATOR

abc

V

CCA

NC

GND

1

2

A1

3

A2

4

A3

5

A4

6

7

ADG3304

TOP VIEW

(Not to Scale)

NC = NO CONNECT

14

V

CCY

13

Y1

12

Y2

11

Y3

10

Y4

9

NC

8

EN

04860-002

Figure 2. 14-Lead TSSOP Figure 3. 12-Bump WLCSP

Table 3. 14-Lead TSSOP Pin Function Descriptions

Pin No. Mnemonic Description

1 V

2 A1

CCA

Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ V

Input/Output A1. Referenced to V
3 A2 Input/Output A2. Referenced to V
4 A3 Input/Output A3. Referenced to V
5 A4 Input/Output A4. Referenced to V
6 NC No Connect.
7 GND Ground.
8 EN Active High Enable Input.
9 NC No Connect.
10 Y4 Input/Output Y4. Referenced to V
11 Y3 Input/Output Y3. Referenced to V
12 Y2 Input/Output Y2. Referenced to V
13 Y1
14 V

CCY

Input/Output Y1. Referenced to V

Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V).

CCA

CCA

CCA

CCA

CCY

CCY

CCY

CCY

Y1

1

Y2

2

Y3

3

Y4

4

TOP VIEW

(BUMPSAT THE BOTTOM)

Not to Scale

≤ V

CCA

CCY).

.
.
.
.

.
.
.
.

V

CCA

EN

GND

CCY

A1

A2

A3

A4

04860-003

Table 4. 12-Bump WLCSP Bump Function Descriptions

Bump No. Mnemonic Description

a1 Y1 Input/Output Y1. Referenced to V
a2 Y2 Input/Output Y2. Referenced to V
a3 Y3 Input/Output Y3. Referenced to V
a4 Y4 Input/Output Y4. Referenced to V
b1 V
b2 V

CCY

CCA

Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V).
Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ V

CCY.

CCY

CCY

CCY

.
.
.

≤ V

CCY

).

CCA

b3 EN Active High Enable Input.
b4 GND Ground.
c1 A1 Input/Output A1. Referenced to V
c2 A2 Input/Output A2. Referenced to V
c3 A3

Input/Output A3. Referenced to V

c4 A4 Input/Output A4. Referenced to V

.

CCA

.

CCA

.

CCA

.

CCA

Rev. 0 | Page 7 of 20

ADG3304

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
TA = 25°C

1 CHANNEL

0.9

= 50pF

C

L

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 4. I

10

TA = 25°C
1 CHANNEL

9

= 50pF

C

L

8

7

6

(mA)

5

CCY

I

4

3

2

1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 5. I

3.0
TA = 25°C

1 CHANNEL

= 15pF

C

L

2.5

2.0

(mA)

1.5

CCA

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 6. I

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

= 1.8V

CCY

CCY

V

= 3.3V, V

CCA

V

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCY

CCA

= 5V

CCY

V

= 1.2V, V

CCA

= 1.8V, V

= 1.8V

CCY

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (Y→A Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

CCY

CCY

= 3.3V

= 3.3V

= 3.3V

04860-004

04860-005

04860-006

3.0
TA = 25°C

1 CHANNEL

= 15pF

C

L

2.5

2.0

V

= 3.3V, V

CCA

(mA)

1.5

CCY

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 7. I

vs. Data Rate (Y→A Level Translation)

CCY

V

DATA RATE (Mbps)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

1.6
TA =25°C

1 CHANNEL

1.4

V

= 1.2V

CCA

V

= 1.8V

CCY

1.2

1.0

(mA)

0.8

CCY

I

0.6

0.4

0.2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 8. I

vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V)

CCY

20Mbps

10Mbps

5Mbps

1Mbps

Level Translation

1.0
TA = 25°C

1 CHANNEL

0.9

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

Figure 9. I

= 1.2V

V

CCA

V

=1.8V

CCY

20Mbps

10Mbps
5Mbps

0

13 23 33 43 53

vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V)

CCA

CAPACITIVE LOAD (pF)

1Mbps

Level Translation

CCY

= 3.3V

04860-007

04860-012

04860-013

Rev. 0 | Page 8 of 20

ADG3304

9

TA = 25°C
1 CHANNEL

8

V

= 1.8V

CCA

= 3.3V

V

CCY

7

6

5

(mA)

4

CCY

I

3

2

1

0

13 23 33 43 53 63 73

Figure 10. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V)

CCY

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

Level Translation

5.0

TA = 25°C
1 CHANNEL

4.5

4.0

3.5

3.0

2.5

(mA)

CCA

I

2.0

1.5

1.0

0.5

Figure 11. I

= 1.8V

V

CCA

= 3.3V

V

CCY

0

13 23 33 43 53

CCA

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V)

Level Translation

12

TA = 25°C
1 CHANNEL

V

= 3.3V

CCA

10

V

= 5V

CCY

8

6

(mA)

CCY

I

4

2

0

13 23 33 43 53 63 73

Figure 12. I

CCY

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V)

Level Translation

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

04865-016

04860-017

04860-020

7

TA = 25°C
1 CHANNEL

= 3.3V

V

6

CCA

= 5V

V

CCY

5

4

(mA)

3

CCA

I

2

1

0

13 23 33 43 53

Figure 13. I

CCA

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V)

50Mbps

30Mbps
20Mbps

10Mbps

5Mbps

04860-021

Level Translation

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME(ns)

3

2

1

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

= 1.8V, V

CCA

V

= 3.3V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

CCY

CCY

= 3.3V

= 5V

04860-023

Figure 14. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

4.0
TA = 25°C

1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 1.8V

CCY

= 1.8V, V

= 3.3V, V

CCY

CCY

= 3.3V

= 5V

04860-024

Figure 15. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

Rev. 0 | Page 9 of 20

ADG3304

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME (ns)

3

2

1

0

13 18 23 28 33 38 43 48 53

Figure 16. Rise Time vs. Capacitive Load at Pin A ( Y→A Level Translation)

V

= 1.2V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

V

CCA

= 1.8V, V

V

CCA

= 3.3V, V

CCY

= 3.3V

CCY

= 5V

04860-025

12

DATA RATE = 50kbps

A

= 25°C

T
1 CHANNEL

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 19. Propagation Delay (t

V

CCA

V

V

CCA

CCA

= 1.2V, V

= 1.8V, V

= 3.3V, V

) vs.

PHL

CCY

CCY

Capacitive Load at Pin Y (A→Y Level Translation)

= 1.8V

CCY

= 3.3V

= 5V

04860-028

4.0
TA = 25°C
1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

V

= 1.2V, V

CCA

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 18 23 28 33 38 43 48 53

= 1.8V

CCY

CAPACITIVE LOAD (pF)

V

CCA

V

= 1.8V, V

= 3.3V, V

CCA

CCY

= 3.3V

CCY

= 5V

04860-026

Figure 17. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)

14

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

12

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63

V

CCA

CAPACITIVE LOAD (pF)

Figure 18. Propagation Delay (t

= 1.8V, V

CCY

V

CCA

V

CCA

= 1.2V, V

= 3.3V

= 3.3V, V

= 1.8V

CCY

= 5V

CCY

73

04860-027

) vs.

PLH

Capacitive Load at Pin Y (A→Y Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

3

V

= 1.8V, V

PROPAGATION DELAY (ns)

CCA

2

1

0

13 18 23 28 33 38 43 48 53

= 3.3V

CCY

CAPACITIVE LOAD (pF)

Figure 20. Propagation Delay (t

V

V

CCA

CCA

= 1.2V, V

= 3.3V, V

PLH

CCY

CCY

) vs.

= 1.8V

= 5V

04860-029

Capacitive Load at Pin A (Y→A Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

V

3

PROPAGATION DELAY (ns)

2

1

0

13 18 23 28 33 38 43 48 53

CCA

CAPACITIVE LOAD (pF)

Figure 21. Propagation Delay (t

= 1.8V, V

V

CCA

V

CCA

= 3.3V

CCY

= 3.3V, V

= 1.2V, V

= 5V

CCY

PHL

CCY

) vs.

= 1.8V

04860-030

Capacitive Load at Pin A (Y→A Level Translation)

Rev. 0 | Page 10 of 20

ADG3304

TA = 25°C
DATA RATE = 25Mbps
C

= 50pF

L

1 CHANNEL

TA = 25°C
DATA RATE = 50Mbps

= 15pF

C

L

1 CHANNEL

400mV/DIV

5ns/DIV

04860-037

Figure 22. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps)

200mV/DIV

TA = 25°C
DATA RATE = 25Mbps

5ns/DIV

= 50pF

C

L

1 CHANNEL

04860-038

Figure 23. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 50Mbps

= 50pF

C

L

1 CHANNEL

400mV/DIV

3ns/DIV

04860-040

Figure 25. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL

1V/DIV

3ns/DIV

04860-041

Figure 26. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
C

= 15pF

L

1 CHANNEL

500mV/DIV

3ns/DIV

04860-039

Figure 24. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps)

Rev. 0 | Page 11 of 20

800mV/DIV

3ns/DIV

04860-042

Figure 27. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps)

ADG3304

TEST CIRCUITS

EN

V

CCA

0.1µF

A

K1

ADG3304

GND

V

CCY

0.1µF

Y

EN

V

CCA

K2

0.1µF

A

ADG3304

V

CCY

0.1µF

Y

K

A

I

OH

I

OL

Figure 28. V

Voltages at Pin A

OH/VOL

GND

04860-043

04860-046

Figure 31. Three-State Leakage Current at Pin Y

EN

V

CCA

0.1µF

K2

V

0.1µF

A

Figure 29. V

EN

CCA

ADG3304

GND

OH/VOL

ADG3304

V

CCY

Y

I

OH

Voltages at Pin Y

0.1µF

V

CCA

0.1µF

K1

I

OL

04860-044

A

K

A

EN

ADG3304

GND

V

CCY

0.1µF

Y

04860-047

Figure 32. EN Pin Leakage Current

V

CCY

0.1µF

EN

V

CCA

ADG3304

V

CCY

A

K

A

GND

Y

CAPACITANCE

METER

04860-045

Figure 30. Three-State Leakage Current at Pin A

A

GND

Figure 33. Capacitance at Pin A

Y

04860-048

Rev. 0 | Page 12 of 20

ADG3304

EN

V

CCA

ADG3304

A

GND

V

CCY

Y

CAPACITANCE

METER

04860-049

Figure 34. Capacitance at Pin Y

A–Y DIRECTION

SIGNAL SOURCE

R

S

50Ω

0.1µF

+

10µF

K1

Z0 = 50Ω

V

CCA

V

A

V

EN

R

T

50Ω

ADG3304

A

EN GND

V

Y

50pF

CCY

0.1µF

+

10µF

1MΩ

V

Y

K2

1MΩ

Y–A DIRECTION

V

+

0.1µF

SIGNAL SOURCE

R

S

50Ω

VY/V

NOTES

1. t

10µF

1MΩ

K1

1MΩ

Z

= 50Ω

0

V

EN

VA/V

Y

90%
VY/V

A

V

EN

VA/V

Y

A

10%

IS WHICHEVER IS LARGER BETWEEN

EN

IN BOTH A-Y AND Y-A DIRECTIONS.

CCA

V

A

15pF

V

EN

R

T

50Ω

t

EN1

t

EN2

Figure 35. Enable Time

ADG3304

A

EN

GND

t

AND

t

EN1

EN2

V

CCY

0.1µF

Y

V

CCA

0V
V

CCA/VCCY

0V
V

CCY/VCCA

0V

V

CCA

0V
V

CCA/VCCY

0V
V

CCY/VCCA

0V

+

10µF

V

Y

K2

04860-050

Rev. 0 | Page 13 of 20

ADG3304

SIGNAL

SOURCE

R

50Ω

S

0.1µF

Z0 = 50Ω

V

50Ω

V

EN

V

CCA

+

10µF

A

R

T

ADG3304

CCY

0.1µF

YA

+

10µF

0.1µF

V

Y

50pF

15pF

EN

V

CCA

+

10µF

V

A

ADG3304

V

CCY

+

V
R

50Ω

Y

T

10µF

Z0 = 50Ω

SIGNAL

SOURCE

R

S

50Ω

0.1µF

YA

GND

V

A

50%

t

P,A-Y

t

F,A-Y

90%

50%

10%

V

Y

Figure 36. Switching Characteristics (A→Y Level Translation)

t

P,A-Y

t

R,A-Y

GND

V

Y

50%

t

V

A

90%

50%

10%

04860-051

P,Y-A

t

F,Y-A

t

P,Y-A

t

R,Y-A

04860-052

Figure 37. Switching Characteristics (Y→A Level Translation)

Rev. 0 | Page 14 of 20

ADG3304

TERMINOLOGY

Table 5.

Symbol Description

V

IHA

V

ILA

V

OHA

V

OLA

C

A

I

LA, HiZ

V

IHY

V

ILY

V

OHY

V

OLY

C

Y

I

LY, HiZ

V

IHEN

V

ILEN

C

EN

I

LEN

t

EN

t

P, A-Y

t

R, A-Y

t

F, A-Y

D

MAX, A-Y

t

SKEW, A-Y

t

PPSKEW, A-Y

t

P, Y-A

t

R, Y-A

t

F, Y-A

D

MAX, Y-A

t

SKEW, Y-A

t

PPSKEW, Y-A

V

CCA

V

CCY

I

CCA

I

CCY

I

HiZA

I

HiZY

Logic input high voltage at Pins A1 to A4.
Logic input low voltage at Pins A1 to A4.
Logic output high voltage at Pins A1 to A4.
Logic output low voltage at Pins A1 to A4.
Capacitance measured at Pins A1 to A4 (EN = 0).
Leakage current at Pins A1 to A4 when EN = 0 (high impedance state at Pins A1 to A4).
Logic input high voltage at Pins Y1 to Y4.
Logic input low voltage at Pins Y1 to Y4.
Logic output high voltage at Pins Y1 to Y4.
Logic output low voltage at Pins Y1 to Y4.
Capacitance measured at Pins Y1 to Y4 (EN = 0).
Leakage current at Pins Y1 to Y4 when EN = 0 (high impedance state at Pins Y1 to Y4).
Logic input high voltage at the EN pin.
Logic input low voltage at the EN pin.
Capacitance measured at EN pin.
Enable (EN) pin leakage current.
Three-state enable time for Pins A1 to A4 /Y1 to Y4.
Propagation delay when translating logic levels in the A→Y direction.
Rise time when translating logic levels in the A→Y direction.
Fall time when translating logic levels in the A→Y direction.
Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the A→Y direction.
Difference in propagation delay between any one channel and the same channel on a different part (under same

driving/loading conditions) when translating in the A

→Y direction.

Propagation delay when translating logic levels in the Y→A direction.
Rise time when translating logic levels in the Y→A direction.
Fall time when translating logic levels in the Y→A direction.
Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the Y→A direction.
Difference in propagation delay between any one channel and the same channel on a different part (under the

same driving/loading conditions) when translating in the Y
V

supply voltage.

CCA

V

supply voltage.

CCY

V

supply current.

CCA

V

supply current.

CCY

V

supply current during three-state mode (EN = 0).

CCA

V

supply current during three-state mode (EN = 0).

CCY

→A direction.

Rev. 0 | Page 15 of 20

ADG3304

THEORY OF OPERATION

The ADG3304 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, V

(V

≤ V

V

CCY

CCA

). These supplies set the logic levels on each

CCY

side of the device. When driving the A pins, the device translates
the V

-compatible logic levels to V

CCA

-compatible logic levels

CCY

available at the Y pins. Similarly, since the device is capable of
bidirectional translation, when driving the Y pins, the V
compatible logic levels are translated to V

-compatible logic

CCA

levels available at the A pins. When EN = 0, the A1 to A4 and
Y1 to Y4 pins are three-stated. When EN is driven high, the
ADG3304 goes into normal operation mode and performs level
translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 38 shows a
simplified block diagram of a bidirectional channel.

V

CCA

6kΩ

U2

U1

P

A

Figure 38. Simplified Block Diagram of an ADG3304 Channel

ONE-SHOT GENERATOR

U4

6kΩ

U3

The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y

→A direction is performed using the inverters

U3 and U4. The one-shot generator detects a rising or falling
edge present on either the A side or the Y side of the channel. It
sends a short pulse that turns on the PMOS transistors (T1–T2)
for a rising edge, or the NMOS transistors (T3–T4) for a falling
edge. This charges/discharges the capacitive load faster, which
results in fast rise and fall times.

→Y or the Y→A

V

CCY

N

and

CCA

-

CCY

T2T1

Y

T3T4

04860-053

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 Ω and a
minimum peak current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3304 level translator is designed to drive CMOS­compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.

ENABLE OPERATION

The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable (EN) pin, as shown in Table 6.

Table 6. Truth Table

EN

0 Hi-Z
1 Normal operation2Normal operation

1

High impedance state.

2

In normal operation, the ADG3304 performs level translation.

Y I/O Pins A I/O Pins

1

Hi-Z

1

2

While EN = 0, the ADG3304 enters into three-state mode. In
this mode, the current consumption from both the V

supplies is reduced, allowing the user to save power, which

V

CCY

CCA

and

is critical, especially on battery-operated systems. The EN input
pin can be driven with either V

CCA

- or V

-compatible logic

CCY

levels.

POWER SUPPLIES

For proper operation of the ADG3304, the voltage applied to
the V
V
sequence is V
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, V
significant increase in the current taken from the V
For optimum performance, the V
decoupled to GND as close as possible to the device.

must be always less than or equal the voltage applied to

CCA

. To meet this condition, the recommended power-up

CCY

first and then V

CCY

may be greater than V

CCA

. The ADG3304 operates

CCA

due to a

CCY

CCA

and V

pins should be

CCY

supply.

CCA

The inputs of the unused channels (A or Y) should be tied to
their corresponding V

rail (V

CC

CCA

or V

) or to GND.

CCY

Rev. 0 | Page 16 of 20

ADG3304

DATA RATE

The maximum data rate at which the device is guaranteed to
operate is a function of the V

CCA

and V
combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to the
device, which meets the V

and VOL levels at the output and

OH

does not exceed the maximum junction temperature (see the
Absolute Maximum Ratings section). Table 7 shows the
guaranteed data rates at which the ADG3304 can operate in
both directions (A
and V

supply combinations.

CCY

→Y or Y→A level translation) for various V

Table 7. Guaranteed Data Rate (Mbps)

V

CCA

1.2 V (1.15 V to 1.3 V)

1.8 V (1.65 V to 1.95 V)

2.5 V (2.3 V to 2.7 V)

3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)

1

The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.

supply voltage

CCY

1

1.8 V

(1.65 V to 1.95 V)

25 30 40 40

- 45 50 50

- - 60 50

- - - 50

- - - -

CCA

2.5 V

(2.3 V to 2.7 V)

V

CCY

3.3 V

(3.0 V to 3.6 V)

5 V

(4.5 V to 5.5 V)

Rev. 0 | Page 17 of 20

ADG3304

APPLICATIONS

The ADG3304 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals to the Y pins. The
ADG3304 can provide level translation in both directions from

→Y or Y→A on all four channels, eliminating the need for a

A
level translator IC for each direction. The internal architecture
allows the ADG3304 to perform bidirectional level translation
without an additional signal to set the direction in which the
translation is made. It also allows simultaneous data flow in
both directions on the same part, for example, when two
channels translate in A→Y direction while the other two
translate in Y→A direction. This simplifies the design by
eliminating the timing requirements for the direction signal
and reduces the number of ICs used for level translation.

Figure 39 shows an application where two microprocessors
operating at 1.8 V and 3.3 V, respectively, can transfer data
simultaneously using two full-duplex serial links, TX1/RX1
and TX2/RX2.

100nF

100nF

100nF 100nF

V

1.8V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

I/O

L1

I/O

L2

I/O

L3

I/O

L4

CS

CCA

A1

ADG3304

A2

A3

A4
EN GND

100nF 100nF

V

CCA

A1

ADG3304

A2

A3

A4
EN GND

Figure 40. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

V

CCY

Y1

Y2

Y3

Y4

V

CCY

Y1

Y2

Y3

Y4

I/O

I/O

I/O

I/O
GND

I/O

I/O

I/O

I/O
GND

H1

H2

H3

H4

H1

H2

H3

H4

3.3V

PERIPHERAL

DEVICE 1

3.3V

PERIPHERAL

DEVICE 2

04860-055

V

V

CCY

1.8V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

TX1

RX1

TX2

RX2

CCA

A1

ADG3304

A2

A3

A4
EN

GND

3.3V

Y1

Y2

Y3

Y4

RX1

TX1

MICROPROCESSOR/

MICROCONTROLLER/

RX2

TX2

GND

DSP

Figure 39. 1.8 V to 3.3 V Level Translation Circuit on

Two Full-Duplex Serial Links

When the application requires level translation between a micro­processor and multiple peripheral devices, the ADG3304 I/O
pins can be three-stated by setting EN = 0. This feature allows
the ADG3304 to share the data buses with other devices without
causing contention issues. Figure 40 shows an application where
a 1.8 V microprocessor is connected to 3.3 V peripheral devices
using the three-state feature.

04860-056

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V

) should be bypassed using low effective series resistance

V

CCY

pin (V

CC

(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V

CCA

and V

pins. The parasitic induc-

CCY

tance of the high speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.

CCA

and

Rev. 0 | Page 18 of 20

ADG3304

OUTLINE DIMENSIONS

5.10

5.00

4.90

BUMP a1

IDENTIFIER

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

Figure 41. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

0.65

1.67

1.61

1.55

TOP VIEW

(BALL SIDE DOWN)

2.07

2.01

1.95

0.59

0.53
SEATING

PLANE

0.50 BSC
BALL PITCH

0.36

0.32

0.28

0.75

0.60

0.45

ABC

1

2

3

4

0.28

0.24

0.20

0.17

0.15

0.13

BOTTOM

VIEW

Figure 42. 12-Bump Wafer Level Chip Scale Package [WLCSP]

(CB-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Branding1Package Option

ADG3304BRUZ
ADG3304BRUZ-REEL
ADG3304BRUZ-REEL7
ADG3304BCBZ-REEL
ADG3304BCBZ-REEL7

1

Branding on these packages is limited to three characters due to space constraints.

2

Z = Pb-free part.

3

Contact your sales representative for availability.

2

2

2, 3

−40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14

−40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14

2

−40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14

−40°C to +85°C 12-Bump Wafer Level Chip Scale Package SDC CB-12

2, 3

−40°C to +85°C 12-Bump Wafer Level Chip Scale Package SDC CB-12

Rev. 0 | Page 19 of 20

ADG3304

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04860–0–1/05(0)

Rev. 0 | Page 20 of 20