Datasheet ADG3300 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

Low Voltage 1.15 V to 5.5 V, 8-Channel

FEATURES

Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current <1 µA
No direction pin

APPLICATIONS

Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communications devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces

Bidirectional Logic Level Translator

ADG3300

FUNCTIONAL BLOCK DIAGRAM

V

CCA

A1

A2

A3

A4

A5 Y5

A6

A7

A8

EN

GND

Figure 1.

V

CCY

Y1

Y2

Y3

Y4

Y6

Y7

Y8

05061-001

GENERAL DESCRIPTION

The ADG3300 is a bidirectional logic level translator that con­tains eight bidirectional channels. It can be used in multivoltage
digital system applications such as data transfer between a low
voltage DSP/controller and a higher voltage device. The internal
architecture allows the device to perform bidirectional logic
level translation without an additional signal to set the direction
of the translation.

The voltage applied to V
the device, while V
operation, V

CCY

must always be less than V

CCA

patible logic signals applied to the A side of the device appear as

-compatible levels on the Y side. Similarly, V

V

CCY

logic levels applied to the Y side of the device appear as V
compatible logic levels on the A side.

The enable pin provides three-state operation of the Y side pins.
When the enable pin (EN) is pulled low, the A1 to A8 pins are

sets the logic levels on the A side of

CCA

sets the levels on the Y side. For proper

CCY

. The V

-com-

CCA

-compatible

CCY

CCA

-

internally pulled down by 6 kΩ resistors, while the Y terminals
are in the high impedance state. The EN pin is referred to V

CCA

supply voltage and driven high for normal operation.

The ADG3300 is available in a compact 20-lead TSSOP package,
and it is guaranteed to operate over the 1.15 V to 5.5 V supply
voltage range and extended −40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

1. Bidirectional level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

4. 20-lead TSSOP package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADG3300

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Tes t Ci rc u it s ..................................................................................... 12

Te r m in o l o g y .................................................................................... 14

Theory of Operation ...................................................................... 15

Level Translator Architecture.................................................... 15

REVISION HISTORY

4/05—Revision 0: Initial Version

Input Driving Requirements..................................................... 15

Output Load Requirements ...................................................... 15

Enable Operation ....................................................................... 15

Power Supplies ............................................................................ 15

Data Rate ..................................................................................... 16

Applications..................................................................................... 17

Layout Guidelines....................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Rev. 0 | Page 2 of 20

ADG3300

www.BDTIC.com/ADI

CCA

3

3

3

≤ V

≤ V

1

= 1.15 V to V

CCA

3

3

3

3

, V

CCY

CCY

, V

CCY

CCY

, GND = 0 V. All specifications T

CCY

V

IHA

IHA

V

ILA

VY = V

OHA

VY = 0 V, IOL = 20 µA, Figure 27 0.4 V

OLA

A,HiZ

V

IHY

V

ILY

OHY

OLY

CY

LY, HiZ

V

IHEN

IHEN

V

ILEN

LEN

C

EN

t

EN

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V V

CCA

0.4 V

EN = 0 4.2 6 8.4 kΩ

V

0.4 V
VA = V
VA = 0 V, IOL = 20 µA, Figure 28 0.4 V
f = 1 MHz, EN = 0, Figure 31 6 pF
VY = 0 V/V

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V V

CCA

0.4 V
VEN = 0 V/V

3 pF
RS = RT = 50 Ω, VA = 0 V/V

CCY

CCA

to T

MIN

, IOH = 20 µA, Figure 27 V

, IOH = 20 µA, Figure 28 V

, EN = 0, Figure 29 ±1 µA

CCY

, VA = 0 V, Figure 30 ±1

CCA

, unless otherwise noted.

MAX

CCA

(A Y),

1 1.8 µs

− 0.3 V

CCA

− 0.4 V

CCA

− 0.4 V

CCA

− 0.4 V

CCY

− 0.4 V

CCY

− 0.3 V

CCA

− 0.4 V

CCA

Figure 32

= 5 V ± 0.5 V

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

= RT = 50 Ω, CL = 50 pF, Figure 33

S

6 10 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 4 ns
3 ns

= RT = 50 Ω, CL = 15 pF, Figure 34

S

4 7 ns
1 3 ns

3 7 ns
50 Mbps
2 3.5 ns
2 ns

= 3.3 V ± 0.3 V

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

= RT = 50 Ω, CL = 50 pF, Figure 33

S

8 11 ns
2 5 ns
2 5 ns
50 Mbps
2 4 ns
4 ns

µA

SPECIFICATIONS

V

= 1.65 V to 5.5 V, V

CCY

Table 1.

Parameter Symbol Conditions Min Typ2Max Unit

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage
V
Input Low Voltage
Output High Voltage V
Output Low Voltage V
Three-State Pull-Down Resistance R

Y Side

Input Low Voltage
Input High Voltage
Output High Voltage V
Output Low Voltage V
Capacitance
Leakage Current I

Enable (EN)

Input High Voltage
V
Input Low Voltage
Leakage Current I

Capacitance
Enable Time

SWITCHING CHARACTERISTICS

3.3 V ± 0.3 V ≤ V
A Y Level Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y A Level Translation

Propagation Delay t
Rise Time t

Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.8 V ± 0.15 V ≤ V
A Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

3

3

3

CCA

Rev. 0 | Page 3 of 20

ADG3300

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ2Max Unit

Y A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V ≤ V

CCA

≤ V

, V

= 3.3 V ± 0.3 V

CCY

CCY

A Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

1.15 V to 1.3 V≤ V

CCA

≤ V

, V

= 1.8 V ± 0.3 V

CCY

CCY

A Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

2.5 V ± 0.2 V ≤ V

CCA

≤ V

, V

= 3.3 V ± 0.3 V

CCY

CCY

A Y Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

Y A Translation

Propagation Delay t
Rise Time t
Fall Time t
Maximum Data Rate D
Channel-to-Channel Skew t
Part-to-Part Skew t

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

R

P, A-Y

R, A-Y

F, A-Y

MAX, A-Y

SKEW, A-Y

PPSKEW, A-Y

R

P, Y-A

R, Y-A

F, Y-A

MAX, Y-A

SKEW, Y-A

PPSKEW, Y-A

= RT = 50 Ω, CL = 15 pF, Figure 34

S

5 8 ns
2 3.5 ns
2 3.5 ns
50 Mbps
2 3 ns
3 ns

= RT = 50 Ω, CL = 50 pF, Figure 33

S

9 18 ns
3 5 ns
2 5 ns
40 Mbps
2 5 ns
10 ns

= RT = 50 Ω, CL = 15 pF, Figure 34

S

5 9 ns
2 4 ns
2 4 ns
40 Mbps
2 4 ns
4 ns

= RT = 50 Ω, CL = 50 pF, Figure 33

S

12 25 ns
7 12 ns
3 5 ns
25 Mbps
2 5 ns
15 ns

= RT = 50 Ω, CL = 15 pF, Figure 34

S

14 35 ns
5 16 ns

2.5 6.5 ns
25 Mbps
3 6.5 ns

23.5 ns

= RT = 50 Ω, CL = 50 pF, Figure 33

S

7 10 ns

2.5 4 ns
2 5 ns
60 Mbps

1.5 2 ns
4 ns

= RT = 50 Ω, CL = 15 pF, Figure 34

S

5 8 ns
1 4 ns
3 5 ns
60 Mbps
2 3 ns
3 ns

Rev. 0 | Page 4 of 20

ADG3300

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ2Max Unit

POWER REQUIREMENTS

Power Supply Voltages V
V
Quiescent Power Supply Current I

I

Three-State Mode Power Supply Current I
I

1

Temperature range is a follows: B version: −40°C to +85°C.

2

All typical values are at TA = 25°C, unless otherwise noted.

3

Guaranteed by design; not subject to production test.

CCA

CCY

CCA

CCY

HiZA

HiZY

V

CCA

≤ V

CCY

1.15 5.5 V

1.65 5.5 V
VA = 0 V/V

= V

V

CCA

VA = 0 V/V
V

= V

CCA

V

= V

CCA

V

= V

CCA

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

= 5.5 V, EN = 0 0.1 5 µA

CCY

= 5.5 V, EN = 0 0.1 5 µA

CCY

CCY

CCY

,

,

0.17 5 µA

0.27 5 µA

Rev. 0 | Page 5 of 20

ADG3300

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

V

to GND −0.3 V to +7 V

CCA

V

to GND V

CCY

Digtal Inputs (A) −0.3 V to (V
Digtal Inputs (Y) −0.3 V to (V
EN to GND −0.3 V to +7 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (4-Layer Board)

20-Lead TSSOP 78°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 260°C

to +7 V

CCA

+ 0.3 V)

CCA

+ 0.3 V)

CCY

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

ADG3300

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A1

V

CCA

A2
A3
A4
A5
A6
A7
A8

10

EN

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin. No. Mnemonic Description

1 A1 Input/Output A1. Referenced to V
2 V

CCA

Power Supply Voltage Input for the A1 to A8 I/O pins (1.15 V ≤ V
3 A2 Input/Output A2. Referenced to V
4 A3 Input/Output A3. Referenced to V
5 A4 Input/Output A4. Referenced to V
6 A5 Input/Output A5. Referenced to V
7 A6 Input/Output A6. Referenced to V
8 A7 Input/Output A7. Referenced to V
9 A8 Input/Output A8. Referenced to V
10 EN Active High Enable Input.
11 GND Ground.
12 Y8 Input/Output Y8. Referenced to V
13 Y7 Input/Output Y7. Referenced to V
14 Y6 Input/Output Y6. Referenced to V
15 Y5 Input/Output Y5. Referenced to V
16 Y4 Input/Output Y4. Referenced to V
17 Y3 Input/Output Y3. Referenced to V
18 Y2 Input/Output Y2. Referenced to V
19 V

CCY

Power Supply Voltage Input for the Y1 to Y8 I/O pins (1.65 V ≤ V
20 Y1 Input/Output Y1. Referenced to V

1

2

3

ADG3300

4

TOP VIEW

(Not to Scale)

5

6

7

8

9

CCA.

.

CCA

.

CCA

.

CCA

.

CCA

.

CCA

.

CCA

.

CCA

.

CCY

.

CCY

.

CCY

.

CCY

.

CCY

.

CCY

.

CCY

.

CCY

20

Y1

19

V

CCY

18

Y2

17

Y3

16

Y4

15

Y5

14

Y6

13

Y7

12

Y8

11

GND

05061-002

< V

CCA

CCY

).

CCY

≤ 5.5 V).

Rev. 0 | Page 7 of 20

ADG3300

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
TA = 25°C

1 CHANNEL

0.9

C

= 50pF

L

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 3. I

10

TA = 25°C
1 CHANNEL

9

= 50pF

C

L

8

7

6

(mA)

5

CCY

I

4

3

2

1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 4. I

3.0
TA = 25°C

1 CHANNEL
C

= 15pF

L

2.5

2.0

(mA)

1.5

CCA

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 5. I

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (A Y Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

= 1.8V

CCY

V

= 3.3V, V

CCA

V

DATA RATE (Mbps)

vs. Data Rate (A Y Level Translation)

CCY

CCA

= 5V

CCY

V

= 1.2V, V

CCA

= 1.8V, V

= 1.8V

CCY

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (Y A Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

CCY

CCY

CCY

= 3.3V

= 3.3V

= 3.3V

05061-003

05061-004

05061-005

3.0
TA = 25°C

1 CHANNEL
C

= 15pF

L

2.5

2.0

V

= 3.3V, V

CCA

(mA)

1.5

CCY

I

1.0

0.5

V

0

0 5 10 15 20 25 30 35 40 45 50

Figure 6. I

vs. Data Rate (Y A Level Translation)

CCY

CCA

DATA RATE (Mbps)

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

1.6
TA =25°C

1 CHANNEL

1.4

V

= 1.2V

CCA

= 1.8V

V

CCY

1.2

1.0

(mA)

0.8

CCY

I

0.6

0.4

0.2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 7. I

vs. Capacitive Load at Pin Y for A Y (1.2 V 1.8 V)

CCY

20Mbps

10Mbps

5Mbps

1Mbps

Level Translation

1.0
TA = 25°C

1 CHANNEL

0.9

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

Figure 8. I

= 1.2V

V

CCA

=1.8V

V

CCY

20Mbps

10Mbps
5Mbps

0

13 23 33 43 53

vs. Capacitive Load at Pin A for Y A (1.8 V 1.2 V)

CCA

CAPACITIVE LOAD (pF)

1Mbps

Level Translation

CCY

= 3.3V

05061-006

05061-007

05061-008

Rev. 0 | Page 8 of 20

ADG3300

www.BDTIC.com/ADI

9

TA = 25°C
1 CHANNEL

8

V

= 1.8V

CCA

V

= 3.3V

CCY

7

6

5

(mA)

4

CCY

I

3

2

1

0

13 23 33 43 53 63 73

Figure 9. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A Y (1.8 V 3.3 V)

CCY

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

Level Translation

5.0

TA = 25°C
1 CHANNEL

4.5

V

= 1.8V

CCA

V

4.0

3.5

3.0

2.5

(mA)

CCA

I

2.0

1.5

1.0

0.5

Figure 10. I

= 3.3V

CCY

0

13 23 33 43 53

CCA

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y A (3.3 V 1.8 V)

Level Translation

12

TA = 25°C
1 CHANNEL

V

= 3.3V

CCA

10

= 5V

V

CCY

8

6

(mA)

CCY

I

4

2

0

13 23 33 43 53 63 73

Figure 11. I

CCY

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V)

Level Translation

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

05061-009

05061-010

05061-011

7

TA = 25°C
1 CHANNEL
V

= 3.3V

6

CCA

V

= 5V

CCY

5

4

(mA)

3

CCA

I

2

1

0

13 23 33 43 53

Figure 12. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y A (5 V 3.3 V)

CCA

50Mbps

30Mbps
20Mbps

10Mbps

5Mbps

05061-012

Level Translation

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME(ns)

3

2

1

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

= 1.8V, V

CCA

V

= 3.3V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

CCY

CCY

= 3.3V

= 5V

05061-013

Figure 13. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation)

4.0
TA = 25°C

1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 1.8V

CCY

= 1.8V, V

= 3.3V, V

CCY

CCY

= 3.3V

= 5V

05061-014

Figure 14. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation)

Rev. 0 | Page 9 of 20

ADG3300

www.BDTIC.com/ADI

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME (ns)

3

2

1

0

13 18 23 28 33 38 43 48 53

Figure 15. Rise Time vs. Capacitive Load at Pin A ( Y A Level Translation)

4.0

3.5

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

Figure 16. Fall Time vs. Capacitive Load at Pin A (Y A Level Translation)

14

12

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63

V

CCA

= 1.2V, V

= 1.8V

CCY

V

= 1.8V, V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 3.3V, V

CCY

= 3.3V

CCY

= 5V

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

V

= 1.2V, V

CCA

13 18 23 28 33 38 43 48 53

= 1.8V

CCY

CAPACITIVE LOAD (pF)

V

CCA

= 1.8V, V

V

CCA

= 3.3V, V

CCY

= 3.3V

CCY

= 5V

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

V

CCA

CAPACITIVE LOAD (pF)

Figure 17. Propagation Delay (t

= 1.8V, V

CCY

V

CCA

V

CCA

= 1.2V, V

= 3.3V

= 3.3V, V

= 1.8V

CCY

= 5V

CCY

73

) vs.

PLH

Capacitive Load at Pin Y (A Y Level Translation)

05061-015

05061-016

05061-017

12

DATA RATE = 50kbps

A

T

= 25°C

1 CHANNEL

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 18. Propagation Delay (t

V

CCA

V

V

CCA

CCA

= 1.2V, V

= 1.8V, V

= 3.3V, V

) vs.

PHL

CCY

Capacitive Load at Pin Y (A Y Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

3

V

= 1.8V, V

PROPAGATION DELAY (ns)

CCA

2

1

0

13 18 23 28 33 38 43 48 53

= 3.3V

CCY

CAPACITIVE LOAD (pF)

Figure 19. Propagation Delay (t

V

V

CCA

CCA

= 1.2V, V

= 3.3V, V

PLH

CCY

CCY

) vs.

Capacitive Load at Pin A (Y A Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

V

3

PROPAGATION DELAY (ns)

2

1

0

13 18 23 28 33 38 43 48 53

CCA

CAPACITIVE LOAD (pF)

Figure 20. Propagation Delay(t

= 1.8V, V

V

CCA

V

CCA

= 3.3V

CCY

= 3.3V, V

= 1.2V, V

= 5V

CCY

PHL

CCY

) vs.

Capacitive Load at Pin A (Y A Level Translation)

= 1.8V

CCY

CCY

= 1.8V

= 5V

= 1.8V

= 3.3V

= 5V

05061-018

05061-019

05061-020

Rev. 0 | Page 10 of 20

ADG3300

www.BDTIC.com/ADI

TA = 25°C
DATA RATE = 25Mbps

= 50pF

C

L

1 CHANNEL

TA = 25°C
DATA RATE = 50Mbps
C

= 15pF

L

1 CHANNEL

200mV/DIV

5ns/DIV

05061-021

Figure 21. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 25Mbps
C

= 50pF

L

1 CHANNEL

400mV/DIV

5ns/DIV

05061-022

Figure 22. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 50Mbps

= 50pF

C

L

1 CHANNEL

400mV/DIV

3ns/DIV

05061-024

Figure 24. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL

1V/DIV

3ns/DIV

05061-025

Figure 25. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
C

= 15pF

L

1 CHANNEL

500mV/DIV

3ns/DIV

05061-023

Figure 23. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps)

Rev. 0 | Page 11 of 20

800mV/DIV

3ns/DIV

05061-026

Figure 26. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps)

ADG3300

www.BDTIC.com/ADI

TEST CIRCUITS

EN

V

CCA

0.1µF

A

K1

ADG3300

GND

V

0.1µF

Y

CCY

V

CCA

K2

0.1µF

A

ADG3300

V

CCY

0.1µF

Y

I

OH

I

OL

Figure 27. V

Voltages at Pin A

OH/VOL

05061-027

A

K

EN

GND

Figure 30. EN Pin Leakage Current

05061-031

EN

V

CCA

0.1µF

K2

A

Figure 28. V

ADG3300

GND

OH/VOL

V

CCY

Y

I

OH

Voltages at Pin Y

0.1µF

EN

V

CCA

A

K1

I

OL

05061-028

ADG3300

GND

Figure 31.Capacitance at Pin Y

V

CCY

Y

CAPACITANCE

METER

05061-033

0.1µF

EN

V

CCA

ADG3300

V

CCY

0.1µF

A

GND

Y

K

A

05061-030

Figure 29. Three-State Leakage Current at Pin Y

Rev. 0 | Page 12 of 20

ADG3300

www.BDTIC.com/ADI

SIGNAL

SOURCE

R

50Ω

S

0.1µF

Z0 = 50Ω

V

50Ω

V

SIGNAL SOURCE

R

S

50Ω

NOTES

+

0.1µF

90%

10%

10µF

K1

Z0 = 50Ω

V

EN

V

A

V

Y

V

EN

V

A

V

Y

1. t

IS WHICHEVER IS LARGER BETWEEN

EN

CCA

A

V

A

V

EN

R

T

50Ω

t

EN1

t

EN2

ADG3300

EN

GND

t

AND

EN1

t

.

EN2

Figure 32. Enable Time

V

EN

V

CCA

+

10µF

A

R

T

ADG3300

CCY

0.1µF

YA

V

Y

50pF

+

10µF

0.1µF

15pF

+

V

A

V

CCA

10µF

V

CCY

+

0.1µF

Y

50pF

V

CCA

0V
V

CCA

0V
V

CCY

0V

V

CCA

0V
V

CCA

0V
V

CCY

0V

10µF

1MΩ

V

Y

K2

1MΩ

05061-034

V

EN

ADG3300

CCY

0.1µF

+

10µF

SIGNAL

SOURCE

Z0 = 50Ω

R

YA

V

Y

R

T

50Ω

S

50Ω

GND

V

A

50%

t

P,A-Y

t

R,A-Y

05061-035

90%
50%

10%

t

V

Y

P,A-Y

t

F,A-Y

Figure 33. Switching Characteristics (A Y Level Translation)

Rev. 0 | Page 13 of 20

GND

V

Y

50%

t

P,Y-A

t

F,Y-A

90%
50%

10%

V

A

Figure 34. Switching Characteristics (Y A Level Translation)

t

P,Y-A

t

R,Y-A

05061-036

ADG3300

www.BDTIC.com/ADI

TERMINOLOGY

Table 4.

Symbol Description

V

IHA

V

ILA

V

OHA

V

OLA

R

A,HiZ

V

IHY

V

ILY

V

OHY

V

OLY

C

Y

I

LY, HiZ

V

IHEN

V

ILEN

C

EN

I

LEN

t

EN

t

P, A-Y

t

R, A-Y

t

F, A-Y

D

MAX, A-Y

t

SKEW, A-Y

t

PPSKEW, A-Y

t

P, Y-A

t

R, Y-A

t

F, Y-A

D

MAX, Y-A

t

SKEW, Y-A

t

PPSKEW, Y-A

V

CCA

V

CCY

I

CCA

I

CCY

I

HiZA

I

HiZY

Logic input high voltage at Pins A1 to A8.
Logic input low voltage at Pins A1 to A8.
Logic output high voltage at Pins A1 to A8.
Logic output low voltage at Pins A1 to A8.
Pull-down resistance measured at Pins A1 to A8 when EN = 0.
Logic input high voltage at Pins Y1 to Y8.
Logic input low voltage at Pins Y1 to Y8.
Logic output high voltage at Pins Y1 to Y8.
Logic output low voltage at Pins Y1 to Y8.
Capacitance measured at Pins Y1 to Y8 (EN = 0).
Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).
Logic input high voltage at the EN pin.
Logic input low voltage at the EN pin.
Capacitance measured at EN pin.
Enable (EN) pin leakage curent.
Three-state enable time for Pins Y1 to Y8.
Propagation delay when translating logic levels in the A Y direction.
Rise time when translating logic levels in the A Y direction.
Fall time when translating logic levels in the A Y direction.
Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the A Y direction.
Difference in propagation delay between any one channel and the same channel on a different part (under the

same driving/loading conditions) when translating logic levels in the A
Propagation delay when translating logic levels in the Y A direction.
Rise time when translating logic levels in the Y A direction.
Fall time when translating logic levels in the Y A direction.
Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions

specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the Y A direction.
Difference in propagation delay between any one channel and the same channel on a different part (under the

same driving/loading conditions) when translating in the Y
V

supply voltage.

CCA

V

supply voltage.

CCY

V

supply current.

CCA

V

supply current.

CCY

V

supply current during three-state mode (EN = 0).

CCA

V

supply current during three-state mode (EN = 0).

CCY

Y direction.

A direction.

Rev. 0 | Page 14 of 20

ADG3300

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADG3300 level translator allows the level shifting necessary
for data transfer in a system where multiple supply voltages are
used. The device requires two supplies, V
V

). These supplies set the logic levels on each side of the

CCY

CCA

and V

device. When driving the A pins, the device translates the V
compatible logic levels to V

-compatible logic levels available

CCY

CCY

(V

CCA

≤

CCA

at the Y pins. Similarly, since the device is capable of bidirectional
translation, when driving the Y pins, the V
levels are translated to V

-compatible logic levels available at

CCA

-compatible logic

CCY

the A pins. When EN = 0, the A1 to A8 are internally pulled
down with 6 kΩ resistors while Y1 to Y8 pins are three-stated.
When EN is driven high, the ADG3300 goes into normal
operation mode and performs level translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3300 consists of eight bidirectional channels. Each
channel can translate logic levels in either the A Y or the Y A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 35 shows a
simplified block diagram of a bidirectional channel.

V

CCA

6kΩ

U2

U1

P

A

ONE-SHOT GENERATOR

V

CCY

T2T1

N

Y

-

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3300, the circuit that
drives the input of an ADG3300 channels should have an output
impedance of less than or equal to 150 Ω and a minimum
current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3300 level translator is designed to drive CMOS­compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3300 outputs
and the load.

ENABLE OPERATION

The ADG3300 provides three-state operation at the Y I/O pins
by using the enable (EN) pin as shown in Table 5.

Table 5. Truth Table

EN

0 Hi-Z
1 Normal operation2Normal operation

1

High impedance state.

2

In normal operation, the ADG3300 performs level translation.

When EN = 0, the ADG3300 enters into three-state mode. In
this mode the current consumption from both the V
V

supplies is reduced, allowing the user to save power, which

CCY

is critical, especially for battery-operated systems. The EN input
pin can be driven with either V
levels.

Y I/O Pins A I/O Pins

1

6 kΩ pull-down to GND

CCA

- or V

-compatible logic

CCY

CCA

2

and

U3

6kΩ

Figure 35. Simplified Block Diagram of an ADG3300 Channel

U4

T3T4

05061-037

The logic level translation in the A Y direction is performed
using a level translator (U1) and an inverter (U2), and the
translation in the Y

A direction is performed using the inverters

U3 and U4. The one-shot generator detects a rising or falling
edge present on either the A side or the Y side of the channel. It
sends a short pulse that turns on the PMOS transistors (T1–T2)
for a rising edge, or the NMOS transistors (T3–T4) for a falling
edge. This charges/discharges the capacitive load faster, which
results in fast rise and fall times.

The inputs of the unused channels (A or Y) should be tied to
their corresponding V

rail (V

CC

CCA

or V

) or to GND.

CCY

Rev. 0 | Page 15 of 20

POWER SUPPLIES

For proper operation of the ADG3300, the voltage applied to
the V
to V
sequence is V
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where
V
nificant increase in the current taken from the V
optimum performance, the V
decoupled to GND as close as possible to the device.

must always be less than or equal to the voltage applied

CCA

. To meet this condition, the recommended power-up

CCY

first and then V

CCY

might be greater than V

CCA

. The ADG3300 operates

CCA

during power-up due to a sig-

CCY

CCA

and V

pins should be

CCY

supply. For

CCA

ADG3300

www.BDTIC.com/ADI

DATA RATE

The maximum data rate at which the device is guaranteed
to operate is a function of the V

CCA

and V
combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to
the device, which meets the V

and VOL levels at the output and

OH

does not exceed the maximum junction temperature (see
Tabl e 2) . Ta b le 6 sho w s t h e g u ar a nte e d d a ta r ate s at w hic h th e
ADG3300 can operate in both directions (A
translation) for various V

CCA

and V

CCY

Table 6. Guaranteed Data Rate (Mbps)

V

CCA

1.2 V (1.15 V to 1.3 V) 25 30 40 40

1.8 V (1.65 V to 1.95 V) - 45 50 50

2.5 V (2.3 V to 2.7 V) - - 60 50

3.3 V (3.0 V to 3.6 V) - - - 50
5 V (4.5 V to 5.5 V) - - - -

1

The load capacitance used is 50 pF when translating in the A Y direction and 15 pF when translating in the Y A direction.

supply voltage

CCY

Y and Y A level

supply combinations.

1

1.8 V

(1.65 V to 1.95 V)

2.5 V

(2.3 V to 2.7 V)

V

CCY

3.3 V

(3.0 V to 3.6 V)

5 V

(4.5 V to 5.5 V)

Rev. 0 | Page 16 of 20

ADG3300

www.BDTIC.com/ADI

APPLICATIONS

The ADG3300 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3300 can provide level translation in both
directions from A

Y and Y A on all eight channels, eliminating

the need for a level translator IC for each direction. The internal
architecture allows the ADG3300 to perform bidirectional level
translation without an additional signal to set the direction of
the translation. It also allows simultaneous data flow in both
directions on the same part, for example, four channels translate
in the A Y direction while the other four translate in the Y A
direction. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.

Figure 36 shows an application where a 1.8 V microprocessor
can read or write data to or from a 3.3 V peripheral device using
an 8-bit bus.

100nF

Y1

V

CCY

Y2

Y3

Y4

Y5

Y6

Y7

Y8A8

I/OH1

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

2

H

3

H

4

H

PERIPHERAL

5

H

6

H

7

H

8

H

3.3V

DEVICE

1.8V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit

I/OL1

I/O

I/O

I/O

I/OL5

I/O

I/O

I/O

100nF

A1
V

CCA

2

L

3

L

4

L

6

L

7

L

8

L

A2

A3

A4

ADG3300

A5

A6

A7

EN GND

When the application requires level translation between a
microprocessor and multiple peripheral devices, the ADG3300
Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0.
This feature allows the ADG3300 to share the data buses with

05061-038

other devices without causing contention issues. Figure 37 shows
an application where a 3.3 V microprocessor is connected to

1.8 V peripheral devices using the three-state feature.

100nF 100nF

3.3V

MICROPROCESSOR/

MICROCONTROLLER/

DSP

GND

CS

I/O

1

H

I/OH2
I/O

3

H

I/O

4

H

5

I/O

H

I/O

6

H

I/O

7

H

8

I/O

H

100nF 100nF

Y1
V

CCY

Y2
Y3

ADG3300

Y4
Y5
Y6
Y7
Y8

Y1
V

CCY

Y2
Y3

ADG3300

Y4
Y5
Y6
Y7
Y8
GND

A1

V

CCA

A2
A3
A4
A5
A6
A7
A8

ENGND

A1

V

CCA

A2
A3
A4
A5
A6
A7
A8
EN

I/OL1

I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

I/OL1

I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

2

L

3

L

4

L

5

L

6

L

7

L

8

L

2

L

3

L

4

L

5

L

6

L

7

L

8

L

1.8V

PERIPHERAL

DEVICE 1

1.8V

PERIPHERAL

DEVICE 2

Figure 37. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board
layout is important in the overall circuit performance. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V
V

) should be bypassed using low effective series resistance

CCY

pin (V

CC

(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V

CCA

and V

pins. The parasitic induc-

CCY

tance of the high speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length
of the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.

CCA

and

05061-039

Rev. 0 | Page 17 of 20

ADG3300

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARITY

0.10

20

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 38 . 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3300BRUZ
ADG3300BRUZ-REEL
ADG3300BRUZ-REEL7

1

Z = Pb-free part.

1

1

−40°C to +85°C TSSOP RU-20

−40°C to +85°C TSSOP RU-20

1

−40°C to +85°C TSSOP RU-20

Rev. 0 | Page 18 of 20

ADG3300

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 19 of 20

ADG3300

www.BDTIC.com/ADI

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05061–0–4/05(0)

Rev. 0 | Page 20 of 20