Datasheet ADG3257 Datasheet (ANALOG DEVICES)

High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux

A

2A3A

4A

www.BDTIC.com/ADI

FEATURES

100 ps propagation delay through the switch
2 Ω switches connect inputs to outputs
Data rates up to 933 Mbps
Single 3.3 V/5 V supply operation
Level translation operation
Ultralow quiescent supply current (1 nA typical)

3.5 ns switching
Switches remain in the off state when power is off
Standard 3257 type pinout

APPLICATIONS

Bus switching
Bus isolation
Level translation
Memory switching/interleaving

GENERAL DESCRIPTION

The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low on
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional
ground bounce noise.

The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Tabl e 1. These switches
are bidirectional when on. In the off state, signal levels are blocked
up to the supplies. When the power supply is off, the switches
remain in the off state, isolating Port A and Port B.

This bus switch is suited to both switching and level translation
applications. It can be used in applications requiring level trans­lation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally,
with a diode connected in series with 5 V V
may also be used in applications requiring 5 V to 3.3 V level
translation.

Table 1. Truth Table

BE

S Function

H X Disable
L L A = B1
L H A = B2

, the ADG3257

DD

(4-Bit, 1 of 2) Bus Switch

FUNCTIONAL BLOCK DIAGRAM

1

LOGIC

BE

Figure 1.

PRODUCT HIGHLIGHTS

1. 0.1 ns propagation delay through switch.

2. 2 Ω switches connect inputs to outputs.

3. Bidirectional operation.

4. Ultralow power dissipation.

5. 16-lead QSOP package.

S

ADG3257

1B

1

1B

2

2B

1

2B

2

3B

1

3B

2

4B

1

4B

2

02914-001

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no re­sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2008 Analog Devices, Inc. All rights reserved.

ADG3257

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

REVISION HISTORY

03/08—Rev. D to Rev. E

Updated Format .................................................................... Universal

Changes to Features .............................................................................1

Changes to General Description .......................................................1

Changes to Absolute Maximum Ratings ..........................................5

Changes to Pin Configuration and Function Descriptions ...........6

Changes to Test Circuits .....................................................................9

Changes to Ordering Guide ...............................................................11

11/04—Rev. C to Rev. D

Changes to Specifications ...................................................................2

Changes to Ordering Guide ...............................................................4

04/03—Rev. A to Rev. B

Updated Outline Dimensions ............................................................8

06/02—Rev. 0 to Rev. A

Edits to Features ...................................................................................1

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Test Circuits ........................................................................................9

Applications Information .............................................................. 10

Mixed Voltage Operation, Level Translation .......................... 10

Memory Switching ..................................................................... 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. E | Page 2 of 12

ADG3257

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SPECIFICATIONS

VCC = 5.0 V ± 10%, GND = 0 V. All specifications T

Table 2.

Parameter1 Symbol Conditions2

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V
Input Low Voltage V

2.4 V

INH

−0.3 +0.8 V

INL

Input Leakage Current II 0 ≤ VIN ≤ 5.5 V ±0.01 ±1 μA
Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
On State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
Maximum Pass Voltage4 VP VIN = VCC = 5 V, IO = −5 μA 3.9 4.2 4.4 V

CAPACITANCE4

A Port Off Capacitance CA OFF f = 1 MHz 7 pF
B Port Off Capacitance CB OFF f = 1 MHz 5 pF
A, B Port On Capacitance CA, CB ON f = 1 MHz 11 pF
Control Input Capacitance CIN f = 1 MHz 4 pF

4

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, tPD t

, t

PHL

Propagation Delay Matching6 VA = 0 V, CL = 50 pF 0.0075 0.035 ns

t

Bus Enable Time BE to A or B
Bus Disable Time BE to A or B

, t

PZH

t

, t

PHZ

Bus Select Time S to A or B

Enable t
Disable t

SEL_EN

SEL_DIS

Maximum Data Rate VA = 2 V p-p 933 Mbps

DIGITAL SWITCH

On Resistance RON VA = 0 V
I
I
V
I
I

On-Resistance Matching ΔRON VA = 0 V, IO = 48 mA, 15 mA, 8 mA 0.15 Ω
POWER REQUIREMENTS

VCC 3.0 5.5 V

Quiescent Power Supply Current ICC Digital inputs = 0 V or VCC 0.001 1 μA

4, 7

Increase in ICC per Input

1

Temperature range is: Version B: –40°C to +85°C.

2

See Test Circuits section.

3

All typical values are at TA = 25°C, unless otherwise noted.

4

Guaranteed by design, not subject to production test.

5

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage

source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

6

Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.

7

This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute

no significant ac or dc currents as they transition.

ΔICC V

MIN

to T

, unless otherwise noted.

MAX

B Version

5

VA = 0 V, CL = 50 pF 0.10 ns

PLH

CL = 50 pF, RL = 500 Ω 1 5 7.5 ns

PZL

CL = 50 pF, RL = 500 Ω 1 3.5 7 ns

PLZ

CL = 50 pF, RL = 500 Ω 8 12 ns

CL = 50 pF, RL = 500 Ω 5 8 ns

= 48 mA, 15 mA, 8 mA, TA = 25°C 2 4 Ω

O

= 48 mA, 15 mA, 8 mA 5 Ω

O

= 2.4 V

A

= 48 mA, 15 mA, 8 mA, TA = 25°C 3 6 Ω

O

= 48 mA, 15 mA, 8 mA 7 Ω

O

= 5.5 V, one input at 3.0 V; others at VCC or GND 200 μA

CC

Unit Min Typ3Max

Rev. E | Page 3 of 12

ADG3257

www.BDTIC.com/ADI

VCC = 3.3 V ± 10%, GND = 0 V. All specifications T

Table 3.

Parameter1 Symbol Conditions2

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V
Input Low Voltage V

INH

INL

Input Leakage Current II 0 ≤ VIN ≤ 3.6 V ±0.01 ±1 μA
Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
On State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
Maximum Pass Voltage4 VP VIN = VCC = 3.3 V, IO = −5 μA 2.3 2.6 2.8 V

CAPACITANCE4

A Port Off Capacitance CA OFF f = 1 MHz 7 pF
B Port Off Capacitance CB OFF f = 1 MHz 5 pF
A, B Port On Capacitance CA, CB ON f = 1 MHz 11 pF
Control Input Capacitance CIN f = 1 MHz 4 pF

SWITCHING CHARACTERISTICS4

Propagation Delay A to B or B to A, tPD t

PHL

Propagation Delay Matching6 VA = 0 V, CL = 50 pF 0.01 0.04 ns
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B

t

PZH

t

PHZ

Bus Select Time S to A or B

Enable t
Disable t

SEL_EN

SEL_DIS

Maximum Data Rate VA = 2 V p-p 933 Mbps

DIGITAL SWITCH

On Resistance RON V
V
V
V

On-Resistance Matching ΔR

ON

POWER REQUIREMENTS

VCC 3.0 5.5 V

Quiescent Power Supply Current ICC Digital inputs = 0 V or VCC 0.001 1 μA

Increase in ICC per Input

1

Temperature range is: Version B: −40°C to +85°C.

2

See Test Circuits section.

3

All typical values are at TA = 25°C, unless otherwise noted.

4

Guaranteed by design, not subject to production test.

5

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage

source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven sid e.

6

Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.

7

This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute

no significant ac or dc currents as they transition.

4, 7

ΔICC V

to T

MIN

, unless otherwise noted.

MAX

B Version

Unit Min Typ3Max

2.0 V

−0.3 +0.8 V

5

, t

VA = 0 V, CL = 50 pF 0.10 ns

PLH

, t

CL = 50 pF, RL = 500 Ω 1 5.5 9 ns

PZL

, t

CL = 50 pF, RL = 500 Ω 1 4.5 8.5 ns

PLZ

CL = 50 pF, RL = 500 Ω 8 12 ns

CL = 50 pF, RL = 500 Ω 6 9 ns

= 0 V, IO = 15 mA, 8 mA, TA = 25°C 2 4 Ω

A

= 0 V, Io = 15 mA, 8 mA 5 Ω

A

= 1 V, IO = 15 mA, 8 mA, TA = 25°C 4 7 Ω

A

= 1 V, Io = 15 mA, 8 mA 8 Ω

A

V

= 0 V, IO = 15 mA, 8 mA 0.2 Ω

A

= 3.3 V, one input at 3.0 V; others at VCC or GND 200 μA

CC

Rev. E | Page 4 of 12

ADG3257

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VCC to GND −0.3 V to +6 V
Digital Inputs to GND −0.3 V to +6 V
DC Input Voltage −0.3 V to +6 V
DC Output Current 100 mA
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
QSOP Package

θJA Thermal Impedance 149.97°C/W
Lead Soldering

Lead Temperature, Soldering (10 sec) 300°C

IR Reflow, Peak Temperature (<20 sec) 220°C
Soldering (Pb-Free)

Reflow, Peak Temperature 260(+0/−5)°C

Time at Peak Temperature 20 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational sec­tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 5 of 12

ADG3257

G

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

S

2

1B

1

3

1B

ADG3257

2

TOP VIEW

4

1A

(Not to Scale)

5

2B

1

6

2B

2

7

2A 3B

8

ND 3A

16

V

CC

15

BE

14

4B

1

13

4B

2

12

4A

11

3B

1

10

2

9

02914-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 S Port Select.
2, 3, 5, 6, 10, 11, 13, 14 1B1, 1B2, 2B1, 2B2, 3B2, 3B1, 4B2, 4B1 Port B, Inputs or Outputs.
4, 7, 9, 12 1A, 2A, 3A, 4A Port A, Inputs or Outputs.
8 GND Negative Power Supply.
15

BE

Output Enable (Active Low).

16 VCC Positive Power Supply.

Rev. E | Page 6 of 12

ADG3257

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TYPICAL PERFORMANCE CHARACTERISTICS

20

TA = 25°C

16

12

(Ω)

ON

R

8

4

0

012345

VCC = 4.5V

VCC = 5.0V

V

A/VB

(V)

VCC = 5.5V

914-003
02

Figure 3. On Resistance vs. Input Voltage

20

TA = 25°C

16

VCC = 3.0V

12

(Ω)

ON

R

8

4

VCC = 2.7V

VCC = 3.3V

20

VCC = 3V

15

(Ω)

10

ON

R

5

0

0 0.5 1.0 1.5 2.0 3.02.5

+25°C

+85°C

–40°C

VA/VB (V)

Figure 6. On Resistance vs. Input Voltage for Different Temperatures

10m

1m

100µ

10µ

CURRENT (A)

1µ

100n

VCC = 5V

VCC = 3V

TA = 25°C

02914-006

0

0 0.5 1.0 1.5 2.0 3.02.5

VA/VB (V)

Figure 4. On Resistance vs. Input Voltage

20

VCC = 5V

15

(Ω)

10

ON

R

5

0

012345

+25°C

+85°C

V

A/VB

–40°C

(V)

Figure 5. On Resistance vs. Input Voltage for Different Temperatures

02914-004

00502914-

Rev. E | Page 7 of 12

10n

0.1 1 10 100 1k 10k

FREQUENCY (kHz)

Figure 7. ICC vs. Enable Frequency

5

TA = 25°C

4

3

2

OUTPUT VOLTAGE (V)

1

0

012345

INPUT VOLTAG E (V)

VCC = 5.5V

VCC = 4.5V

Figure 8. Maximum Pass Voltage

02914-007

VCC = 5.0V

02914-008

ADG3257

www.BDTIC.com/ADI

3.6
TA = 25°C

3.0

2.0

OUTPUT VOLTAGE (V)

1.0

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

INPUT VOLTAG E (V)

Figure 9. Maximum Pass Voltage

VCC = 3.6V

VCC = 3.0V

VCC = 3.3V

40mV/DIV
180ps/DIV

02914-009

VCC = 5V

= 2V p-p

V

IN

933MBPS

20dB ATTENUATION

= 25°C

T

A

02914-011

Figure 11. 933 Mbps Eye Diagram

40mV/DIV
267ps/DIV

VCC = 5V

= 2V p-p

V

IN

622MBPS

20dB ATTENUATION

= 25°C

T

A

2914-010

Figure 10. 622 Mbps Eye Diagram

Rev. E | Page 8 of 12

ADG3257

V

V

www.BDTIC.com/ADI

TEST CIRCUITS

CC

V

PULSE

GENERATOR

1

PULSE GENERATOR FOR ALL PULSES:

2

CL = INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.

3

RT IS THE TERMINATION RESISTOR; SHOULD BE EQUALTO Z

PULSE GENERATOR.

IN

1

3

R

T

DUT

V

OUT

2

C

L

t

2.5ns,

t

<

F

<

R

Figure 12. Load Circuit

SWITCH INPUT

t

PHL

OUTPUT

t

PLH

2.5ns.

OUT

S1

R

L

R

L

OF THE

IH

V

T

0V

V

OH

V

T

V

OL

2 × V

OPEN

GND

2914-013

CC

2914-012

Table 6. Switch S1 Condition

Test S1

t

, t

Open

PLH

PHL

t

, t

2 × VCC

PLZ

PZL

t

, t

GND

PHZ

PZH

t

Open

SEL

Table 7. Test Conditions

Symbol VCC = 5 V ± 10% VCC = 3.3 V ± 10% Unit

RL 500 500 Ω
ΔV 300 300 mV
CL 50 50 pF

CONTROL INPUTS

OUTPUT

S1 @ 2V

OUTPUT

S1 @ 2V

Figure 13. Propagation Delay

DISABLE

t

PHZ

t

PLZ

LOW

CC

CC

ENABLE

t

t

PZL

PZH

V

CC

V

T

V

T

0V

Figure 14. Select, Enable, and Disable Times

V

IH

V

T

0V

V

CC

VOL + ΔV

V

OL

V

OH

VOH – ΔV

0V

02914-014

Rev. E | Page 9 of 12

ADG3257

V

V

V

V

3.3V

2.5V

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APPLICATIONS INFORMATION

MIXED VOLTAGE OPERATION, LEVEL TRANSLATION

Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3.3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
as shown in Figure 15.

= 5

CC

BE

3.3V CPU/DSP/

MICROPROCESSOR/

MEMORY

3.3V

5V

3.3V 3.3V

Figure 15. Level Translation Between 5 V and 3.3 V Devices

The diode drops the internal gate voltage down to 4.3 V. The
bus switch limits the voltage present on the output to

V

− External Diode Drop = VTH

CC

Therefore, assuming a diode drop of 0.7 V and a V
output voltage is limited to 3.3 V with a logic high.

OUT

3.3V

SWITCH

OUTPUT

0V

Figure 16. Input Voltage to Output Voltage

SWITCH

INPUT

5V SUPPLY

5V

5V MEMORY

V

IN

02914-016

5V I/O

TH

4-015
0291

of 1 V, the

Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need for
an external diode. The internal V
V

= 3.3 V the bus switch limits the output voltage to

CC

− 1 V = 2.3 V

V

CC

drop is 1 V, so with a

TH

2.5V

OUT

SWITCH

OUTPUT

0V

SWITCH

INPUT

3.3V SUPPL Y

3.3V

V

IN

3.3V

2.5V

ADG3257

2.5V

Figure 17. 3.3 V to 2.5 V Level Translation Using the ADG3257 Bus Switch

MEMORY SWITCHING

This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 18 illustrates the
ADG3257 in such an application.

SDRAM NO. 1

SDRAM NO. 2

SDRAM NO. 7

SDRAM NO. 8

LOGIC

BE

S

Figure 18. Allows Additional Memory Modules Without Added Drive or Delay

02914-018

02914-017

Rev. E | Page 10 of 12

ADG3257

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OUTLINE DIMENSIONS

0.197

0.193

0.189

0.012

0.008

9

8

0.158

0.154

0.150

0.069

0.053

SEATING
PLANE

0.244

0.236

0.228

0.010

0.006

8°
0°

0.050

0.016

0.065

0.049

0.010

0.004

COPLANARITY

0.004

16

1

PIN 1

0.025
BSC

COMPLIANT TO JEDEC STANDARDS MO-137-AB

Figure 19. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3257BRQ –40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADG3257BRQ-REEL –40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADG3257BRQ-REEL7 –40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADG3257BRQZ1 –40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADG3257BRQZ-REEL1 –40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADG3257BRQZ-REEL7

1

Z = RoHS Compliant Part.

1

–40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16

Rev. E | Page 11 of 12

ADG3257

www.BDTIC.com/ADI

NOTES

©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02914-0-3/08(E)

Rev. E | Page 12 of 12