Datasheet ADG3249 Datasheet (Analog Devices)

2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch

ADG3249

FEATURES
225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports
Data Rate 1.244 Gbps

2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
8-Lead SOT-23 Package

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Docking Stations
Memory Switching
Analog Switch Applications

GENERAL DESCRIPTION

The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multi­plexer/demultiplexer bus switch. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
input to be connected to the output without additional propaga­tion delay or generating additional ground bounce noise.

Each switch of the ADG3249 conducts equally well in both direc­tions when on. The ADG3249 exhibits break-before-make
switching action, preventing momentary shorting when switch­ing channels.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from

3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device
is operated from 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating pin (SEL) is included. When SEL is low, V

CC

is
reduced internally, allowing for level translating between 3.3 V
inputs and 1.8 V outputs.

The ADG3249 is available in a tiny 8-lead SOT-23 package.

FUNCTIONAL BLOCK DIAGRAM

ADG3249

A0

A1

PRODUCT HIGHLIGHTS

CONTROL

LOGIC

IN

B

EN

1. 3.3 V or 2.5 V supply operation.

2. Extremely low propagation delay through switch.

3. 4.5 Ω switches connect inputs to outputs.

4. Tiny SOT-23 package.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADG3249–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

unless otherwise noted.)

MIN

to T

MAX

,

B Version

Parameter Symbol Conditions Min Typ2Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I

INH

V

INH

INL

V

INL

I

OZ

ON State Leakage Current 0 ≤ A, B ≤ V
Maximum Pass Voltage V

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 µA

0 ≤ A, B ≤ V

CC

CC

± 0.01 ± 1 µA
± 0.01 ±1 µA

VA/VB = VCC = SEL = 3.3 V, IO = –5 µA 2.0 2.5 2.9 V

= VCC = SEL = 2.5 V, IO= –5 µA1.51.82.1V

V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA 1.5 1.8 2.1 V

CAPACITANCE

A Port Off Capacitance CA OFF f = 1 MHz; EN = V
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Break-before-Make Time t
Transition Time t

Maximum Data Rate V
Channel Jitter V

3

OFF f = 1 MHz; EN = V

B

, CB ON f = 1 MHz 8.5 pF

A

IN, CSEL

C

EN

3

4

t

PHL

t

PZH

t

PHZ

t

PZH

t

PHZ

t

PZH

t

PHZ

BBM

TRANS

, t

, t
, t
, t
, t
, t
, t

5

PD

6

6

6

6

6

6

f = 1 MHz 4 pF
f = 1 MHz 6.5 pF

CL = 50 pF, VCC = SEL = 3 V 0.225 ns

PLH

VCC = 3.0 V to 3.6 V; SEL = V

PZL

VCC = 3.0 V to 3.6 V; SEL = V

PLZ

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 3.2 4.5 ns

PZL

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 4.5 7.7 ns

PLZ

VCC = 2.3 V to 2.7 V; SEL = V

PZL

VCC = 2.3 V to 2.7 V; SEL = V

PLZ

RL = 510 Ω, CL = 50 pF 5 10 ns
RL = 510 Ω, CL = 50 pF; SEL = V
R

= 510 Ω, CL = 50 pF; SEL = 0 V 15 22 ns

L

= SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps

CC

= SEL = 3.3 V; VA/VB = 2 V 45 ps p-p

CC

CC

CC

CC

CC

CC

CC

1 3.5 4.8 ns
1 5.5 8.2 ns

1 3.5 4.6 ns
14 5.8 ns

CC

3.5 pF

4.5 pF

5ps

16 29 ns

DIGITAL SWITCH

On Resistance R

On Resistance Matching ⌬R

ON

ON

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 Ω

= 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 12 28 Ω

V

CC

V

= 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 Ω

CC

= 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 9 18 Ω

V

CC

= 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA 5 8 Ω

V

CC

V

= 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 12 Ω

CC

VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA 0.1 0.5 Ω
VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA 0.1 0.5 Ω

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Typical values are at 25°C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

7

⌬I

CC

CC

Digital Inputs = 0 V or VCC; SEL = V
Digital Inputs = 0 V or V

; SEL = 0 V 0.1 0.2 mA

CC

CC

VCC = 3.6 V, EN = 3.0 V; SEL = VCC; IN = V

2.3 3.6 V

0.01 1 µA

CC

0.15 8 µA

REV. 0–2–

ADG3249

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

ADG3249

GND

A1

EN

IN

SEL

V

CC

A0

B

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W

␪

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

Table II. Truth Table

EN IN SEL* FUNCTION

HXX Disconnect
LLLA0 = B; 3.3 V to 1.8 V Level Shifting

LLHA0 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
LHLA1 = B; 3.3 V to 1.8 V Level Shifting
LHHA1 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting

*SEL = 0 V only when VDD = 3.3 V  10%

PIN CONFIGURATION

8-Lead SOT-23

Table I. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN Enable (Active Low)
2A0 Port A0, Input or Output
3A1 Port A1, Input or Output
4 GND Ground Reference
5B Port B, Input or Output
6INChannel Select

7 SEL Level Translation Select
8V

CC

Positive Power Supply Voltage

ORDERING GUIDE

Model Temperature Range Package Description Package Branding

ADG3249BRJ-R2 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA
ADG3249BRJ-REEL –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA
ADG3249BRJ-REEL7 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3249 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADG3249

TERMINOLOGY

V

CC

Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V

INH

V

INL

I

I

I

OZ

I

OL

V

P

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when

the switch input voltage is equal to the supply voltage.
R

ON

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified

amount of current through the switch.
⌬R

ON

C

OFF OFF Switch Capacitance.

X

C

ON ON Switch Capacitance.

X

C

, C

SEL

, C

IN

I

CC

ON Resistance Match between Any Two Channels, i.e., RON max to R

Control Input Capacitance. This consists of IN, SEL, and EN.

EN

ON

min.

Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.

It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬I
t

t

PLH

PZH

CC

, t

, t

PHL

PZL

Extra power supply current component for the EN control input when the input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

R

× CL, where CL is the load capacitance.

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on

in response to the control signal, EN.
t

PHZ

, t

PLZ

Bus Disable Times. These are the time taken to place the switch in the high impedance OFF state in response to the

control signal. They are measured as the time taken for the output voltage to change by V

from the original

⌬

quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable

and disable times.)
t

BBM

t

TRANS

On or Off Time. Measured between the 90% points of both switches when switching fom one to another.

Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the

OUT signal.
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

REV. 0–4–

Typical Performance Characteristics–ADG3249

)



(

ON

R

40

35

30

25

20

15

10

5

0

T

= 25C

A

SEL = V

0 0.5

CC

1.5 2.5 3.5
VA/VB (V

)

V

= 3V

CC

VCC = 3.3V

VCC = 3.6V

3.02.01.0

TPC 1. On Resistance vs.
Input Voltage

20

= 3.3V

V

CC

SEL = V

CC

15

()

10

ON

R

5

0

0 0.5

85C

40C

VA/VB (V)

25C

1.5

2.01.0

TPC 4. On Resistance vs. Input
Voltage for Different Temperatures

40

35

30

)

25



(

ON

20

R

15

10

TA = 25C

SEL = V

5

0

0 0.5

CC

VCC = 2.3V

VCC = 2.5V

VCC = 2.7V

1.5 2.5

VA/VB (V

)

3.02.01.0

TPC 2. On Resistance vs.
Input Voltage

15

= 2.5V

V

CC

SEL = V

CC

10

85C

()

ON

R

5

0

0 0.5

25C

VA/VB(V)

40C

1.0

TPC 5. On Resistance vs. Input
Voltage for Different Temperatures

1.2

)



(

ON

R

40

35

30

25

20

15

10

5

0

TA = 25C
SEL = 0V

0 0.5

1.0 2.0 3.0

VCC = 3V

= 3.3V

V

CC

VCC = 3.6V

1.5 2.5
VA/VB (V

)

TPC 3. On Resistance vs.
Input Voltage

(V)

V

3.0

2.5

2.0

1.5

OUT

1.0

0.5

TA = 25C
SEL = V
I

0

0 0.5

CC

= –5A

O

1.0 2.0 3.0

VCC = 3.6V

VCC = 3V

1.5 2.5 3.5
V

(V)

A/VB

TPC 6. Pass Voltage vs. V

3.5

VCC = 3.3V

CC

2.5

T

= 25C

A

SEL = V
I

O

CC

= –5A

1.0 2.0 3.0
VA/VB (V)

2.0

1.5

(V)

OUT

V

1.0

0.5

0

0 0.5

TPC 7. Pass Voltage vs. V

REV. 0

VCC = 2.7V

VCC = 2.5V

VCC = 2.3V

1.5 2.5

CC

2.5

TA = 25C
SEL = 0V

2.0

I

= –5A

O

1.5

(V)

OUT

V

1.0

0.5

0

0 0.5

1.0 2.0 3.0

VCC = 3V

1.5 2.5
VA/VB (V)

TPC 8. Pass Voltage vs. V

–5–

VCC = 3.6V

VCC = 3.3V

CC

3.5

300

TA = 25C

250

VCC = SEL = 3.3V

200

VCC = 3.3V

SEL = 0V

150

(A)

CC

I

100

50

0

051015 20 25 30 35 40 45

ENABLE FREQUENCY (MHz)

VCC = SEL = 2.5V

TPC 9. ICC vs. Enable Frequency

50

ADG3249

(

)

0

(

)

0

5

3.0
TA = 25C
V

= 0V

A

2.5

EN = 0

(V)

V

2.0

1.5

OUT

1.0

0.5

0

0.02 0.04 0.06 0.08 0.100

VCC = 3.3V; SEL = 0V

VCC = SEL = 3.3V

VCC = SEL = 2.5V

I

(A)

O

TPC 10. Output Low Characteristic

1

0

–1

–2

–3

–4

TA = 25C

–5

V

= 3.3V/2.5V

CC

ATTENUATION (dB)

SEL = V

–6

–7

–8

0.03 0.1 1.0

CC

VIN = 0dBm
N/W ANALYZER:
R

= RS = 50

L

FREQUENCY

10 100

100

MHz

TPC 13. Bandwidth vs. Frequency

3.0
TA = 25C
V

= V

A

CC

EN = 0

VCC = SEL = 3.3V

VCC = SEL = 2.5V

VCC = 3.3V; SEL = 0V

–0.08 –0.06 –0.04 –0.02 0

IO (A)

(V)

V

OUT

2.5

2.0

1.5

1.0

0.5

–0.10

0

TPC 11. Output High Characteristic

0

TA = 25C

–10

V

= 3.3V/2.5V

CC

SEL = V

–20

–30

–40

–50

–60

–70
ATTENUATION (dB)

–80

–90

–100

0.03 0.1 1.0

CC

VIN = 0dBm
N/W ANALYZER:
R

= RS = 50

L

FREQUENCY

10 100

100

MHz

TPC 14. Crosstalk vs. Frequency

0

TA = 25C
SEL = V

–0.2

–0.4

–0.6

(pC)

INJ

–0.8

Q

–1.0

–1.2

–1.4

0

CC

ON = OFF
CL = INF.

VCC = 3.3V

0.5 1.0 1.5 2.52.0 3.0 3.

VCC = 2.5V

V

A/VB

(V)

TPC 12. Charge Injection vs.
Source Voltage

0

TA = 25C

–10

V

= 3.3V/2.5V

CC

SEL = V

–20

–30

–40

–50

–60

–70
ATTENUATION (dB)

–80

–90

–100

0.03 0.1 1.0

CC

VIN = 0dBm
N/W ANALYZER:
R

= RS = 50

L

FREQUENCY (MHz)

10 1000100

TPC 15. Off Isolation vs.
Frequency

6

DISABLE

5

DISABLE

4

ENABLE

3

TIME (ns)

ENABLE

2

1

0
–40 –20 0

TEMPERATURE (C)

VCC = SEL = 3.3V

VCC = 3.3V, SEL = 0V

20 806040

TPC 16. Enable/Disable Time
vs. Temperature

4.0

3.5

DISABLE

3.0

ENABLE

2.5

2.0

TIME (ns)

1.5

1.0

0.5

0

–40 –20 0

TEMPERATURE (C)

VCC = SEL = 2.5V

20 806040

TPC 17. Enable/Disable Time
vs. Temperature

100

VCC = SEL = 3.3V

90

= 1.5V p-p

V

IN

20dB ATTENUATION

80

70

60

50

40

JITTER (ps p-p)

30

20

10

0

0.7 0.9 1.1 1.3 1.5 1.7 1.9

0.5
DATA RATE (Gbps)

TPC 18. Jitter vs. Data Rate;
PRBS 31

REV. 0–6–

100

95

VCC = SEL = 3.3V

90

= 1.5V p-p

V

IN

20dB ATTENUATION

85

80

75

70

EYE WIDTH (%)

65

60

% EYE WIDTH = ((CLOCK PERIOD –

55

JITTER p-p)/CLOCK PERIOD)  100%

50

0.5
DATA RATE (Gbps)

1.51.31.10.90.7 1.7 1.9

TPC 19. Eye Width vs. Data
Rate; PRBS 31

38.7mV/DIV

133.7ps/DIV

V

= 3.3V

CC

SEL = 3.3V

= 2V p-p

V

IN

20dB
ATTENUATION

= 25C

T

A

TPC 20. Eye Pattern; 1.244 Gbps,

= 3.3 V, PRBS 31

V

CC

ADG3249

V

= 2.5V

CC

20mV/DIV

166.3ps/DIV

SEL = 2.5V

= 1V p-p

V

IN

TPC 21. Eye Pattern; 1 Gbps,

= 2.5 V, PRBS 31

V

CC

20dB
ATTENUATION

= 25C

T

A

REV. 0

–7–

ADG3249

TIMING MEASUREMENT INFORMATION

For the following load circuit and waveforms, the notation that is used is VIN and V

VVand V V or V V and V V

====

IN A OUT B IN B OUT A

OUT

where

V

CC

DUT

R

V

2.5ns, t

OUT

F

C

L

2.5ns,

V

10MHz.

IN

R

T

PULSE

GENERATOR

NOTES
PULSE GENERATOR FOR ALL PULSES: t

FREQUENCY
CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z

OF THE PULSE GENERATOR.

OUT

R

L

R

L

SW1

2  V

GND

Figure 1. Load Circuit

Test Conditions

Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC)V

R

L

V

⌬

C

L

V

T

500 500 500 Ω
300 150 150 mV
50 30 30 pF

1.5 0.9 0.9 V

= 2.5 V ± 0.2 V (SEL = VCC)VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit

CC

V

CC

CONTROL
INPUT EN

V

OUT

t

PLH

t

PLH

IH

V

T

0V

V

H

V

T

V

L

Figure 2. Propagation Delay

CONTROL INPUT EN

V

SW1 @ 2V

CC

SW1 @ GND

OUT

V

OUT

= 0V

V

IN

VIN = V

Figure 3. Enable and Disable Times

CC

ENABLE

t

t

PZL

PZH

DISABLE

t

PLZ

V

CC

V

T

t

PHZ

V

T

0V

V

INH

V

T

0V

V

CC

VL + V
V

L

V

H

VH –V

0V

Table III. Switch Position

Test S1

, t

t

PLZ





t

PHZ

, t

PZL

PZH

2 × V
GND

CC

REV. 0–8–

ADG3249

BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation

Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3249 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly
to 2.5 V.

Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler­ant inputs, therefore placing the ADG3249 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.

3.3V

3.3V ADC

3.3V

ADG3249

2.5V

2.5V

MICROPROCESSOR

Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor

3.3 V to 2.5 V Translation

When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to V
within a voltage threshold below the V

, the maximum output signal will be clamped to

CC

supply. In this case,

CC

the output will be limited to 2.5 V, as shown in Figure 6. This
device can be used for translation from 2.5 V to 3.3 V devices
and also between two 3.3 V devices.

3.3V

3.3V

ADG3249

2.5V

2.5V

2.5V

2.5 V to 1.8 V Translation

When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to V
to within a voltage threshold below the V

, the maximum output signal will, as before, be clamped

CC

supply. In this case,

CC

the output will be limited to approximately 1.8 V, as shown
in Figure 8.

2.5V

V

OUT

OUTPUT

0V

ADG3249

2.5V SUPPLY

SWITCH

INPU T

SEL = 2.5V

2.5V

1.8V

SEL

= 2.5 V

V

IN

SEL

= V

CC

CC

2.5V

Figure 7. 2.5 V to 1.8 V Voltage Translation,

1.8V

SWITCH

Figure 8. 2.5 V to 1.8 V Voltage Translation,

3.3 V to 1.8 V Translation

The ADG3249 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti­vates internal circuitry in the ADG3242 that allows voltage
translation between 3.3 V devices and 1.8 V devices.

When V

is 3.3 V and the input signal range is 0 V to VCC, the

CC

maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to V

3.3V

CC

.

Figure 5. 3.3 V to 2.5 V Voltage Translation,

V

2.5V

SWITCH

OUT

OUTPUT

0V

SWITCH

INPU T

3.3V SUPPLY

SEL = 3.3V

3.3V

V

IN

Figure 6. 3.3 V to 2.5 V Voltage Translation,

REV. 0

SEL

SEL

= V

= V

CC

CC

3.3V

ADG3249

Figure 9. 3.3 V to 1.8 V Voltage Translation,

V

1.8V

SWITCH

OUT

OUTPUT

0V

SWITCH

INPU T

3.3V SUPPLY

SEL = 0V

3.3V

Figure 10. 3.3 V to 1.8 V Voltage Translation,

–9–

1.8V

SEL

= 0 V

V

IN

SEL

= 0 V

ADG3249

MEMORY

ADDRESS

DATA

MEMORY

BANK B

MEMORY

BANK C

MEMORY

BANK D

MEMORY

BANK A

Analog Switching

Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.

Multiplexing

Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common prob­lems faced by designers of these systems include

•

Large delays caused by capacitive loading of the bus

•

Noise due to simultaneous switching of the address and data
bus signals

Figure 11 shows an array of memory banks in which each ad­dress and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in Figure 12, the output
load on the memory address and data bits is halved. The speed
at which the selected bank’s data can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.

High Impedance during Power-Up/Power-Down

To ensure the high impedance state during power-up or power­down, EN should be tied to V
minimum value of the resistor is determined by the current­sinking capability of the driver.

through a pull-up resistor; the

CC

Figure 11. All Memory Banks Are Permanently
Connected to the Bus

MEMORY

MEMORY

ADDRESS

ADG3249

BANK A

MEMORY

BANK B

MEMORY

BANK C

MEMORY

BANK D

DATA

ADG3249

Figure 12. ADG3249 Used to Reduce Both Access
Time and Noise

REV. 0–10–

OUTLINE DIMENSIONS

8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

2.90 BSC

ADG3249

1.60 BSC

PIN 1

1.30

1.15

0.90

0.15 MAX

7

2

1.95

BSC

5 6

4

2.80 BSC

0.65 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08

8

1 3

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178BA

8
4
0

0.60

0.45

0.30

REV. 0

–11–

C04403–0–10/03(0)

–12–