Page 1
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
ADG3248
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Level Translation
3.3 V to 2.5 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
6-Lead SC70 Package
APPLICATIONS
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Docking Stations
Memory Switching
Analog Switch Applications
GENERAL DESCRIPTION
The ADG3248 is a 2.5 V or 3.3 V, high performance 2:1 multiplexer/demultiplexer. It is designed on a low voltage CMOS
process, which provides low power dissipation yet gives high
switching speed and very low on resistance. This allows the input
to be connected to the output without additional propagation
delay or generating additional ground bounce noise.
Each switch of the ADG3248 conducts equally well in both directions when on. The ADG3248 exhibits break-before-make
switching action, preventing momentary shorting when switching channels.
The ADG3248 is available in a tiny 6-lead SC70 package.
FUNCTIONAL BLOCK DIAGRAM
ADG3248
A0
A1
IN
SWITCHES SHOWN FOR A LOGIC 0 INPUT
PRODUCT HIGHLIGHTS
B
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SC70 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Page 2
ADG3248–SPECIFICATIONS
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T
1
otherwise noted.)
MIN
to T
, unless
MAX
B Version
Parameter Symbol Conditions Min Typ2Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
INH
V
INH
INL
V
INL
I
OZ
ON State Leakage Current 0 ≤ A, B ≤ V
Maximum Pass Voltage V
CAPACITANCE
3
P
VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V
± 0.01 ± 1 µA
0 ≤ A, B ≤ V
VA/VB = V
VA/VB = V
CC
CC
= 3.3 V, IO = –5 µA 2.0 2.5 2.9 V
CC
= 2.5 V, IO= –5 µA 1.5 1.8 2.1 V
CC
± 0.01 ± 1 µA
± 0.01 ±1 µA
A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
3
5
PD
Transition Time t
Break-before-Make Time t
Maximum Data Rate V
Channel Jitter V
OFF f = 1 MHz 4.5 pF
B
, CB ON f = 1 MHz 8.5 pF
A
IN
4
t
, t
PHL
TRANS
BBM
f = 1 MHz 4 pF
CL = 50 pF, VCC = 3 V 0.225 ns
PLH
RL = 510 Ω, CL = 50 pF 16 29 ns
RL = 510 Ω, CL = 50 pF 5 10 ns
= 3.3 V; VA/VB = 2 V 1.244 Gbps
CC
= 3.3 V; VA/VB = 2 V 45 ps p-p
CC
5ps
DIGITAL SWITCH
On Resistance R
On Resistance Matching ⌬R
ON
ON
VCC = 3 V, VA = 0 V, IBA = 8 mA 4.5 8 Ω
= 3 V, VA = 1.7 V, IBA = 8 mA 12 28 Ω
V
CC
V
= 2.3 V, VA = 0 V, IBA = 8 mA 5 9 Ω
CC
= 2.3 V, VA = 1 V, IBA = 8 mA 9 18 Ω
V
CC
VCC = 3 V, VA = 0 V, IA = 8 mA 0.1 0.5 Ω
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
Specifications subject to change without notice.
CC
Digital Inputs = 0 V or V
CC
2.3 3.6 V
0.01 1 µA
REV. 0–2–
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ADG3248
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Table II. Truth Table
IN Function
LB = A0
HB = A1
PIN CONFIGURATION
6-Lead SC70
GND
A0
A1
1
ADG3248
2
TOP VIEW
(Not to Scale)
3
IN
6
V
5
CC
4
B
Table I. Pin Function Descriptions
Pin No. Mnemonic Description
1A0 Port A0, Input or Output
2 GND Ground Reference
3A1 Port A1, Input or Output
4B Port B, Input or Output
5V
CC
Positive Power Supply Voltage
6INChannel Select
ORDERING GUIDE
Temperature Package
Model Range Description Package Branding
ADG3248BKS-R2 –40°C to +85°CSC70 (Thin Shrink Small Outline Transistor Package) KS-6 SMA
ADG3248BKS-REEL –40°C to +85°CSC70 (Thin Shrink Small Outline Transistor Package) KS-6 SMA
ADG3248BKS-REEL7 –40°C to +85°CSC70 (Thin Shrink Small Outline Transistor Package) KS-6 SMA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3248 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
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ADG3248
TERMINOLOGY
V
CC
Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V
INH
V
INL
I
I
I
OZ
I
OL
V
P
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
R
ON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬R
ON
C
OFF OFF Switch Capacitance.
X
C
ON ON Switch Capacitance.
X
C
IN
I
CC
ON Resistance Match between Any Two Channels, i.e., RON max – R
ON
min.
Control Input Capacitance. This consists of IN.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
t
PLH
t
BBM
t
TRANS
, t
PHL
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
× CL, where CL is the load capacitance.
R
ON
On or Off time measured between the 90% points of both switches when switching from one to another.
Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the
OUT signal.
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
REV. 0–4–
Page 5
Typical Performance Characteristics–ADG3248
40
TA = 25ⴗC
35
30
)
25
⍀
(
ON
20
R
15
10
5
0
0 0.5
1.5 2.5 3.5
VA/VB (V
)
TPC 1. On Resistance vs.
Input Voltage
15
= 2.5V
V
CC
10
ⴙ85ⴗC
(⍀)
ON
R
5
ⴙ25ⴗC
VCC = 3V
VCC = 3.3V
VCC = 3.6V
3.02.01.0
ⴚ40ⴗC
40
TA = 25ⴗC
35
30
)
25
⍀
(
ON
20
R
15
10
5
0
0 0.5
1.5 2.5
VA/VB (V
)
TPC 2. On Resistance vs.
Input Voltage
3.0
TA = 25ⴗC
= –5A
I
O
2.5
2.0
(V)
1.5
OUT
V
1.0
0.5
VCC = 2.3V
VCC = 2.5V
VCC = 2.7V
VCC = 3.6V
VCC = 3.3V
VCC = 3V
20
= 3.3V
V
CC
15
(⍀)
10
ON
R
5
0
3.02.01.0
0 0.5
ⴙ85ⴗC
ⴚ40ⴗC
VA/VB (V)
ⴙ25ⴗC
1.5
2.01.0
TPC 3. On Resistance vs. Input
Voltage for Different Temperatures
2.5
TA = 25ⴗC
= –5A
I
O
2.0
1.5
(V)
OUT
V
1.0
0.5
VCC = 2.7V
VCC = 2.5V
VCC = 2.3V
0
0 0.5
VA/VB(V)
1.0
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
3.0
TA = 25ⴗC
V
= 0V
A
2.5
2.0
(V)
V
1.5
OUT
1.0
0.5
0
0.02 0.04 0.06 0.08 0.100
VCC = 2.5V
VCC = 3.3V
IO (A)
TPC 7. Output Low Characteristic
1.2
0
0 0.5
TPC 5. Pass Voltage vs. V
3.0
2.5
2.0
(V)
1.5
OUT
V
1.0
0.5
0
–0.10
1.0 2.0 3.0
1.5 2.5 3.5
VA/VB (V)
TA = 25ⴗC
V
= V
A
CC
VCC = 3.3V
VCC = 2.5V
–0.08 –0.06 –0.04 –0.02 0
IO (A)
CC
TPC 8. Output High Characteristic
0
0 0.5
1.0 2.0 3.0
1.5 2.5
VA/VB (V)
TPC 6. Pass Voltage vs. V
0
TA = 25ⴗC
ON = OFF
–0.2
CL = 1nF
–0.4
–0.6
(pC)
INJ
–0.8
Q
–1.0
–1.2
–1.4
0
VCC = 3.3V
0.5 1.0 1.5 2.52.0 3.0 3.5
VCC = 2.5V
V
A/VB
(V)
TPC 9. Charge Injection vs.
Source Voltage
CC
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–5–
Page 6
ADG3248
(
)
0
(
)
0
1
0
–1
–2
–3
–4
TA = 25ⴗC
–5
V
= 3.3V/2.5V
CC
ATTENUATION (dB)
V
= 0dBm
IN
–6
N/W ANALYZER:
= RS = 50⍀
R
L
–7
–8
0.03 0.1 1.0
FREQUENCY
10 100
100
MHz
TPC 10. Bandwidth vs. Frequency
25
20
15
(ns)
TRANS
10
t
5
0
–40 –20 0
VCC = 2.5V
V
20 80 856040
TEMPERATURE (ⴗC)
CC
= 3.3V
TPC 13. Transition Time vs.
Temperature
0
TA = 25ⴗC
–10
V
= 3.3V/2.5V
CC
V
= 0dBm
IN
–20
N/W ANALYZER:
–30
R
= RS = 50⍀
L
–40
–50
–60
–70
ATTENUATION (dB)
–80
–90
–100
0.03 0.1 1.0
FREQUENCY
10 100
100
MHz
TPC 11. Crosstalk vs. Frequency
100
VCC = 3.3V
90
= 1.5V p-p
V
A
20dB ATTENUATION
80
70
60
50
40
JITTER (ps p-p)
30
20
10
0
0.7 0.9 1.1 1.3 1.5 1.7 1.9
0.5
DATA RATE (Gbps)
TPC 14. Jitter vs. Data Rate;
PRBS 31
0
TA = 25ⴗC
–10
V
= 3.3V/2.5V
CC
V
= 0dBm
IN
–20
N/W ANALYZER:
–30
R
= RS = 50⍀
L
–40
–50
–60
–70
ATTENUATION (dB)
–80
–90
–100
0.03 0.1 1.0
10 1000100
FREQUENCY (MHz)
TPC 12. Off Isolation vs.
Frequency
100
95
VCC = 3.3V
90
= 1.5V p-p
V
A
20dB ATTENUATION
85
80
75
70
EYE WIDTH (%)
65
60
% EYE WIDTH = ((CLOCK PERIOD –
55
JITTER p-p)/CLOCK PERIOD) ⴛ 100%
50
0.5
DATA RATE (Gbps)
1.51.31.10.90.7 1.7 1.9
TPC 15. Eye Width vs. Data Rate;
PRBS 31
38.7mV/DIV
133.7ps/DIV
V
CC
V
IN
= 3.3V
= 2V p-p
20dB
ATTENUATION
= 25ⴗC
T
A
TPC 16. Eye Pattern; 1.244 Gbps,
= 3.3 V, PRBS 31
V
CC
20mV/DIV
166.3ps/DIV
V
CC
V
IN
= 2.5V
= 1V p-p
20dB
ATTENUATION
= 25ⴗC
T
A
TPC 17. Eye Pattern; 1 Gbps,
VCC = 2.5 V, PRBS 31
REV. 0–6–
Page 7
BUS SWITCH APPLICATIONS
V
IN
2.5V
V
OUT
0V
3.3V
SWITCH
INPU T
SWITCH
OUTPUT
3.3V SUPPLY
V
IN
1.8V
V
OUT
0V
2.5V
SWITCH
INPU T
SWITCH
OUTPUT
2.5V SUPPLY
Mixed Voltage Operation, Level Translation
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3248 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly
to 2.5 V.
Figure 1 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3248 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
ADG3248
Figure 3. 3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V and the input signal range is 0 V to VCC, the
maximum output signal will, as before, be clamped to within a
voltage threshold below the V
will be limited to approximately 1.8 V, as shown in Figure 5.
supply. In this case, the output
CC
3.3V
3.3V ADC
3.3V
2.5V
2.5V
MICROPROCESSOR
ADG3248
Figure 1. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to within a voltage
threshold below the V
supply.
CC
In this case, the output will be limited to 2.5 V, as shown in
Figure 3. This device can be used for translation from 2.5 V to
3.3 V devices and also between two 3.3 V devices.
3.3V
3.3V
2.5V
ADG3248
2.5V
2.5V
Figure 2. 3.3 V to 2.5 V Voltage Translation
2.5V
2.5V
ADG3248
1.8V
Figure 4. 2.5 V to 1.8 V Voltage Translation
Figure 5. 2.5 V to 1.8 V Voltage Translation
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
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ADG3248
MEMORY
ADDRESS
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
MEMORY
BANK A
Multiplexing
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common problems faced by designers of these systems include
•
Large delays caused by capacitive loading of the bus
•
Noise due to simultaneous switching of the address and data
bus signals
Figure 6 shows an array of memory banks in which each address
and data signal is loaded by the sum of the individual loads. If
a bus switch is used as shown in Figure 7, the output load on
the memory address and data bits is halved. The speed at which
the selected bank’s data can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
Figure 6. All Memory Banks Are Permanently
Connected to the Bus
MEMORY
MEMORY
ADDRESS
ADG3248
BANK A
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
DATA
ADG3248
Figure 7. ADG3248 Used to Reduce Both Access
Time and Noise
REV. 0–8–
Page 9
OUTLINE DIMENSIONS
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
2.00 BSC
4
5
1.25 BSC
1.00
0.90
0.70
0.10 MAX
6
1
2
PIN 1
1.30 BSC
0.30
0.15
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
3
0.65 BSC
2.10 BSC
1.10 MAX
SEATING
PLANE
0.22
0.08
0.46
8ⴗ
4ⴗ
0ⴗ
0.36
0.26
ADG3248
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C04404–0–10/03(0)
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