Datasheet ADG3247 Datasheet (Analog Devices)

2.5 V/3.3 V, 16-Bit, 2-Port

Level Translating, Bus Switch

ADG3247

FEATURES
225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports
Data Rate 1.244 Gbps

2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V

40-Lead 6 mm  6 mm LFCSP and 38-Lead TSSOP

Packages

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Plug
Hot Swap
Analog Switching Applications

GENERAL DESCRIPTION

The ADG3247 is a 2.5 V or 3.3 V 16-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.

The ADG3247 is organized as dual 8-bit bus switches with
separate bus enable (BEx) inputs. This allows the device to be
used as two 8-bit digital switches or one 16-bit bus switch. These
bus switches allow bidirectional signals to be switched when ON.
In the OFF condition, signal levels up to the supplies are blocked.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is operated
from a 2.5 V supply and 2.5 V inputs are applied, the device will
translate the outputs to 1.8 V. In addition to this, the ADG3247
has a level translating select pin (SEL). When SEL is low, V

CC

is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to appli­cations requiring level translation between different supplies, such
as converter to DSP/microcontroller interfacing.

FUNCTIONAL BLOCK DIAGRAM

A0

A7

BE1

A8

A15

BE2

PRODUCT HIGHLIGHTS

B0

B7

B8

B15

1. 3.3 V or 2.5 V supply operation

2. Extremely low propagation delay through switch

3. 4.5 W switches connect inputs to outputs

4. Level/voltage translation

5. 40-lead 6 mm ⫻ 6 mm LFCSP and 38-lead TSSOP packages

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADG3247–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

noted.)

MIN

to T

, unless otherwise

MAX

Parameter Symbol Conditions Min Typ

B Version

2

Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage V

INH

V

INH

INL

V

INL

I

OZ

OL

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 mA

0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V

CC

CC

± 0.01 ± 1 mA
± 0.01 ± 1 mA

VA/VB = VCC = SEL = 3.3 V, IO = –5 mA 2.0 2.5 2.9 V

= VCC = SEL = 2.5 V, IO = –5 mA 1.5 1.8 2.1 V

V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 mA 1.5 1.8 2.1 V

CAPACITANCE

3

A Port Off Capacitance CA OFF f = 1 MHz 5 pF
B Port Off Capacitance C
A, B Port On Capacitance
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B

3

5

PD

6

6

6

6

6

6

OFF f = 1 MHz 5 pF

B

CA, CB ON

IN

4

t

PHL, tPLHCL

t

PZH

t

PHZ

t

PZH

t

PHZ

t

PZH

t

PHZ

f = 1 MHz 10 pF
f = 1 MHz 6 pF

, t

PZLVCC

, t

PLZVCC

, t

PZLVCC

, t

PLZVCC

, t

PZLVCC

, t

PLZVCC

= 50 pF, VCC =

= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 2.3 V to 2.7 V;
= 2.3 V to 2.7 V;

SEL =

3 V 0.225 ns

SEL = V
SEL = V
SEL = 0 V
SEL = 0 V

SEL = V

SEL = V

CC

CC

CC

CC

1 3.2 4.8 ns
1 3.2 4.8 ns

0.5 2.2 3.3 ns

0.5 1.7 2.9 ns

0.5 2.2 3 ns

0.5 1.75 2.6 ns

22.5 ps

Maximum Data Rate VCC = SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps
Channel Jitter VCC = SEL = 3.3 V; VA/VB = 2 V 50 ps p-p

Operating Frequency—Bus Enable f

BEx

10 MHz

DIGITAL SWITCH

On Resistance R

On Resistance Matching DR

ON

ON

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA

4.5 8
15 28
59
11 18
58
14

0.45

0.65

W
W
W
W
W
W
W
W

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40∞C to +85∞C.

2

Typical values are at 25∞C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the control pins (BEx) only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

7

I
D I

CC

CC

CC

Digital Inputs = 0 V or VCC; SEL = V

CC

Digital Inputs = 0 V or VCC; SEL = 0 V 0.65 1.2 mA
V

= 3.6 V, BE1 = 3.0 V;

CC

BE2 = VCC or GND;

SEL = V

CC

2.3 3.6 V

0.001 1 mA

85 mA

REV. 0–2–

ADG3247

1

2

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

LFCSP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 32°C/W

θ

JA

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 98°C/W

θ

JA

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3247BCP –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-40
ADG3247BCP-REEL7 –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-40
ADG3247BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-38
ADG3247BRU-REEL7 –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-38

Table I. Pin Description

Mnemonic Description

BEx Bus Enable (Active Low)
SEL Level Translation Select

Ax Port A, Inputs or Outputs
Bx Port B, Inputs or Outputs

BEx SEL* Function

LL A = B, 3.3 V to 1.8 V Level Shifting
LH A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
HX Disconnect

*SEL = 0 only when VDD = 3.3 V ± 10%

Table II. Truth Table

PIN CONFIGURATION

40-Lead LFCSP and 38-Lead TSSOP

1

SEL

2

CC

40 A5

39 A4

38 A3

37 A2

A6

1

A7

2

A8

3

A9

4

A10

5

A11

6

A12

7

A13

8

A14

9

A15

10

PIN 1
INDICATOR

ADG3247

TOP VIEW

NC 12

NC 13

NC 14

GND 11

NC = NO CONNECT

36 A1

35 A0

B15 15

B14 16

33 V

34 SEL

B12 18

B13 17

32 BE2

31 BE1

B10 20

B11 19

30 B0
29 B1
28 B2
27 B3
26 B4
25 B5
24 B6
23 B7
22 B8
21 B9

A0

3

A1

ADG3247

4

A2

TOP VIEW

5

A3

(Not to Scale)

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

12

A10

13

A11

14

A12

A13

15

A14

16

17

A15

18

GND

19

NC

NC = NO CONNECT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3247 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

38

V

CC

37

BE

36

BE

35

B0

34

B1

33

B2

32

B3

B4

31

30

B5

29

B6

28

B7

27

B8

26

B9

25

B10

24

B11

23

B12

22

B13

21

B14

20

B15

REV. 0

–3–

ADG3247

TERMINOLOGY

V

CC

GND Ground (0 V) Reference.

V

INH

V

INL

I

I

I

OZ

I

OL

V

P

R

ON

⌬R

ON

C

OFF OFF Switch Capacitance.

X

C

ON ON Switch Capacitance.

X

C

IN

I

CC

⌬I

CC

t

, t

PLH

PHL

t

, t

PZH

PZL

t

, t

PHZ

PLZ

Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.

Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

f

BEx

Positive Power Supply Voltage.

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.

On Resistance Match between Any Two Channels, i.e., R

Max – R

ON

ON

Min.

Control Input Capacitance. This consists of BEx and SEL.

Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.

Extra power supply current component per each BEx control input when the Input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

⫻ CL, where CL is the load capacitance.

R

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.

Bus Disable Times. These are the times taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V

from the original quiescent

⌬

level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)

Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BEx) can be toggled.

REV. 0–4–

Typical Performance Characteristics–ADG3247



–

R

ON

40

35

30

25

20

15

10

SEL = V

5

0

0 0.5

TA = 25C

CC

1.5 2.5 3.5
VA/VB – V

VCC = 3V

VCC = 3.3V

= 3.6V

V

CC

3.02.01.0

TPC 1. On Resistance vs.
Input Voltage

20

= 3.3V

V

CC

SEL = V

CC

15



–

10

ON

R

5

0

0 0.5

85C

40C

VA/VB – V

25C

1.5

2.01.0

TPC 4. On Resistance vs. Input
Voltage for Different Temperatures

40

35

30

25



–

ON

20

R

15

10

TA = 25C

SEL = V

5

0

0 0.5

CC

VCC = 2.3V

VCC = 2.5V

VCC = 2.7V

1.5 2.5

VA/VB – V

TPC 2. On Resistance vs.
Input Voltage

15

= 2.5V

V

CC

SEL = V

CC

10



85C

–

ON

R

5

25C

0

00.5
VA/VB – V

40C

1.0

TPC 5. On Resistance vs. Input
Voltage for Different Temperatures

40

TA = 25C

35

SEL = 0V

30

25



–

ON

20

R

15

10

5

0

3.02.01.0

0 0.5

1.0 2.0 3.0

VCC = 3V

VCC = 3.3V

V

= 3.6V

CC

1.5 2.5
VA/VB – V

3.5

TPC 3. On Resistance vs.
Input Voltage

1.2

3.0
TA = 25C

SEL = V

= –5A

I

O

0 0.5

CC

1.0 2.0 3.0

– V

V

2.5

2.0

1.5

OUT

1.0

0.5

0

TPC 6. Pass Voltage vs. V

VCC = 3.6V

VCC = 3.3V

VCC = 3V

1.5 2.5 3.5
VCC – V

CC

2.5

TA = 25C
SEL = V
I

O

CC

= –5A

1.0 2.0 3.0
VCC – V

– V

V

2.0

1.5

OUT

1.0

0.5

0

0 0.5

TPC 7. Pass Voltage vs. V

REV. 0

VCC = 2.7V

VCC = 2.5V

VCC = 2.3V

1.5 2.5

CC

2.5

TA = 25C
SEL = 0V

2.0

= –5A

I

O

1.5

– V

OUT

V

1.0

0.5

0

0 0.5

1.0 2.0 3.0

VCC = 3V

1.5 2.5
VCC – V

TPC 8. Pass Voltage vs. V

–5–

VCC = 3.6V

VCC = 3.3V

CC

3.5

1800

TA = 25C

1600

1400

1200

A
–

CC

I

1000

800

600

400

200

0

02

VCC = SEL = 3.3V

VCC = 3.3V, SEL = 0V

= SEL = 2.5V

V

CC

4

6810

ENABLE FREQUENCY – MHz

12

14 16 18 20

TPC 9. ICC vs. Enable Frequency

ADG3247

3.0
TA = 25C
V

= 0V

A

2.5
BE = 0

– V

V

2.0

1.5

OUT

1.0

0.5

0

0.02 0.04 0.06 0.08 0.100

VCC = 3.3V; SEL = 0V

VCC = SEL = 3.3V

VCC = SEL = 2.5V

IO – A

TPC 10. Output Low Characteristic

0

TA = 25C

–2

= 3.3V/2.5V

V

CC

SEL = V

–4

–6

–8

ATTENUATION – dB

–10

–12

–14

CC

V

= 0dBm

IN

N/W ANALYZER

= RS = 50

R

L

0.03 0.1 1000

:

110100

FREQUENCY – MHz

TPC 13. Bandwidth vs. Frequency

3.0
TA = 25C
V

= V

A

CC

BE = 0

VCC = SEL = 3.3V

VCC = SEL = 2.5V

VCC = 3.3V; SEL = 0V

–0.08 –0.06 –0.04 –0.02 0

IO – A

– V

V

OUT

2.5

2.0

1.5

1.0

0.5

0

–0.10

TPC 11. Output High Characteristic

–20

TA = 25C

= 3.3V/2.5V

V

–30

CC

SEL = V

CC

ADJACENT CHANNELS

–40

= 0dBm

V

IN

N/W ANALYZER

–50

= RS = 50

R

L

–60

–70

ATTENUATION – dB

–80

–90

–100

0.03 0.1 1000110100

:

FREQUENCY – MHz

TPC 14. Crosstalk vs. Frequency

0

TA = 25C

–0.2

SEL = V

CC

ON OFF

–0.4

C

= InF

L

–0.6

–0.8

– pC

–1.0

INJ

Q

–1.2

–1.4

–1.6

–1.8

–2.0

V

0 0.5

= 2.5V

CC

VCC = 3.3V

1.0 2.0 3.0

1.5 2.5

VA/VB – V

TPC 12. Charge Injection vs.
Source Voltage

–20

TA = 25C

–30

–40

–50

–60

–70

ATTENUATION – dB

–80

–90

–100

= 3.3V/2.5V

V

CC

SEL = V

CC

VIN = 0dBm

N/W ANALYZER

= RS = 50

R

L

0.03 0.1 1000110100

:

FREQUENCY – MHz

TPC 15. Off Isolation vs.
Frequency

3.5

ENABLE

3.0

DISABLE

2.5
ENABLE

2.0
DISABLE

1.5

TIME – ns

1.0

0.5

0
–40

–20 0 20 40 60 80 100

VCC = SEL = 3.3V

VCC = 3.3V, SEL = 0V

TEMPERATURE – C

TPC 16. Enable/Disable Time
vs. Temperature

2.5

ENABLE

2.0

DISABLE

1.5

TIME – ns

1.0

0.5

0
–40

VCC = SEL = 2.5V

–20 0 20 40 60 80 100

TEMPERATURE – C

TPC 17. Enable/Disable Time
vs. Temperature

100

VCC = SEL = 3.3V

90

= 2V p-p

V

IN

20dB ATTENUATION

80

70

60

50

40

JITTER – ps

30

20

10

0

0.5 0.6

0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.51.0
DATA RATE – Gbps

TPC 18. Jitter vs. Data Rate;
PRBS 31

REV. 0–6–

100

95

VCC = SEL = 3.3V

90

85

80

75

70

EYE WIDTH – %

65

60

55

50

= 2V p-p

V

IN

20dB ATTENUATION

% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD)  100%

0.5 0.6

0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5
DATA RATE – Gbps

1.0

35mV/DIV
100ps/DIV

VCC = 3.3V

SEL = 3.3V

= 2V p-p

V

IN

20dB
ATTENUATION
T

= 25C

A

37mV/DIV
200ps/DIV

= 2.5V

V

CC

SEL = 2.5V
V

= 2V p-p

IN

ADG3247

20dB
ATTENUATION
TA = 25C

TPC 19. Eye Width vs. Data
Rate; PRBS 31

20dB

50.1mV/DIV
50ps/DIV

= 25C

T

A

ATTENUATION

= 3.3V

V

CC

SEL = 3.3V

= 2V p-p

V

IN

TPC 22. Jitter @ 1.244 Gbps,
PRBS 31

TPC 20. Eye Pattern; 1.244
Gbps, V

= 3.3 V, PRBS 31

CC

TPC 21. Eye Pattern; 1 Gbps,
V

= 2.5 V, PRBS 31

CC

REV. 0

–7–

ADG3247

TIMING MEASUREMENT INFORMATION

For the following load circuit and waveforms, the notation that is used is VIN and V

VVand V V or V V and V V

====

IN A OUT B IN B OUT A

OUT

where

V

CC

t

ⱕ 2.5ns,

R

V

OUT

V

PULSE

GENERATOR

NOTE S
PULSE GENERATOR FOR ALL PULSES:
FREQUENCY ⱕ 10MHz.
C

INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.

L

R

IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z

T

OF THE PULSE GENERATOR.

IN

D.U.T.

R

T

Figure 1. Load Circuit

Symbol V

R

L

V

D

C

L

V

T

= 3.3 V

CC

± 0.3 V (SEL =

500 500 500 W
300 150 150 mV
50 30 30 pF

1.5 0.9 0.9 V

C

L

t

ⱕ 2.5ns,

F

V

CC

SW1

R

L

R

L

OUT

)

VCC = 2.5 V

2  V

CC

GND

Test Conditions

± 0.2 V (SEL =

SWITCH INPUT

t

PLH

OUTPUT

Figure 2. Propagation Delay

V

)

CC

VCC = 3.3

V ± 0.3 V (SEL = 0 V)

V

IH

V

T

t

PHL

0V

V

H

V

T

V

L

Unit

CONTROL INPUT BEx

V

SW1 @ 2V

CC

SW1 @ GND

OUT

V

OUT

= 0V

V

IN

VIN = V

Figure 3. Enable and Disable Times

CC

ENABLE

t

t

PZL

PZH

DISABLE

t

PLZ

V

CC

V

T

t

PHZ

V

T

0V

V

INH

V

T

0V

V

CC

VL + V
V

L

V

H

VH –V

0V

Table III. Switch Position

TEST S1

t

, t

PLZ





t

PHZ

, t

PZL

PZH

2 ⫻ V
GND

CC

REV. 0–8–

ADG3247

V

IN

1.8V

V

OUT

0V

2.5V

SWITCH

INPU T

SWITCH

OUTPUT

2.5V SUPPLY

SEL = 2.5V

BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation

Bus switches can be used to provide an ideal solution for inter­facing between mixed voltage systems. The ADG3247 is suitable
for applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from

3.3 V directly to 2.5 V.

Figure 4 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V micro­processor. The microprocessor may not have 3.3 V tolerant inputs;
therefore placing the ADG3247 between the two devices allows the
devices to communicate easily. The bus switch directly connects
the two blocks, thus introducing minimal propagation delay,
timing skew, or noise.

3.3V

3.3V ADC

ADG3247

2.5V3.3V

2.5V

MICROPROCESSOR

Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor

3.3 V to 2.5 V Translation

When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V

, the maximum output signal will be clamped to within

to V

CC

a voltage threshold below the V

3.3V

2.5V

Figure 5. 3.3 V to 2.5 V Voltage Translation,

supply.

CC

3.3V

ADG3247

2.5V

2.5V

SEL

= V

CC

In this case, the output will be limited to 2.5 V, as shown in
Figure 6.

V

OUT

2.5V

SWITCH

OUTPUT

0V

Figure 6. 3.3 V to 2.5 V Voltage Translation,

SWITCH

INPU T

3.3V SUPPLY

SEL = 3.3V

3.3V

V

IN

SEL

= V

CC

This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.

2.5 V to 1.8 V Translation

When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V

, the maximum output signal will, as before, be clamped

to V

CC

to within a voltage threshold below the V

2.5V

2.5V

ADG3247

Figure 7. 2.5 V to 1.8 V Voltage Translation,

supply.

CC

1.8V

SEL

= V

CC

In this case, the output will be limited to approximately 1.8 V,
as shown in Figure 7.

Figure 8. 2.5 V to 1.8 V Voltage Translation,

SEL

= V

CC

3.3 V to 1.8 V Translation

The ADG3247 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the

SEL pin.
SEL pin: An active low control pin. SEL activates internal

circuitry in the ADG3247 that allows voltage translation between

3.3 V devices and 1.8 V devices.

3.3V

3.3V

Figure 9. 3.3 V to 1.8 V Voltage Translation,

ADG3247

1.8V

SEL

= 0 V

When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to V

CC

.

REV. 0

–9–

ADG3247

1.8V

V

OUT

3.3V SUPPLY

SEL = 0V

CPU

ADG3247ADG3247

PLUG-IN
CARD (1)

CARD I/O

SWITCH

OUTPUT

V

SWITCH

0V

INPU T

Figure 10. 3.3 V to 1.8 V Voltage Translation,

3.3V

IN

SEL

= 0 V

Bus Isolation

A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3247 is designed specifically for
applications that do not need drive yet require simple logic func­tions, it solves this requirement. The device isolates access to the
bus, thus minimizing capacitance loading.

BUS SWITCH

LOCATION

LOAD A

LOAD B

LOAD C

LOAD D

BUS/

BACKPLANE

Figure 11. Location of Bus Switched in a Bus
Isolation Application

Hot Plug and Hot Swap Isolation

The ADG3247 is suitable for hot swap and hot plug applications.
The output signal of the ADG3247 is limited to a voltage that is
below the V

supply, as shown in Figures 6, 8, and 10. There-

CC

fore the switch acts like a buffer to take the impact from hot
insertion, protecting vital and expensive chipsets from damage.

In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.

RAM

PLUG-IN
CARD (2)

CARD I/O

Figure 12. ADG3247 in a Hot Plug Application

There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.

Analog Switching

Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical plot),
but in many cases, this does not present an issue.

High Impedance during Power-Up/Power-Down

To ensure the high impedance state during power-up or power­down, BEx should be tied to V

through a pull-up resistor;

CC

the minimum value of the resistor is determined by the current­sinking capability of the driver.

PACKAGE AND PINOUT

The ADG3247 is packaged in both a small 38-lead TSSOP or
a tiny 40-lead LFCSP package. The area of the TSSOP option
is 62.7 mm

2

, while the area of the LFCSP option is 36 mm2.
This leads to a 43% savings in board space when using the LFCSP
package compared with the TSSOP package. This makes the
LFCSP option an excellent choice for space-constrained
applications.

The ADG3247 in the TSSOP package offers a flowthrough
pinout. The term flowthrough signifies that all the inputs are on
opposite sides from the outputs. A flowthrough pinout simplifies
the PCB layout.

REV. 0–10–

OUTLINE DIMENSIONS

40-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-40)

Dimensions shown in millimeters

ADG3247

PIN 1

INDICATOR

1.00

0.90

0.80

12 MAX

SEATING
PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 NOM

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

0.60 MAX

31

30

21

20

BOTTOM

VIEW

4.50
REF

38-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-38)

Dimensions shown in millimeters

9.80

9.70

9.60

PIN 1

40

11

INDICATOR

1

4.25

3.70 SQ

1.75

10

38

PIN 1

0.15

0.05

COPLANARITY

0.10

20

4.50

4.40

4.30

1.20
MAX

0.20

0.09

6.40 BSC

8
0

191

0.50
BSC

COMPLIANT TO JEDEC STANDARDS MS-153BD-1

0.27

0.17

SEATING
PLANE

0.70

0.60

0.45

REV. 0

–11–

C03013–0–5/03(0)

–12–