Datasheet ADG3246 Datasheet (Analog Devices)

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Page 1

2.5 V/3.3 V, 10-Bit, 2-Port

Level Translating, Bus Switch

ADG3246

FEATURES 225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports Data Rate 1.244 Gbps

2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Small Signal Bandwidth 610 MHz Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V

24-Lead TSSOP and LFCSP Packages

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation Bus Switching Bus Isolation Hot Swap Hot Plug Analog Signal Switching

GENERAL DESCRIPTION

The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch. It is designed on Analog Devices’ low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance, allowing inputs to be connected to outputs without additional propagation delay or generating additional ground bounce noise.

The switches are enabled by means of the bus enable (BE) input signal. These digital switches allow bidirectional signals to be switched when ON. In the OFF condition, signal levels up to the supplies are blocked.

This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs occurs. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, the ADG3246 has a level translating select pin (SEL). When SEL is low, V

is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing.

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. 3.3 V or 2.5 V supply operation

2. Extremely low propagation delay through switch

3. 4.5 W switches connect inputs to outputs

4. Level/voltage translation

5. 24-lead 4 mm ¥ 4 mm LFCSP and 24-lead TSSOP packages

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

Page 2

ADG3246–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

otherwise noted.)

MIN

to T

MAX

, unless

B Version

Parameter Symbol Conditions Min Typ2Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I OFF State Leakage Current I

INH

INL

ON State Leakage Current 0 £ A, B £ V Maximum Pass Voltage V

VCC = 2.7 V to 3.6 V 2.0 V VCC = 2.3 V to 2.7 V 1.7 V VCC = 2.7 V to 3.6 V 0.8 V VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 mA

0 £ A, B £ V

± 0.01 ± 1 mA ± 0.01 ± 1 mA

VA/VB = VCC = SEL = 3.3 V, IO = –5 mA 2.0 2.5 2.9 V

= VCC = SEL = 2.5 V, IO = –5 mA 1.5 1.8 2.1 V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 mA 1.5 1.8 2.1 V

CAPACITANCE

A Port Off Capacitance CA OFF f = 1 MHz 5 pF B Port Off Capacitance C

OFF f = 1 MHz 5 pF

A, B Port On Capacitance CA, CB ON f = 1 MHz 10 pF Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t Propagation Delay Matching Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Enable Time BE to A or B Bus Disable Time BE to A or B

, t

PHL

PLH

, t

PZH

PZL

, t

PHZ

PLZ

, t

PZH

PZL

, t

PHZ

PLZ

, t

PZH

PZL

, t

PHZ

PLZ

f = 1 MHz 6 pF

CL = 50 pF, VCC = SEL = 3 V 0.225 ns

22.5 ps VCC = 3.0 V to 3.6 V; SEL = V VCC = 3.0 V to 3.6 V; SEL = V

1 3.2 4.8 ns

1 3.2 4.8 ns VCC = 3.0 V to 3.6 V; SEL = 0 V 0.5 2.2 3.3 ns VCC = 3.0 V tp 3.6 V; SEL = 0 V 0.5 1.7 2.9 ns VCC = 2.3 V to 2.7 V; SEL = V VCC = 2.3 V to 2.7 V; SEL = V

0.5 2.2 3 ns

0.5 1.75 2.6 ns Maximum Data Rate VCC = SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps Channel Jitter VCC = SEL = 3.3 V; VA/VB = 2 V 50 ps p-p Operating Frequency—Bus Enable f

10 MHz

DIGITAL SWITCH

On Resistance R

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 W VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 15 28 W VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 W VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 11 18 W VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA 5 8 W VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 14 W

On Resistance Matching ⌬R

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 0.45 W VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 0.65 W

POWER REQUIREMENTS

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

Temperature range is as follows: B Version: –40∞C to +85∞C.

Typical values are at 25∞C, unless otherwise stated.

Guaranteed by design, not subject to production test.

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage

I ⌬I

Digital Inputs = 0 V or VCC; SEL = V

Digital Inputs = 0 V or VCC; SEL = 0 V 0.65 1.2 mA VCC = 3.6 V, BE = 3.0 V; SEL = V

2.3 3.6 V

0.001 1 mA

130 mA

source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

See Timing Measurement Information section.

This current applies to the control pin (BE) only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

REV. 0–2–

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ADG3246

GND

SEL

TOP VIEW

(Not to Scale)

ADG3246

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

LFCSP Package ␪

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 35°C/W

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 128°C/W

␪

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3246BCP –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-24 ADG3246BCP-REEL7 –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-24 ADG3246BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-24 ADG3246BRU-REEL7 –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-24

Table I. Pin Description

Mnemonic Description

BE Bus Enable (Active Low) SEL Level Translation Select

Ax Port A, Inputs or Outputs Bx Port B, Inputs or Outputs

BE SEL* Function

LL A = B, 3.3 V to 1.8 V Level Shifting LH A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting HX Disconnect

*SEL = 0 only when VDD = 3.3 V ± 10%

Table II. Truth Table

PIN CONFIGURATION

24-Lead LFCSP and TSSOP

24 A4

23 A3

22 A2

21 A1

20 A0

19 V

B6 11

18 BE 17 B0

16 B1 15 B2 14 B3 13 B4

B5 12

–3–

SEL 1

A5 2 A6 3 A7 4 A8 5 A9 6

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3246 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

PIN 1 INDICATOR

ADG3246

TOP VIEW

B9 8

B8 9

GND 7

B7 10

Page 4

ADG3246

TERMINOLOGY

Positive Power Supply Voltage.

GND Ground (0 V) Reference.

INH

INL

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clipped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage.

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch.

⌬R

OFF OFF Switch Capacitance.

ON ON Switch Capacitance.

On Resistance Match between Any Two Channels, i.e., RON Max – RON Min.

Control Input Capacitance. This consists of BE and SEL.

Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF.

⌬I

PLH

PZH

, t

PHL

PZL

Extra power supply current component for the BE control input when the input is not criven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

¥ CL, where CL is the load capacitance.

Bus Enable Times. These are times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, BE.

PHZ

, t

PLZ

Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control signal. It is measured as the time taken for the output voltage to change by V

from the original quiescent level,

⌬

with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)

Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.

Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.

REV. 0–4–

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Typical Performance Characteristics–ADG3246



–

TA = 25C

SEL = V

0 0.5

1.5 2.5 3.5 VA/VB – V

= 3V

VCC = 3.3V

VCC = 3.6V

3.02.01.0

TPC 1. On Resistance vs. Input Voltage

= 3.3V

SEL = V



–

0 0.5

85C

40C

VA/VB – V

25C

1.5

2.01.0

TPC 4. On Resistance vs. Input Voltage for Different Temperatures



–

TA = 25C

SEL = V

0 0.5

VCC = 2.3V

VCC = 2.7V

1.5 2.5

VA/VB – V

= 2.5V

3.02.01.0

TPC 2. On Resistance vs. Input Voltage

= 2.5V

SEL = V



85C

–

0 0.5

25C

VA/VB – V

40C

1.0

TPC 5. On Resistance vs. Input Voltage for Different Temperatures

1.2



–

TA = 25C SEL = 0V

0 0.5

1.0 2.0 3.0

VCC = 3V

VCC = 3.3V

VCC = 3.6V

1.5 2.5 VA/VB – V

TPC 3. On Resistance vs. Input Voltage

– V

3.0

2.5

2.0

1.5

OUT

1.0

0.5

TA = 25C SEL = V I

0 0.5

= –5A

1.0 2.0 3.0

VCC = 3.6V

VCC = 3V

1.5 2.5 3.5 VCC – V

TPC 6. Pass Voltage vs. V

3.5

VCC = 3.3V

2.5

TA = 25C SEL = V I

= –5A

1.0 2.0 3.0 VCC – V

– V

2.0

1.5

OUT

1.0

0.5

0 0.5

TPC 7. Pass Voltage vs. V

REV. 0

VCC = 2.7V

VCC = 2.5V

VCC = 2.3V

1.5 2.5

2.5

TA = 25C SEL = 0V

2.0

= –5A

1.5

– V

OUT

1.0

0.5

0 0.5

1.0 2.0 3.0

VCC = 3V

1.5 2.5 VCC – V

TPC 8. Pass Voltage vs. V

–5–

VCC = 3.6V

VCC = 3.3V

3.5

1800

TA = 25C

1600

1400

1200

A –

1000

800

600

400

200

VCC = SEL = 3.3V

VCC = 3.3V, SEL = 0V

VCC = SEL = 2.5V

6810

ENABLE FREQUENCY – MHz

14 16 18 20

TPC 9. ICC vs. Enable Frequency

Page 6

ADG3246

3.0 TA = 25C V

= 0V

2.5 BE = 0

– V

2.0

1.5

OUT

1.0

0.5

0.02 0.04 0.06 0.08 0.100

VCC = 3.3V; SEL = 0V

VCC = SEL = 3.3V

VCC = SEL = 2.5V

IO – A

TPC 10. Output Low Characteristic

TA = 25C

–2

= 3.3V/2.5V

SEL = V

–4

–6

–8

ATTENUATION – dB

–10

–12

–14

0.03 0.1 1000

VIN = 0dBm N/W ANALYZER

= RS = 50

FREQUENCY – MHz

110100

TPC 13. Bandwidth vs. Frequency

3.0 TA = 25C V

= V

BE = 0

VCC = SEL = 3.3V

VCC = SEL = 2.5V

VCC = 3.3V; SEL = 0V

–0.08 –0.06 –0.04 –0.02 0

IO – A

– V

OUT

2.5

2.0

1.5

1.0

0.5

–0.10

TPC 11. Output High Characteristic

–20

TA = 25C

= 3.3V/2.5V

–30

SEL = V

ADJACENT CHANNELS

–40

= 0dBm

N/W ANALYZER

–50

= RS = 50

–60

–70

ATTENUATION – dB

–80

–90

–100

0.03 0.1 1000110100

FREQUENCY – MHz

TPC 14. Crosstalk vs. Frequency

TA = 25C

–0.2

SEL = V

ON OFF

–0.4

= InF

–0.6

– pC

INJ

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

VCC = 2.5V

0 0.5

VCC = 3.3V

1.5 2.5

1.0 2.0 3.0 VA/VB – V

TPC 12. Charge Injection vs. Source Voltage

–20

TA = 25C

–30

–40

–50

–60

–70

ATTENUATION – dB

–80

–90

–100

= 3.3V/2.5V

SEL = V

VIN = 0dBm N/W ANALYZER

= RS = 50

0.03 0.1 1000110100

FREQUENCY – MHz

TPC 15. Off Isolation vs. Frequency

3.5

ENABLE

3.0

DISABLE

2.5 ENABLE

2.0 DISABLE

1.5

TIME – ns

1.0

0.5

–20 0 20 40 60 80 100

–40

VCC = SEL = 3.3V

VCC = 3.3V, SEL = 0V

TEMPERATURE – C

TPC 16. Enable/Disable Time vs. Temperature

2.5

ENABLE

2.0

DISABLE

1.5

TIME – ns

1.0

0.5

0 –40

VCC = SEL = 2.5V

–20 0 20 40 60 80 100

TEMPERATURE – C

TPC 17. Enable/Disable Time vs. Temperature

100

VCC = SEL = 3.3V

VIN = 2V p-p 20dB ATTENUATION

JITTER – ps

0.5 0.6

0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.51.0 DATA RATE – Gbps

TPC 18. Jitter vs. Data Rate; PRBS 31

REV. 0–6–

Page 7

100

= SEL = 3.3V

= 2V p-p

20dB ATTENUATION

EYE WIDTH – %

% EYE WIDTH = ((CLOCK PERIOD –

JITTER p-p)/CLOCK PERIOD)  100%

0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5

0.5 0.6 DATA RATE – Gbps

1.0

35mV/DIV 100ps/DIV

VCC = 3.3V SEL = 3.3V

= 2V p-p

20dB ATTENUATION

= 25C

37mV/DIV 200ps/DIV

= 2.5V

SEL = 2.5V V

= 2V p-p

ADG3246

20dB ATTENUATION T

= 25C

TPC 19. Eye Width vs. Data Rate; PRBS 31

20dB

50.1mV/DIV

50ps/DIV

= 25C

ATTENUATION

= 3.3V

SEL = 3.3V

= 2V p-p

TPC 22. Jitter @ 1.244 Gbps, PRBS 31

TPC 20. Eye Pattern; 1.244 Gbps, V

= 3.3 V, PRBS 31

TPC 21. Eye Pattern; 1 Gbps,

= 2.5 V, PRBS 31

REV. 0

–7–

Page 8

ADG3246

For the following load circuit and waveforms, the notation that is used is VIN and V

ⱕ 2.5ns,

OUT

PULSE

GENERATOR

NOTE S PULSE GENERATOR FOR ALL PULSES: FREQUENCY ⱕ 10MHz. C

INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.

IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z

OF THE PULSE GENERATOR.

D.U.T.

Figure 1. Load Circuit

TIMING MEASUREMENT INFORMATION

VVand V V or V V and V V

====

IN A OUT B IN B OUT A

CONTROL INPUT BE

PLH

OUT

Figure 2. Propagation Delay

ⱕ 2.5ns,

OUT

2  V

SW1

GND

OUT

where

PHL

Test Conditions

Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC)VCC = 2.5 V ± 0.2 V (SEL = VCC)VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit

CONTROL INPUT BE

= 0V

VIN = V

500 500 500 W 300 150 150 mV 50 30 30 pF

1.5 0.9 0.9 V

DISABLE

PHZ

INH

PLZ

VL + V V

VH –V

Table III. Switch Position



TEST S1

t t

PLZ

PHZ

, t

PZL

PZH

2 ¥ V GND

SW1 @ 2V

OUT

SW1 @ GND

ENABLE

PZL

PZH

Figure 3. Enable and Disable Times

REV. 0–8–

Page 9

ADG3246

1.8V

OUT

2.5V

SWITCH

INPU T

SWITCH

OUTPUT

2.5V SUPPLY

SEL = 2.5V

BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation

Bus switches can be used to provide an ideal solution for interfacing between mixed voltage systems. The ADG3246 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V.

Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3246 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise.

3.3V

3.3V ADC

3.3V

ADG3246

2.5V

MICROPROCESSOR

Figure 4. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor

3.3 V to 2.5 V Translation

When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V

, the maximum output signal will be clamped to within a

to V

voltage threshold below the V

3.3V

supply.

3.3V

2.5V

ADG3246

2.5V

Figure 5. 3.3 V to 2.5 V Voltage Translation,

2.5V

SEL

= V

In this case, the output will be limited to 2.5 V, as shown in Figure 6.

OUT

2.5V

SWITCH

OUTPUT

Figure 6. 3.3 V to 2.5 V Voltage Translation,

SWITCH

INPU T

3.3V SUPPLY

SEL = 3.3V

3.3V

SEL

= V

This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices.

2.5 V to 1.8 V Translation

When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V

, the maximum output signal will, as before, be clamped

to V

to within a voltage threshold below the V

2.5V

ADG3246

Figure 7. 2.5 V to 1.8 V Voltage Translation,

supply.

1.8V

SEL

= V

In this case, the output will be limited to approximately 1.8 V, as shown in Figure 7.

Figure 8. 2.5 V to 1.8 V Voltage Translation,

SEL

= V

3.3 V to 1.8 V Translation

The ADG3246 offers the option of interfacing between a 3.3 V device and a 1.8 V device. This is possible through use of the

SEL pin. SEL pin: An active low control pin. SEL activates internal cir-

cuitry in the ADG3246 that allows voltage translation between

3.3 V devices and 1.8 V devices.

3.3V

Figure 9. 3.3 V to 1.8 V Voltage Translation,

ADG3246

1.8V

SEL

= 0 V

When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal will be clamped to 1.8 V, as shown in Figure 9. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to V

REV. 0

–9–

Page 10

ADG3246

OUT

1.8V

SWITCH

OUTPUT

Figure 10. 3.3 V to 1.8 V Voltage Translation,

Bus Isolation

A common requirement of bus architectures is low capacitance loading of the bus. Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. Because the ADG3246 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. The device isolates access to the bus, thus minimizing capacitance loading.

LOAD A

BUS SWITCH

LOCATION

LOAD B

Figure 11. Location of Bus Switched in a Bus Isolation Application

Hot Plug and Hot Swap Isolation

The ADG3246 is suitable for hot swap and hot plug applications. The output signal of the ADG3246 is limited to a voltage that is below the V

supply, as shown in Figures 6, 8, and 10. There-

fore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage.

In hot-plug applications, the system cannot be shutdown when new hardware is being added. To overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. The bus switch is turned off during hot plug. Figure 12 shows a typical example of this type of application.

SWITCH

INPU T

LOAD C

3.3V SUPPLY

SEL = 0V

3.3V

LOAD D

BACKPLANE

BUS/

SEL

= 0 V

CPU

RAM

ADG3246ADG3246

PLUG-IN CARD (1)

PLUG-IN CARD (2)

CARD I/O

Figure 12. ADG3246 in a Hot Plug Application

There are many systems that require the ability to handle hot swapping, such as docking stations, PCI boards for servers, and line cards for telecommunications switches. If the bus can be isolated prior to insertion or removal, then there is more control over the hot swap event. This isolation can be achieved using a bus switch. The bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the hot swap card must connect to the ground pin of the back plane before any other signal or power pins.

Analog Switching

Bus switches can be used in many analog switching applications; for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance and thus improved frequency performance than their analog counterparts. The bus switch channel itself consisting solely of an NMOS switch limits the operating voltage (see TPC 1 for a typical plot), but in many cases, this does not present an issue.

High Impedance During Power-Up/Power-Down

To ensure the high impedance state during power-up or powerdown, BE should be tied to V

through a pull-up resistor; the

minimum value of the resistor is determined by the currentsinking capability of the driver.

PACKAGE AND PINOUT

The ADG3246 is packaged in both a small 24-lead TSSOP or a tiny 24-lead LFCSP package. The area of the TSSOP option is

49.375 mm

, while the area of the LFCSP option is 16 mm2. This leads to a 67% savings in board space when using the LFCSP package compared with the TSSOP package. This makes the LFCSP option an excellent choice for space-constrained applications.

The ADG3246 in the TSSOP package offers a flowthrough pinout. The term flowthrough signifies that all the inputs are on opposite sides from the outputs. A flowthrough pinout simplifies the PCB layout.

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OUTLINE DIMENSIONS

24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm  4 mm Body

(CP-24)

Dimensions shown in millimeters

ADG3246

PIN 1

INDICATOR

1.00

0.90

0.85

0.25 REF

0.60 MAX

BOTTOM

VIEW

2.50 REF

0.25 MIN

12 MAX

SEATING PLANE

4.0

BSC SQ

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

TOP

VIEW

0.80 MAX

0.65 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

0.60 MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.50

0.40

0.30

24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

7.90

7.80

7.70

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MS-153AD

121

1.20

MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8 0

0.75

0.60

0.45

PIN 1 INDICATOR

2.25 SQ

1.70

0.75

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